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254 lines
6.8 KiB
254 lines
6.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Samsung SATA SerDes(PHY) driver |
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* |
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* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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* Authors: Girish K S <[email protected]> |
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* Yuvaraj Kumar C D <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/i2c.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/spinlock.h> |
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#include <linux/mfd/syscon.h> |
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#define SATAPHY_CONTROL_OFFSET 0x0724 |
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#define EXYNOS5_SATAPHY_PMU_ENABLE BIT(0) |
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#define EXYNOS5_SATA_RESET 0x4 |
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#define RESET_GLOBAL_RST_N BIT(0) |
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#define RESET_CMN_RST_N BIT(1) |
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#define RESET_CMN_BLOCK_RST_N BIT(2) |
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#define RESET_CMN_I2C_RST_N BIT(3) |
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#define RESET_TX_RX_PIPE_RST_N BIT(4) |
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#define RESET_TX_RX_BLOCK_RST_N BIT(5) |
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#define RESET_TX_RX_I2C_RST_N (BIT(6) | BIT(7)) |
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#define LINK_RESET 0xf0000 |
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#define EXYNOS5_SATA_MODE0 0x10 |
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#define SATA_SPD_GEN3 BIT(1) |
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#define EXYNOS5_SATA_CTRL0 0x14 |
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#define CTRL0_P0_PHY_CALIBRATED_SEL BIT(9) |
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#define CTRL0_P0_PHY_CALIBRATED BIT(8) |
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#define EXYNOS5_SATA_PHSATA_CTRLM 0xe0 |
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#define PHCTRLM_REF_RATE BIT(1) |
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#define PHCTRLM_HIGH_SPEED BIT(0) |
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#define EXYNOS5_SATA_PHSATA_STATM 0xf0 |
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#define PHSTATM_PLL_LOCKED BIT(0) |
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#define PHY_PLL_TIMEOUT (usecs_to_jiffies(1000)) |
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struct exynos_sata_phy { |
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struct phy *phy; |
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struct clk *phyclk; |
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void __iomem *regs; |
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struct regmap *pmureg; |
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struct i2c_client *client; |
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}; |
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static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit, |
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u32 status) |
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{ |
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unsigned long timeout = jiffies + PHY_PLL_TIMEOUT; |
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while (time_before(jiffies, timeout)) { |
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if ((readl(base + reg) & checkbit) == status) |
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return 0; |
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} |
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return -EFAULT; |
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} |
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static int exynos_sata_phy_power_on(struct phy *phy) |
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{ |
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struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy); |
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return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, |
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EXYNOS5_SATAPHY_PMU_ENABLE, true); |
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} |
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static int exynos_sata_phy_power_off(struct phy *phy) |
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{ |
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struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy); |
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return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, |
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EXYNOS5_SATAPHY_PMU_ENABLE, false); |
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} |
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static int exynos_sata_phy_init(struct phy *phy) |
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{ |
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u32 val = 0; |
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int ret = 0; |
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u8 buf[] = { 0x3a, 0x0b }; |
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struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy); |
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ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, |
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EXYNOS5_SATAPHY_PMU_ENABLE, true); |
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if (ret != 0) |
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dev_err(&sata_phy->phy->dev, "phy init failed\n"); |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); |
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val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N |
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| RESET_CMN_I2C_RST_N | RESET_TX_RX_PIPE_RST_N |
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| RESET_TX_RX_BLOCK_RST_N | RESET_TX_RX_I2C_RST_N; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); |
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val |= LINK_RESET; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); |
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val |= RESET_CMN_RST_N; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); |
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val &= ~PHCTRLM_REF_RATE; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); |
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/* High speed enable for Gen3 */ |
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val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); |
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val |= PHCTRLM_HIGH_SPEED; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0); |
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val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0); |
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val |= SATA_SPD_GEN3; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); |
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ret = i2c_master_send(sata_phy->client, buf, sizeof(buf)); |
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if (ret < 0) |
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return ret; |
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/* release cmu reset */ |
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val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); |
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val &= ~RESET_CMN_RST_N; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); |
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val |= RESET_CMN_RST_N; |
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writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); |
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ret = wait_for_reg_status(sata_phy->regs, |
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EXYNOS5_SATA_PHSATA_STATM, |
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PHSTATM_PLL_LOCKED, 1); |
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if (ret < 0) |
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dev_err(&sata_phy->phy->dev, |
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"PHY PLL locking failed\n"); |
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return ret; |
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} |
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static const struct phy_ops exynos_sata_phy_ops = { |
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.init = exynos_sata_phy_init, |
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.power_on = exynos_sata_phy_power_on, |
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.power_off = exynos_sata_phy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static int exynos_sata_phy_probe(struct platform_device *pdev) |
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{ |
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struct exynos_sata_phy *sata_phy; |
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struct device *dev = &pdev->dev; |
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struct phy_provider *phy_provider; |
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struct device_node *node; |
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int ret = 0; |
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sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL); |
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if (!sata_phy) |
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return -ENOMEM; |
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sata_phy->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(sata_phy->regs)) |
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return PTR_ERR(sata_phy->regs); |
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sata_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
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"samsung,syscon-phandle"); |
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if (IS_ERR(sata_phy->pmureg)) { |
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dev_err(dev, "syscon regmap lookup failed.\n"); |
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return PTR_ERR(sata_phy->pmureg); |
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} |
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node = of_parse_phandle(dev->of_node, |
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"samsung,exynos-sataphy-i2c-phandle", 0); |
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if (!node) |
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return -EINVAL; |
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sata_phy->client = of_find_i2c_device_by_node(node); |
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of_node_put(node); |
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if (!sata_phy->client) |
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return -EPROBE_DEFER; |
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dev_set_drvdata(dev, sata_phy); |
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sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); |
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if (IS_ERR(sata_phy->phyclk)) { |
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dev_err(dev, "failed to get clk for PHY\n"); |
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ret = PTR_ERR(sata_phy->phyclk); |
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goto put_dev; |
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} |
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ret = clk_prepare_enable(sata_phy->phyclk); |
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if (ret < 0) { |
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dev_err(dev, "failed to enable source clk\n"); |
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goto put_dev; |
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} |
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sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops); |
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if (IS_ERR(sata_phy->phy)) { |
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dev_err(dev, "failed to create PHY\n"); |
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ret = PTR_ERR(sata_phy->phy); |
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goto clk_disable; |
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} |
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phy_set_drvdata(sata_phy->phy, sata_phy); |
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phy_provider = devm_of_phy_provider_register(dev, |
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of_phy_simple_xlate); |
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if (IS_ERR(phy_provider)) { |
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ret = PTR_ERR(phy_provider); |
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goto clk_disable; |
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} |
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return 0; |
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clk_disable: |
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clk_disable_unprepare(sata_phy->phyclk); |
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put_dev: |
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put_device(&sata_phy->client->dev); |
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return ret; |
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} |
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static const struct of_device_id exynos_sata_phy_of_match[] = { |
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{ .compatible = "samsung,exynos5250-sata-phy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match); |
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static struct platform_driver exynos_sata_phy_driver = { |
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.probe = exynos_sata_phy_probe, |
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.driver = { |
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.of_match_table = exynos_sata_phy_of_match, |
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.name = "samsung,sata-phy", |
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.suppress_bind_attrs = true, |
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} |
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}; |
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module_platform_driver(exynos_sata_phy_driver); |
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MODULE_DESCRIPTION("Samsung SerDes PHY driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Girish K S <[email protected]>"); |
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MODULE_AUTHOR("Yuvaraj C D <[email protected]>");
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