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227 lines
7.8 KiB
227 lines
7.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018 MediaTek Inc. |
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* Author: Chunhui Dai <[email protected]> |
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*/ |
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#include "phy-mtk-hdmi.h" |
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#include "phy-mtk-io.h" |
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#define HDMI_CON0 0x00 |
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#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) |
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#define RG_HDMITX_EN_SER_MASK GENMASK(15, 12) |
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#define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16) |
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#define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20) |
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#define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24) |
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#define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28) |
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#define HDMI_CON1 0x04 |
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#define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18) |
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#define RG_HDMITX_PRED_IMP BIT(22) |
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#define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26) |
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#define HDMI_CON2 0x08 |
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#define RG_HDMITX_EN_TX_CKLDO BIT(0) |
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#define RG_HDMITX_EN_TX_POSDIV BIT(1) |
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#define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3) |
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#define RG_HDMITX_EN_MBIAS BIT(6) |
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#define RG_HDMITX_MBIAS_LPF_EN BIT(7) |
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#define HDMI_CON4 0x10 |
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#define RG_HDMITX_RESERVE_MASK GENMASK(31, 0) |
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#define HDMI_CON6 0x18 |
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#define RG_HTPLL_BR_MASK GENMASK(1, 0) |
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#define RG_HTPLL_BC_MASK GENMASK(3, 2) |
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#define RG_HTPLL_BP_MASK GENMASK(7, 4) |
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#define RG_HTPLL_IR_MASK GENMASK(11, 8) |
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#define RG_HTPLL_IC_MASK GENMASK(15, 12) |
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#define RG_HTPLL_POSDIV_MASK GENMASK(17, 16) |
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#define RG_HTPLL_PREDIV_MASK GENMASK(19, 18) |
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#define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20) |
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#define RG_HTPLL_RLH_EN BIT(22) |
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#define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24) |
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#define RG_HTPLL_EN BIT(31) |
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#define HDMI_CON7 0x1c |
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#define RG_HTPLL_AUTOK_EN BIT(23) |
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#define RG_HTPLL_DIVEN_MASK GENMASK(30, 28) |
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw) |
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{ |
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); |
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void __iomem *base = hdmi_phy->regs; |
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mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); |
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usleep_range(80, 100); |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); |
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usleep_range(80, 100); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); |
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usleep_range(80, 100); |
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return 0; |
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} |
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static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) |
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{ |
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); |
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void __iomem *base = hdmi_phy->regs; |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); |
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usleep_range(80, 100); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); |
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usleep_range(80, 100); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); |
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mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); |
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usleep_range(80, 100); |
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} |
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static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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return rate; |
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} |
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static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); |
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void __iomem *base = hdmi_phy->regs; |
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u32 pos_div; |
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if (rate <= 64000000) |
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pos_div = 3; |
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else if (rate <= 128000000) |
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pos_div = 2; |
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else |
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pos_div = 1; |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK); |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); |
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mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); |
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mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); |
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mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); |
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP); |
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK); |
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28); |
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mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); |
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mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa); |
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return 0; |
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} |
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static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); |
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unsigned long out_rate, val; |
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u32 tmp; |
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tmp = readl(hdmi_phy->regs + HDMI_CON6); |
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val = FIELD_GET(RG_HTPLL_PREDIV_MASK, tmp); |
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switch (val) { |
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case 0x00: |
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out_rate = parent_rate; |
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break; |
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case 0x01: |
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out_rate = parent_rate / 2; |
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break; |
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default: |
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out_rate = parent_rate / 4; |
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break; |
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} |
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val = FIELD_GET(RG_HTPLL_FBKDIV_MASK, tmp); |
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out_rate *= (val + 1) * 2; |
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tmp = readl(hdmi_phy->regs + HDMI_CON2); |
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val = FIELD_GET(RG_HDMITX_TX_POSDIV_MASK, tmp); |
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out_rate >>= val; |
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if (tmp & RG_HDMITX_EN_TX_POSDIV) |
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out_rate /= 5; |
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return out_rate; |
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} |
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static const struct clk_ops mtk_hdmi_phy_pll_ops = { |
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.prepare = mtk_hdmi_pll_prepare, |
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.unprepare = mtk_hdmi_pll_unprepare, |
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.set_rate = mtk_hdmi_pll_set_rate, |
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.round_rate = mtk_hdmi_pll_round_rate, |
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.recalc_rate = mtk_hdmi_pll_recalc_rate, |
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}; |
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static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) |
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{ |
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void __iomem *base = hdmi_phy->regs; |
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mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); |
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usleep_range(80, 100); |
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mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); |
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usleep_range(80, 100); |
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mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); |
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); |
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usleep_range(80, 100); |
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} |
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static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) |
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{ |
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void __iomem *base = hdmi_phy->regs; |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); |
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usleep_range(80, 100); |
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); |
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usleep_range(80, 100); |
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mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); |
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mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); |
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mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); |
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usleep_range(80, 100); |
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} |
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struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { |
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.flags = CLK_SET_RATE_GATE, |
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.pll_default_off = true, |
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.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, |
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.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, |
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.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, |
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}; |
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MODULE_AUTHOR("Chunhui Dai <[email protected]>"); |
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MODULE_DESCRIPTION("MediaTek HDMI PHY Driver"); |
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MODULE_LICENSE("GPL v2");
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