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255 lines
6.5 KiB
255 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/phy/phy-mipi-dphy.h> |
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#include <linux/platform_device.h> |
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#define DPHY_PMA_CMN(reg) (reg) |
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#define DPHY_PCS(reg) (0xb00 + (reg)) |
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#define DPHY_ISO(reg) (0xc00 + (reg)) |
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#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) |
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#define DPHY_CMN_RX_MODE_EN BIT(10) |
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#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) |
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#define DPHY_CMN_SSM_EN BIT(0) |
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#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 |
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#define DPHY_BAND_CFG DPHY_PCS(0x0) |
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#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) |
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#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) |
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#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) |
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#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa |
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#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) |
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#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa |
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#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) |
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#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) |
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#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) |
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#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) |
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#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) |
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#define DPHY_ISO_LANE_READY_BIT 0 |
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#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL |
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#define DPHY_LANES_MIN 1 |
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#define DPHY_LANES_MAX 4 |
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struct cdns_dphy_rx { |
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void __iomem *regs; |
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struct device *dev; |
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struct phy *phy; |
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}; |
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struct cdns_dphy_rx_band { |
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/* Rates are in Mbps. */ |
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unsigned int min_rate; |
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unsigned int max_rate; |
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}; |
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/* Order of bands is important since the index is the band number. */ |
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static const struct cdns_dphy_rx_band bands[] = { |
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{ 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 }, |
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{ 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 }, |
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{ 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 }, |
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{ 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 }, |
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{ 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 } |
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}; |
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static int cdns_dphy_rx_power_on(struct phy *phy) |
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{ |
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struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); |
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/* Start RX state machine. */ |
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writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | |
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FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, |
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DPHY_CMN_RX_BANDGAP_TIMER), |
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dphy->regs + DPHY_CMN_SSM); |
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return 0; |
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} |
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static int cdns_dphy_rx_power_off(struct phy *phy) |
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{ |
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struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); |
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writel(0, dphy->regs + DPHY_CMN_SSM); |
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return 0; |
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} |
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static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) |
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{ |
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unsigned int rate, i; |
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rate = hs_clk_rate / 1000000UL; |
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/* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ |
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rate *= 2; |
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if (rate < bands[0].min_rate) |
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return -EOPNOTSUPP; |
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for (i = 0; i < ARRAY_SIZE(bands); i++) |
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if (rate < bands[i].max_rate) |
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return i; |
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return -EOPNOTSUPP; |
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} |
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static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr, |
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unsigned int bit) |
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{ |
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u32 val; |
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return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, |
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DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); |
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} |
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static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, |
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unsigned int lanes) |
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{ |
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static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, |
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DPHY_ISO_DL_CTRL_L1, |
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DPHY_ISO_DL_CTRL_L2, |
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DPHY_ISO_DL_CTRL_L3}; |
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void __iomem *reg = dphy->regs; |
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unsigned int i; |
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int ret; |
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/* Clock lane */ |
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ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, |
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DPHY_ISO_LANE_READY_BIT); |
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if (ret) |
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return ret; |
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for (i = 0; i < lanes; i++) { |
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ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], |
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DPHY_ISO_LANE_READY_BIT); |
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if (ret) |
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return ret; |
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} |
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return 0; |
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} |
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static int cdns_dphy_rx_configure(struct phy *phy, |
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union phy_configure_opts *opts) |
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{ |
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struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); |
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unsigned int reg, lanes = opts->mipi_dphy.lanes; |
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int band_ctrl, ret; |
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/* Data lanes. Minimum one lane is mandatory. */ |
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if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) |
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return -EINVAL; |
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band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); |
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if (band_ctrl < 0) |
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return band_ctrl; |
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reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | |
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FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); |
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writel(reg, dphy->regs + DPHY_BAND_CFG); |
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/* |
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* Set the required power island phase 2 time. This is mandated by DPHY |
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* specs. |
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*/ |
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reg = DPHY_POWER_ISLAND_EN_DATA_VAL; |
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writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); |
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reg = DPHY_POWER_ISLAND_EN_CLK_VAL; |
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writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); |
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ret = cdns_dphy_rx_wait_lane_ready(dphy, lanes); |
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if (ret) { |
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dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode, |
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int submode, union phy_configure_opts *opts) |
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{ |
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int ret; |
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if (mode != PHY_MODE_MIPI_DPHY) |
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return -EINVAL; |
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ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); |
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if (ret < 0) |
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return ret; |
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return phy_mipi_dphy_config_validate(&opts->mipi_dphy); |
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} |
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static const struct phy_ops cdns_dphy_rx_ops = { |
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.power_on = cdns_dphy_rx_power_on, |
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.power_off = cdns_dphy_rx_power_off, |
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.configure = cdns_dphy_rx_configure, |
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.validate = cdns_dphy_rx_validate, |
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}; |
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static int cdns_dphy_rx_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct phy_provider *provider; |
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struct cdns_dphy_rx *dphy; |
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dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); |
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if (!dphy) |
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return -ENOMEM; |
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dev_set_drvdata(dev, dphy); |
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dphy->dev = dev; |
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dphy->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(dphy->regs)) |
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return PTR_ERR(dphy->regs); |
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dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); |
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if (IS_ERR(dphy->phy)) { |
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dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(dphy->phy)); |
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return PTR_ERR(dphy->phy); |
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} |
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phy_set_drvdata(dphy->phy, dphy); |
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(provider)) { |
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dev_err(dev, "Failed to register PHY provider: %ld\n", |
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PTR_ERR(provider)); |
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return PTR_ERR(provider); |
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} |
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return 0; |
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} |
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static const struct of_device_id cdns_dphy_rx_of_match[] = { |
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{ .compatible = "cdns,dphy-rx" }, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match); |
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static struct platform_driver cdns_dphy_rx_platform_driver = { |
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.probe = cdns_dphy_rx_probe, |
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.driver = { |
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.name = "cdns-mipi-dphy-rx", |
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.of_match_table = cdns_dphy_rx_of_match, |
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}, |
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}; |
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module_platform_driver(cdns_dphy_rx_platform_driver); |
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MODULE_AUTHOR("Pratyush Yadav <[email protected]>"); |
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MODULE_DESCRIPTION("Cadence D-PHY Rx Driver"); |
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MODULE_LICENSE("GPL");
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