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323 lines
8.2 KiB
323 lines
8.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* RISC-V performance counter support. |
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* |
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* Copyright (C) 2021 Western Digital Corporation or its affiliates. |
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* |
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* This implementation is based on old RISC-V perf and ARM perf event code |
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* which are in turn based on sparc64 and x86 code. |
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*/ |
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#include <linux/cpumask.h> |
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#include <linux/irq.h> |
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#include <linux/irqdesc.h> |
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#include <linux/perf/riscv_pmu.h> |
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#include <linux/printk.h> |
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#include <linux/smp.h> |
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#include <asm/sbi.h> |
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static unsigned long csr_read_num(int csr_num) |
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{ |
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#define switchcase_csr_read(__csr_num, __val) {\ |
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case __csr_num: \ |
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__val = csr_read(__csr_num); \ |
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break; } |
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#define switchcase_csr_read_2(__csr_num, __val) {\ |
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switchcase_csr_read(__csr_num + 0, __val) \ |
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switchcase_csr_read(__csr_num + 1, __val)} |
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#define switchcase_csr_read_4(__csr_num, __val) {\ |
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switchcase_csr_read_2(__csr_num + 0, __val) \ |
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switchcase_csr_read_2(__csr_num + 2, __val)} |
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#define switchcase_csr_read_8(__csr_num, __val) {\ |
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switchcase_csr_read_4(__csr_num + 0, __val) \ |
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switchcase_csr_read_4(__csr_num + 4, __val)} |
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#define switchcase_csr_read_16(__csr_num, __val) {\ |
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switchcase_csr_read_8(__csr_num + 0, __val) \ |
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switchcase_csr_read_8(__csr_num + 8, __val)} |
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#define switchcase_csr_read_32(__csr_num, __val) {\ |
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switchcase_csr_read_16(__csr_num + 0, __val) \ |
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switchcase_csr_read_16(__csr_num + 16, __val)} |
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unsigned long ret = 0; |
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switch (csr_num) { |
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switchcase_csr_read_32(CSR_CYCLE, ret) |
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switchcase_csr_read_32(CSR_CYCLEH, ret) |
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default : |
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break; |
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} |
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return ret; |
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#undef switchcase_csr_read_32 |
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#undef switchcase_csr_read_16 |
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#undef switchcase_csr_read_8 |
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#undef switchcase_csr_read_4 |
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#undef switchcase_csr_read_2 |
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#undef switchcase_csr_read |
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} |
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/* |
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* Read the CSR of a corresponding counter. |
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*/ |
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unsigned long riscv_pmu_ctr_read_csr(unsigned long csr) |
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{ |
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if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H || |
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(csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) { |
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pr_err("Invalid performance counter csr %lx\n", csr); |
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return -EINVAL; |
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} |
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return csr_read_num(csr); |
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} |
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u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event) |
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{ |
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int cwidth; |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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if (!rvpmu->ctr_get_width) |
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/** |
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* If the pmu driver doesn't support counter width, set it to default |
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* maximum allowed by the specification. |
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*/ |
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cwidth = 63; |
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else { |
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if (hwc->idx == -1) |
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/* Handle init case where idx is not initialized yet */ |
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cwidth = rvpmu->ctr_get_width(0); |
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else |
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cwidth = rvpmu->ctr_get_width(hwc->idx); |
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} |
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return GENMASK_ULL(cwidth, 0); |
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} |
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u64 riscv_pmu_event_update(struct perf_event *event) |
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{ |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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u64 prev_raw_count, new_raw_count; |
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unsigned long cmask; |
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u64 oldval, delta; |
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if (!rvpmu->ctr_read) |
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return 0; |
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cmask = riscv_pmu_ctr_get_width_mask(event); |
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do { |
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prev_raw_count = local64_read(&hwc->prev_count); |
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new_raw_count = rvpmu->ctr_read(event); |
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oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
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new_raw_count); |
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} while (oldval != prev_raw_count); |
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delta = (new_raw_count - prev_raw_count) & cmask; |
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local64_add(delta, &event->count); |
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local64_sub(delta, &hwc->period_left); |
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return delta; |
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} |
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void riscv_pmu_stop(struct perf_event *event, int flags) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); |
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if (!(hwc->state & PERF_HES_STOPPED)) { |
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if (rvpmu->ctr_stop) { |
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rvpmu->ctr_stop(event, 0); |
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hwc->state |= PERF_HES_STOPPED; |
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} |
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riscv_pmu_event_update(event); |
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hwc->state |= PERF_HES_UPTODATE; |
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} |
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} |
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int riscv_pmu_event_set_period(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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s64 left = local64_read(&hwc->period_left); |
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s64 period = hwc->sample_period; |
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int overflow = 0; |
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uint64_t max_period = riscv_pmu_ctr_get_width_mask(event); |
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if (unlikely(left <= -period)) { |
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left = period; |
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local64_set(&hwc->period_left, left); |
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hwc->last_period = period; |
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overflow = 1; |
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} |
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if (unlikely(left <= 0)) { |
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left += period; |
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local64_set(&hwc->period_left, left); |
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hwc->last_period = period; |
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overflow = 1; |
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} |
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/* |
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* Limit the maximum period to prevent the counter value |
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* from overtaking the one we are about to program. In |
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* effect we are reducing max_period to account for |
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* interrupt latency (and we are being very conservative). |
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*/ |
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if (left > (max_period >> 1)) |
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left = (max_period >> 1); |
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local64_set(&hwc->prev_count, (u64)-left); |
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return overflow; |
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} |
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void riscv_pmu_start(struct perf_event *event, int flags) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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uint64_t max_period = riscv_pmu_ctr_get_width_mask(event); |
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u64 init_val; |
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
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return; |
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if (flags & PERF_EF_RELOAD) |
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); |
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hwc->state = 0; |
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riscv_pmu_event_set_period(event); |
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init_val = local64_read(&hwc->prev_count) & max_period; |
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rvpmu->ctr_start(event, init_val); |
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perf_event_update_userpage(event); |
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} |
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static int riscv_pmu_add(struct perf_event *event, int flags) |
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{ |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); |
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struct hw_perf_event *hwc = &event->hw; |
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int idx; |
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idx = rvpmu->ctr_get_idx(event); |
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if (idx < 0) |
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return idx; |
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hwc->idx = idx; |
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cpuc->events[idx] = event; |
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cpuc->n_events++; |
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
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if (flags & PERF_EF_START) |
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riscv_pmu_start(event, PERF_EF_RELOAD); |
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/* Propagate our changes to the userspace mapping. */ |
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perf_event_update_userpage(event); |
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return 0; |
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} |
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static void riscv_pmu_del(struct perf_event *event, int flags) |
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{ |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); |
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struct hw_perf_event *hwc = &event->hw; |
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riscv_pmu_stop(event, PERF_EF_UPDATE); |
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cpuc->events[hwc->idx] = NULL; |
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/* The firmware need to reset the counter mapping */ |
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if (rvpmu->ctr_stop) |
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rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET); |
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cpuc->n_events--; |
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if (rvpmu->ctr_clear_idx) |
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rvpmu->ctr_clear_idx(event); |
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perf_event_update_userpage(event); |
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hwc->idx = -1; |
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} |
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static void riscv_pmu_read(struct perf_event *event) |
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{ |
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riscv_pmu_event_update(event); |
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} |
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static int riscv_pmu_event_init(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); |
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int mapped_event; |
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u64 event_config = 0; |
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uint64_t cmask; |
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hwc->flags = 0; |
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mapped_event = rvpmu->event_map(event, &event_config); |
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if (mapped_event < 0) { |
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pr_debug("event %x:%llx not supported\n", event->attr.type, |
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event->attr.config); |
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return mapped_event; |
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} |
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/* |
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* idx is set to -1 because the index of a general event should not be |
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* decided until binding to some counter in pmu->add(). |
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* config will contain the information about counter CSR |
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* the idx will contain the counter index |
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*/ |
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hwc->config = event_config; |
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hwc->idx = -1; |
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hwc->event_base = mapped_event; |
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if (!is_sampling_event(event)) { |
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/* |
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* For non-sampling runs, limit the sample_period to half |
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* of the counter width. That way, the new counter value |
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* is far less likely to overtake the previous one unless |
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* you have some serious IRQ latency issues. |
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*/ |
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cmask = riscv_pmu_ctr_get_width_mask(event); |
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hwc->sample_period = cmask >> 1; |
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hwc->last_period = hwc->sample_period; |
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local64_set(&hwc->period_left, hwc->sample_period); |
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} |
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return 0; |
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} |
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struct riscv_pmu *riscv_pmu_alloc(void) |
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{ |
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struct riscv_pmu *pmu; |
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int cpuid, i; |
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struct cpu_hw_events *cpuc; |
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pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); |
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if (!pmu) |
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goto out; |
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pmu->hw_events = alloc_percpu_gfp(struct cpu_hw_events, GFP_KERNEL); |
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if (!pmu->hw_events) { |
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pr_info("failed to allocate per-cpu PMU data.\n"); |
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goto out_free_pmu; |
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} |
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for_each_possible_cpu(cpuid) { |
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cpuc = per_cpu_ptr(pmu->hw_events, cpuid); |
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cpuc->n_events = 0; |
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for (i = 0; i < RISCV_MAX_COUNTERS; i++) |
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cpuc->events[i] = NULL; |
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} |
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pmu->pmu = (struct pmu) { |
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.event_init = riscv_pmu_event_init, |
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.add = riscv_pmu_add, |
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.del = riscv_pmu_del, |
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.start = riscv_pmu_start, |
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.stop = riscv_pmu_stop, |
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.read = riscv_pmu_read, |
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}; |
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return pmu; |
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out_free_pmu: |
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kfree(pmu); |
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out: |
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return NULL; |
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}
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