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269 lines
8.0 KiB
269 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* ZD1211 USB-WLAN driver for Linux |
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* |
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* Copyright (C) 2005-2007 Ulrich Kunitz <[email protected]> |
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* Copyright (C) 2006-2007 Daniel Drake <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include "zd_rf.h" |
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#include "zd_usb.h" |
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#include "zd_chip.h" |
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static const u32 rf2959_table[][2] = { |
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RF_CHANNEL( 1) = { 0x181979, 0x1e6666 }, |
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RF_CHANNEL( 2) = { 0x181989, 0x1e6666 }, |
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RF_CHANNEL( 3) = { 0x181999, 0x1e6666 }, |
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RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 }, |
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RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 }, |
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RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 }, |
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RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 }, |
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RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 }, |
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RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 }, |
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RF_CHANNEL(10) = { 0x181a09, 0x1e6666 }, |
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RF_CHANNEL(11) = { 0x181a19, 0x1e6666 }, |
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RF_CHANNEL(12) = { 0x181a29, 0x1e6666 }, |
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RF_CHANNEL(13) = { 0x181a39, 0x1e6666 }, |
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RF_CHANNEL(14) = { 0x181a60, 0x1c0000 }, |
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}; |
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#if 0 |
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static int bits(u32 rw, int from, int to) |
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{ |
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rw &= ~(0xffffffffU << (to+1)); |
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rw >>= from; |
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return rw; |
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} |
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static int bit(u32 rw, int bit) |
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{ |
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return bits(rw, bit, bit); |
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} |
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static void dump_regwrite(u32 rw) |
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{ |
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int reg = bits(rw, 18, 22); |
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int rw_flag = bits(rw, 23, 23); |
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PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag); |
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switch (reg) { |
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case 0: |
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PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d" |
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" if_vco_reg_en %d if_vga_en %d", |
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bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1), |
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bit(rw, 0)); |
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break; |
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case 1: |
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PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d" |
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" cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d" |
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" ifloopc %d dac1 %d", |
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bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14), |
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bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10), |
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bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3)); |
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break; |
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case 2: |
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PDEBUG("reg2 IFPLL2 n1 %d num1 %d", |
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bits(rw, 6, 17), bits(rw, 0, 5)); |
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break; |
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case 3: |
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PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17)); |
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break; |
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case 4: |
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PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d", |
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bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3)); |
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break; |
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case 5: |
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PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d" |
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" pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d" |
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" dac %d", |
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bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14), |
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bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10), |
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bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3)); |
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break; |
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case 6: |
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PDEBUG("reg6 RFPLL2 n %d num %d", |
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bits(rw, 6, 17), bits(rw, 0, 5)); |
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break; |
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case 7: |
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PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17)); |
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break; |
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case 8: |
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PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d", |
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bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3)); |
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break; |
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case 9: |
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PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d", |
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bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7), |
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bits(rw, 0, 2)); |
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break; |
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case 10: |
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PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d" |
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" rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d" |
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" intbiasen %d tybypass %d", |
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bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14), |
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bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2), |
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bit(rw, 1), bit(rw, 0)); |
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break; |
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case 11: |
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PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d" |
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" tx_delay %d", |
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bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8), |
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bits(rw, 0, 2)); |
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break; |
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case 12: |
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PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d", |
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bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5)); |
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break; |
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case 13: |
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PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d" |
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" lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d" |
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" rf_biasvco %d", |
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bit(rw, 17), bit(rw, 16), bit(rw, 15), |
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bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4), |
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bits(rw, 0, 2)); |
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break; |
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case 14: |
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PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d" |
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" tx_acal %d tx_pcal %d", |
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bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8), |
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bits(rw, 0, 3)); |
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break; |
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} |
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} |
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#endif /* 0 */ |
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static int rf2959_init_hw(struct zd_rf *rf) |
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{ |
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int r; |
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struct zd_chip *chip = zd_rf_to_chip(rf); |
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static const struct zd_ioreq16 ioreqs[] = { |
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{ ZD_CR2, 0x1E }, { ZD_CR9, 0x20 }, { ZD_CR10, 0x89 }, |
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{ ZD_CR11, 0x00 }, { ZD_CR15, 0xD0 }, { ZD_CR17, 0x68 }, |
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{ ZD_CR19, 0x4a }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0E }, |
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{ ZD_CR23, 0x48 }, |
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/* normal size for cca threshold */ |
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{ ZD_CR24, 0x14 }, |
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/* { ZD_CR24, 0x20 }, */ |
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{ ZD_CR26, 0x90 }, { ZD_CR27, 0x30 }, { ZD_CR29, 0x20 }, |
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{ ZD_CR31, 0xb2 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x28 }, |
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{ ZD_CR38, 0x30 }, { ZD_CR34, 0x0f }, { ZD_CR35, 0xF0 }, |
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{ ZD_CR41, 0x2a }, { ZD_CR46, 0x7F }, { ZD_CR47, 0x1E }, |
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{ ZD_CR51, 0xc5 }, { ZD_CR52, 0xc5 }, { ZD_CR53, 0xc5 }, |
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{ ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, |
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{ ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 }, |
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{ ZD_CR85, 0x00 }, { ZD_CR86, 0x10 }, { ZD_CR87, 0x2A }, |
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{ ZD_CR88, 0x10 }, { ZD_CR89, 0x24 }, { ZD_CR90, 0x18 }, |
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/* { ZD_CR91, 0x18 }, */ |
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/* should solve continuous CTS frame problems */ |
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{ ZD_CR91, 0x00 }, |
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{ ZD_CR92, 0x0a }, { ZD_CR93, 0x00 }, { ZD_CR94, 0x01 }, |
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{ ZD_CR95, 0x00 }, { ZD_CR96, 0x40 }, { ZD_CR97, 0x37 }, |
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{ ZD_CR98, 0x05 }, { ZD_CR99, 0x28 }, { ZD_CR100, 0x00 }, |
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{ ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, |
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{ ZD_CR104, 0x18 }, { ZD_CR105, 0x12 }, |
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/* normal size */ |
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{ ZD_CR106, 0x1a }, |
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/* { ZD_CR106, 0x22 }, */ |
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{ ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 }, |
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{ ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, |
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{ ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 }, |
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{ ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 }, |
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{ ZD_CR119, 0x16 }, |
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/* no TX continuation */ |
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{ ZD_CR122, 0x00 }, |
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/* { ZD_CR122, 0xff }, */ |
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{ ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 }, |
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{ ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB }, |
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{ ZD_CR170, 0xBB }, |
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}; |
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static const u32 rv[] = { |
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0x000007, /* REG0(CFG1) */ |
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0x07dd43, /* REG1(IFPLL1) */ |
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0x080959, /* REG2(IFPLL2) */ |
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0x0e6666, |
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0x116a57, /* REG4 */ |
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0x17dd43, /* REG5 */ |
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0x1819f9, /* REG6 */ |
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0x1e6666, |
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0x214554, |
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0x25e7fa, |
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0x27fffa, |
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/* The Zydas driver somehow forgets to set this value. It's |
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* only set for Japan. We are using internal power control |
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* for now. |
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*/ |
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0x294128, /* internal power */ |
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/* 0x28252c, */ /* External control TX power */ |
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/* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */ |
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0x2c0000, |
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0x300000, |
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0x340000, /* REG13(0xD) */ |
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0x381e0f, /* REG14(0xE) */ |
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/* Bogus, RF2959's data sheet doesn't know register 27, which is |
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* actually referenced here. The commented 0x11 is 17. |
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*/ |
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0x6c180f, /* REG27(0x11) */ |
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}; |
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r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
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if (r) |
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return r; |
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return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); |
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} |
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static int rf2959_set_channel(struct zd_rf *rf, u8 channel) |
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{ |
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int i, r; |
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const u32 *rv = rf2959_table[channel-1]; |
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struct zd_chip *chip = zd_rf_to_chip(rf); |
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for (i = 0; i < 2; i++) { |
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r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS); |
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if (r) |
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return r; |
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} |
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return 0; |
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} |
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static int rf2959_switch_radio_on(struct zd_rf *rf) |
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{ |
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static const struct zd_ioreq16 ioreqs[] = { |
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{ ZD_CR10, 0x89 }, |
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{ ZD_CR11, 0x00 }, |
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}; |
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struct zd_chip *chip = zd_rf_to_chip(rf); |
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
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} |
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static int rf2959_switch_radio_off(struct zd_rf *rf) |
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{ |
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static const struct zd_ioreq16 ioreqs[] = { |
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{ ZD_CR10, 0x15 }, |
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{ ZD_CR11, 0x81 }, |
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}; |
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struct zd_chip *chip = zd_rf_to_chip(rf); |
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
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} |
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int zd_rf_init_rf2959(struct zd_rf *rf) |
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{ |
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struct zd_chip *chip = zd_rf_to_chip(rf); |
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if (zd_chip_is_zd1211b(chip)) { |
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dev_err(zd_chip_dev(chip), |
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"RF2959 is currently not supported for ZD1211B" |
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" devices\n"); |
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return -ENODEV; |
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} |
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rf->init_hw = rf2959_init_hw; |
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rf->set_channel = rf2959_set_channel; |
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rf->switch_radio_on = rf2959_switch_radio_on; |
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rf->switch_radio_off = rf2959_switch_radio_off; |
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return 0; |
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}
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