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247 lines
5.8 KiB
247 lines
5.8 KiB
/* |
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* NAND support for Marvell Orion SoC platforms |
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* |
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* Tzachi Perelstein <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/of.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include <linux/platform_data/mtd-orion_nand.h> |
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struct orion_nand_info { |
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struct nand_controller controller; |
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struct nand_chip chip; |
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struct clk *clk; |
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}; |
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static void orion_nand_cmd_ctrl(struct nand_chip *nc, int cmd, |
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unsigned int ctrl) |
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{ |
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struct orion_nand_data *board = nand_get_controller_data(nc); |
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u32 offs; |
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if (cmd == NAND_CMD_NONE) |
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return; |
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if (ctrl & NAND_CLE) |
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offs = (1 << board->cle); |
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else if (ctrl & NAND_ALE) |
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offs = (1 << board->ale); |
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else |
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return; |
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if (nc->options & NAND_BUSWIDTH_16) |
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offs <<= 1; |
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writeb(cmd, nc->legacy.IO_ADDR_W + offs); |
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} |
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static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len) |
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{ |
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void __iomem *io_base = chip->legacy.IO_ADDR_R; |
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#if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5 |
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uint64_t *buf64; |
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#endif |
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int i = 0; |
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while (len && (unsigned long)buf & 7) { |
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*buf++ = readb(io_base); |
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len--; |
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} |
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#if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5 |
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buf64 = (uint64_t *)buf; |
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while (i < len/8) { |
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/* |
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* Since GCC has no proper constraint (PR 43518) |
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* force x variable to r2/r3 registers as ldrd instruction |
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* requires first register to be even. |
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*/ |
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register uint64_t x asm ("r2"); |
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asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); |
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buf64[i++] = x; |
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} |
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i *= 8; |
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#else |
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readsl(io_base, buf, len/4); |
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i = len / 4 * 4; |
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#endif |
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while (i < len) |
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buf[i++] = readb(io_base); |
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} |
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static int orion_nand_attach_chip(struct nand_chip *chip) |
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{ |
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if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && |
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chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) |
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chip->ecc.algo = NAND_ECC_ALGO_HAMMING; |
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return 0; |
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} |
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static const struct nand_controller_ops orion_nand_ops = { |
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.attach_chip = orion_nand_attach_chip, |
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}; |
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static int __init orion_nand_probe(struct platform_device *pdev) |
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{ |
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struct orion_nand_info *info; |
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struct mtd_info *mtd; |
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struct nand_chip *nc; |
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struct orion_nand_data *board; |
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struct resource *res; |
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void __iomem *io_base; |
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int ret = 0; |
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u32 val = 0; |
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info = devm_kzalloc(&pdev->dev, |
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sizeof(struct orion_nand_info), |
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GFP_KERNEL); |
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if (!info) |
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return -ENOMEM; |
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nc = &info->chip; |
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mtd = nand_to_mtd(nc); |
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nand_controller_init(&info->controller); |
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info->controller.ops = &orion_nand_ops; |
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nc->controller = &info->controller; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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io_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(io_base)) |
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return PTR_ERR(io_base); |
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if (pdev->dev.of_node) { |
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board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data), |
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GFP_KERNEL); |
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if (!board) |
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return -ENOMEM; |
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if (!of_property_read_u32(pdev->dev.of_node, "cle", &val)) |
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board->cle = (u8)val; |
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else |
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board->cle = 0; |
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if (!of_property_read_u32(pdev->dev.of_node, "ale", &val)) |
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board->ale = (u8)val; |
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else |
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board->ale = 1; |
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if (!of_property_read_u32(pdev->dev.of_node, |
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"bank-width", &val)) |
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board->width = (u8)val * 8; |
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else |
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board->width = 8; |
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if (!of_property_read_u32(pdev->dev.of_node, |
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"chip-delay", &val)) |
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board->chip_delay = (u8)val; |
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} else { |
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board = dev_get_platdata(&pdev->dev); |
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} |
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mtd->dev.parent = &pdev->dev; |
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nand_set_controller_data(nc, board); |
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nand_set_flash_node(nc, pdev->dev.of_node); |
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nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base; |
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nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl; |
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nc->legacy.read_buf = orion_nand_read_buf; |
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if (board->chip_delay) |
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nc->legacy.chip_delay = board->chip_delay; |
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WARN(board->width > 16, |
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"%d bit bus width out of range", |
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board->width); |
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if (board->width == 16) |
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nc->options |= NAND_BUSWIDTH_16; |
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platform_set_drvdata(pdev, info); |
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/* Not all platforms can gate the clock, so it is optional. */ |
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info->clk = devm_clk_get_optional(&pdev->dev, NULL); |
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if (IS_ERR(info->clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), |
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"failed to get clock!\n"); |
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ret = clk_prepare_enable(info->clk); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to prepare clock!\n"); |
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return ret; |
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} |
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/* |
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* This driver assumes that the default ECC engine should be TYPE_SOFT. |
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* Set ->engine_type before registering the NAND devices in order to |
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* provide a driver specific default value. |
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*/ |
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nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; |
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ret = nand_scan(nc, 1); |
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if (ret) |
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goto no_dev; |
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mtd->name = "orion_nand"; |
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ret = mtd_device_register(mtd, board->parts, board->nr_parts); |
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if (ret) { |
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nand_cleanup(nc); |
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goto no_dev; |
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} |
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return 0; |
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no_dev: |
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clk_disable_unprepare(info->clk); |
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return ret; |
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} |
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static int orion_nand_remove(struct platform_device *pdev) |
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{ |
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struct orion_nand_info *info = platform_get_drvdata(pdev); |
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struct nand_chip *chip = &info->chip; |
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int ret; |
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ret = mtd_device_unregister(nand_to_mtd(chip)); |
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WARN_ON(ret); |
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nand_cleanup(chip); |
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clk_disable_unprepare(info->clk); |
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return 0; |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id orion_nand_of_match_table[] = { |
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{ .compatible = "marvell,orion-nand", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, orion_nand_of_match_table); |
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#endif |
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static struct platform_driver orion_nand_driver = { |
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.remove = orion_nand_remove, |
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.driver = { |
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.name = "orion_nand", |
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.of_match_table = of_match_ptr(orion_nand_of_match_table), |
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}, |
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}; |
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module_platform_driver_probe(orion_nand_driver, orion_nand_probe); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Tzachi Perelstein"); |
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MODULE_DESCRIPTION("NAND glue for Orion platforms"); |
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MODULE_ALIAS("platform:orion_nand");
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