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277 lines
6.7 KiB
277 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Overview: |
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* Platform independent driver for NDFC (NanD Flash Controller) |
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* integrated into EP440 cores |
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* |
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* Ported to an OF platform driver by Sean MacLennan |
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* |
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* The NDFC supports multiple chips, but this driver only supports a |
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* single chip since I do not have access to any boards with |
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* multiple chips. |
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* |
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* Author: Thomas Gleixner |
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* |
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* Copyright 2006 IBM |
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* Copyright 2008 PIKA Technologies |
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* Sean MacLennan <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/mtd/ndfc.h> |
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#include <linux/slab.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <asm/io.h> |
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#define NDFC_MAX_CS 4 |
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struct ndfc_controller { |
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struct platform_device *ofdev; |
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void __iomem *ndfcbase; |
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struct nand_chip chip; |
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int chip_select; |
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struct nand_controller ndfc_control; |
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}; |
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static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; |
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static void ndfc_select_chip(struct nand_chip *nchip, int chip) |
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{ |
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uint32_t ccr; |
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struct ndfc_controller *ndfc = nand_get_controller_data(nchip); |
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ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
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if (chip >= 0) { |
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ccr &= ~NDFC_CCR_BS_MASK; |
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ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
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} else |
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ccr |= NDFC_CCR_RESET_CE; |
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
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} |
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static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl) |
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{ |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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if (cmd == NAND_CMD_NONE) |
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return; |
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if (ctrl & NAND_CLE) |
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writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
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else |
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writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
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} |
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static int ndfc_ready(struct nand_chip *chip) |
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{ |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
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} |
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static void ndfc_enable_hwecc(struct nand_chip *chip, int mode) |
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{ |
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uint32_t ccr; |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
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ccr |= NDFC_CCR_RESET_ECC; |
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
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wmb(); |
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} |
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static int ndfc_calculate_ecc(struct nand_chip *chip, |
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const u_char *dat, u_char *ecc_code) |
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{ |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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uint32_t ecc; |
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uint8_t *p = (uint8_t *)&ecc; |
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wmb(); |
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ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
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/* The NDFC uses Smart Media (SMC) bytes order */ |
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ecc_code[0] = p[1]; |
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ecc_code[1] = p[2]; |
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ecc_code[2] = p[3]; |
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return 0; |
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} |
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/* |
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* Speedups for buffer read/write/verify |
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* |
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* NDFC allows 32bit read/write of data. So we can speed up the buffer |
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* functions. No further checking, as nand_base will always read/write |
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* page aligned. |
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*/ |
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static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) |
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{ |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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uint32_t *p = (uint32_t *) buf; |
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for(;len > 0; len -= 4) |
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*p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
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} |
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static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) |
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{ |
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struct ndfc_controller *ndfc = nand_get_controller_data(chip); |
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uint32_t *p = (uint32_t *) buf; |
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for(;len > 0; len -= 4) |
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out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
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} |
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/* |
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* Initialize chip structure |
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*/ |
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static int ndfc_chip_init(struct ndfc_controller *ndfc, |
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struct device_node *node) |
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{ |
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struct device_node *flash_np; |
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struct nand_chip *chip = &ndfc->chip; |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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int ret; |
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chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; |
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chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; |
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chip->legacy.cmd_ctrl = ndfc_hwcontrol; |
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chip->legacy.dev_ready = ndfc_ready; |
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chip->legacy.select_chip = ndfc_select_chip; |
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chip->legacy.chip_delay = 50; |
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chip->controller = &ndfc->ndfc_control; |
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chip->legacy.read_buf = ndfc_read_buf; |
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chip->legacy.write_buf = ndfc_write_buf; |
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chip->ecc.correct = rawnand_sw_hamming_correct; |
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chip->ecc.hwctl = ndfc_enable_hwecc; |
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chip->ecc.calculate = ndfc_calculate_ecc; |
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chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; |
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chip->ecc.size = 256; |
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chip->ecc.bytes = 3; |
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chip->ecc.strength = 1; |
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nand_set_controller_data(chip, ndfc); |
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mtd->dev.parent = &ndfc->ofdev->dev; |
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flash_np = of_get_next_child(node, NULL); |
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if (!flash_np) |
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return -ENODEV; |
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nand_set_flash_node(chip, flash_np); |
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mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev), |
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flash_np); |
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if (!mtd->name) { |
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ret = -ENOMEM; |
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goto err; |
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} |
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ret = nand_scan(chip, 1); |
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if (ret) |
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goto err; |
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ret = mtd_device_register(mtd, NULL, 0); |
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err: |
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of_node_put(flash_np); |
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if (ret) |
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kfree(mtd->name); |
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return ret; |
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} |
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static int ndfc_probe(struct platform_device *ofdev) |
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{ |
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struct ndfc_controller *ndfc; |
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const __be32 *reg; |
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u32 ccr; |
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u32 cs; |
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int err, len; |
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/* Read the reg property to get the chip select */ |
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reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
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if (reg == NULL || len != 12) { |
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dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); |
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return -ENOENT; |
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} |
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cs = be32_to_cpu(reg[0]); |
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if (cs >= NDFC_MAX_CS) { |
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dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); |
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return -EINVAL; |
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} |
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ndfc = &ndfc_ctrl[cs]; |
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ndfc->chip_select = cs; |
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nand_controller_init(&ndfc->ndfc_control); |
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ndfc->ofdev = ofdev; |
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dev_set_drvdata(&ofdev->dev, ndfc); |
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ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
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if (!ndfc->ndfcbase) { |
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dev_err(&ofdev->dev, "failed to get memory\n"); |
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return -EIO; |
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} |
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ccr = NDFC_CCR_BS(ndfc->chip_select); |
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/* It is ok if ccr does not exist - just default to 0 */ |
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reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
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if (reg) |
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ccr |= be32_to_cpup(reg); |
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
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/* Set the bank settings if given */ |
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reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
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if (reg) { |
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int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); |
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out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); |
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} |
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err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
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if (err) { |
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iounmap(ndfc->ndfcbase); |
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return err; |
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} |
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return 0; |
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} |
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static int ndfc_remove(struct platform_device *ofdev) |
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{ |
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struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
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struct nand_chip *chip = &ndfc->chip; |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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int ret; |
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ret = mtd_device_unregister(mtd); |
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WARN_ON(ret); |
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nand_cleanup(chip); |
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kfree(mtd->name); |
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return 0; |
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} |
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static const struct of_device_id ndfc_match[] = { |
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{ .compatible = "ibm,ndfc", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, ndfc_match); |
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static struct platform_driver ndfc_driver = { |
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.driver = { |
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.name = "ndfc", |
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.of_match_table = ndfc_match, |
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}, |
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.probe = ndfc_probe, |
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.remove = ndfc_remove, |
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}; |
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module_platform_driver(ndfc_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Thomas Gleixner <[email protected]>"); |
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MODULE_DESCRIPTION("OF Platform driver for NDFC");
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