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108 lines
2.8 KiB
108 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2016 Marvell, All Rights Reserved. |
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* |
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* Author: Hu Ziji <[email protected]> |
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* Date: 2016-8-24 |
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*/ |
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#ifndef SDHCI_XENON_H_ |
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#define SDHCI_XENON_H_ |
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/* Register Offset of Xenon SDHC self-defined register */ |
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#define XENON_SYS_CFG_INFO 0x0104 |
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#define XENON_SLOT_TYPE_SDIO_SHIFT 24 |
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#define XENON_NR_SUPPORTED_SLOT_MASK 0x7 |
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#define XENON_SYS_OP_CTRL 0x0108 |
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#define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20) |
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#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8 |
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#define XENON_SLOT_ENABLE_SHIFT 0 |
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#define XENON_SYS_EXT_OP_CTRL 0x010C |
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#define XENON_MASK_CMD_CONFLICT_ERR BIT(8) |
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#define XENON_SLOT_OP_STATUS_CTRL 0x0128 |
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#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16 |
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#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7 |
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#define XENON_TUN_CONSECUTIVE_TIMES 0x4 |
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#define XENON_TUNING_STEP_SHIFT 12 |
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#define XENON_TUNING_STEP_MASK 0xF |
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#define XENON_TUNING_STEP_DIVIDER BIT(6) |
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#define XENON_SLOT_EMMC_CTRL 0x0130 |
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#define XENON_ENABLE_RESP_STROBE BIT(25) |
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#define XENON_ENABLE_DATA_STROBE BIT(24) |
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#define XENON_SLOT_RETUNING_REQ_CTRL 0x0144 |
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/* retuning compatible */ |
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#define XENON_RETUNING_COMPATIBLE 0x1 |
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#define XENON_SLOT_EXT_PRESENT_STATE 0x014C |
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#define XENON_DLL_LOCK_STATE 0x1 |
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#define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150 |
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/* Tuning Parameter */ |
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#define XENON_TMR_RETUN_NO_PRESENT 0xF |
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#define XENON_DEF_TUNING_COUNT 0x9 |
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#define XENON_DEFAULT_SDCLK_FREQ 400000 |
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#define XENON_LOWEST_SDCLK_FREQ 100000 |
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/* Xenon specific Mode Select value */ |
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#define XENON_CTRL_HS200 0x5 |
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#define XENON_CTRL_HS400 0x6 |
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enum xenon_variant { |
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XENON_A3700, |
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XENON_AP806, |
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XENON_AP807, |
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XENON_CP110 |
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}; |
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struct xenon_priv { |
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unsigned char tuning_count; |
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/* idx of SDHC */ |
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u8 sdhc_id; |
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/* |
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* eMMC/SD/SDIO require different register settings. |
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* Xenon driver has to recognize card type |
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* before mmc_host->card is not available. |
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* This field records the card type during init. |
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* It is updated in xenon_init_card(). |
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* |
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* It is only valid during initialization after it is updated. |
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* Do not access this variable in normal transfers after |
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* initialization completes. |
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*/ |
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unsigned int init_card_type; |
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/* |
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* The bus_width, timing, and clock fields in below |
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* record the current ios setting of Xenon SDHC. |
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* Driver will adjust PHY setting if any change to |
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* ios affects PHY timing. |
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*/ |
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unsigned char bus_width; |
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unsigned char timing; |
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unsigned int clock; |
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struct clk *axi_clk; |
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int phy_type; |
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/* |
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* Contains board-specific PHY parameters |
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* passed from device tree. |
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*/ |
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void *phy_params; |
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struct xenon_emmc_phy_regs *emmc_phy_regs; |
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bool restore_needed; |
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enum xenon_variant hw_version; |
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}; |
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int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios); |
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int xenon_phy_parse_params(struct device *dev, |
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struct sdhci_host *host); |
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void xenon_soc_pad_ctrl(struct sdhci_host *host, |
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unsigned char signal_voltage); |
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#endif
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