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637 lines
16 KiB
637 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* Copyright (C) 2019 ASPEED Technology Inc. */ |
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/* Copyright (C) 2019 IBM Corp. */ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/math64.h> |
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#include <linux/mmc/host.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/spinlock.h> |
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#include "sdhci-pltfm.h" |
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#define ASPEED_SDC_INFO 0x00 |
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#define ASPEED_SDC_S1_MMC8 BIT(25) |
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#define ASPEED_SDC_S0_MMC8 BIT(24) |
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#define ASPEED_SDC_PHASE 0xf4 |
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#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) |
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#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) |
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#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) |
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#define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) |
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#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) |
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#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3) |
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#define ASPEED_SDC_S0_PHASE_IN_EN BIT(2) |
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#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) |
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#define ASPEED_SDC_PHASE_MAX 31 |
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/* SDIO{10,20} */ |
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#define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) |
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/* SDIO{14,24} */ |
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#define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) |
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struct aspeed_sdc { |
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struct clk *clk; |
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struct resource *res; |
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spinlock_t lock; |
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void __iomem *regs; |
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}; |
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struct aspeed_sdhci_tap_param { |
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bool valid; |
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#define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4) |
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u8 in; |
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u8 out; |
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}; |
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struct aspeed_sdhci_tap_desc { |
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u32 tap_mask; |
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u32 enable_mask; |
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u8 enable_value; |
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}; |
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struct aspeed_sdhci_phase_desc { |
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struct aspeed_sdhci_tap_desc in; |
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struct aspeed_sdhci_tap_desc out; |
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}; |
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struct aspeed_sdhci_pdata { |
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unsigned int clk_div_start; |
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const struct aspeed_sdhci_phase_desc *phase_desc; |
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size_t nr_phase_descs; |
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}; |
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struct aspeed_sdhci { |
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const struct aspeed_sdhci_pdata *pdata; |
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struct aspeed_sdc *parent; |
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u32 width_mask; |
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struct mmc_clk_phase_map phase_map; |
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const struct aspeed_sdhci_phase_desc *phase_desc; |
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}; |
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/* |
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* The function sets the mirror register for updating |
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* capbilities of the current slot. |
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* |
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* slot | capability | caps_reg | mirror_reg |
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* -----|-------------|----------|------------ |
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* 0 | CAP1_1_8V | SDIO140 | SDIO10 |
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* 0 | CAP2_SDR104 | SDIO144 | SDIO14 |
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* 1 | CAP1_1_8V | SDIO240 | SDIO20 |
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* 1 | CAP2_SDR104 | SDIO244 | SDIO24 |
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*/ |
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static void aspeed_sdc_set_slot_capability(struct sdhci_host *host, struct aspeed_sdc *sdc, |
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int capability, bool enable, u8 slot) |
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{ |
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u32 mirror_reg_offset; |
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u32 cap_val; |
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u8 cap_reg; |
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if (slot > 1) |
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return; |
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cap_reg = capability / 32; |
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cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); |
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if (enable) |
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cap_val |= BIT(capability % 32); |
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else |
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cap_val &= ~BIT(capability % 32); |
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mirror_reg_offset = ((slot + 1) * 0x10) + (cap_reg * 4); |
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writel(cap_val, sdc->regs + mirror_reg_offset); |
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} |
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static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, |
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struct aspeed_sdhci *sdhci, |
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bool bus8) |
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{ |
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u32 info; |
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/* Set/clear 8 bit mode */ |
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spin_lock(&sdc->lock); |
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info = readl(sdc->regs + ASPEED_SDC_INFO); |
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if (bus8) |
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info |= sdhci->width_mask; |
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else |
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info &= ~sdhci->width_mask; |
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writel(info, sdc->regs + ASPEED_SDC_INFO); |
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spin_unlock(&sdc->lock); |
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} |
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static u32 |
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aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc, |
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u8 tap, bool enable, u32 reg) |
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{ |
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reg &= ~(desc->enable_mask | desc->tap_mask); |
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if (enable) { |
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reg |= tap << __ffs(desc->tap_mask); |
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reg |= desc->enable_value << __ffs(desc->enable_mask); |
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} |
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return reg; |
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} |
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static void |
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aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, |
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const struct aspeed_sdhci_phase_desc *desc, |
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const struct aspeed_sdhci_tap_param *taps) |
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{ |
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u32 reg; |
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spin_lock(&sdc->lock); |
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reg = readl(sdc->regs + ASPEED_SDC_PHASE); |
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reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg); |
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reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg); |
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writel(reg, sdc->regs + ASPEED_SDC_PHASE); |
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spin_unlock(&sdc->lock); |
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} |
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#define PICOSECONDS_PER_SECOND 1000000000000ULL |
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#define ASPEED_SDHCI_NR_TAPS 15 |
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/* Measured value with *handwave* environmentals and static loading */ |
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#define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253 |
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static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz, |
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int phase_deg) |
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{ |
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u64 phase_period_ps; |
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u64 prop_delay_ps; |
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u64 clk_period_ps; |
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unsigned int tap; |
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u8 inverted; |
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phase_deg %= 360; |
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if (phase_deg >= 180) { |
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inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; |
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phase_deg -= 180; |
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dev_dbg(dev, |
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"Inverting clock to reduce phase correction from %d to %d degrees\n", |
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phase_deg + 180, phase_deg); |
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} else { |
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inverted = 0; |
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} |
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prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS; |
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clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); |
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phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); |
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tap = div_u64(phase_period_ps, prop_delay_ps); |
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if (tap > ASPEED_SDHCI_NR_TAPS) { |
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dev_dbg(dev, |
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"Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n", |
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tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS); |
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tap = ASPEED_SDHCI_NR_TAPS; |
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} |
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return inverted | tap; |
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} |
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static void |
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aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, |
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const struct mmc_clk_phase *phases, |
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struct aspeed_sdhci_tap_param *taps) |
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{ |
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taps->valid = phases->valid; |
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if (!phases->valid) |
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return; |
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taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); |
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taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); |
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} |
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static void |
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aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate) |
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{ |
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struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps; |
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struct mmc_clk_phase *params; |
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struct aspeed_sdhci *sdhci; |
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struct device *dev; |
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dev = mmc_dev(host->mmc); |
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sdhci = sdhci_pltfm_priv(sdhci_priv(host)); |
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if (!sdhci->phase_desc) |
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return; |
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params = &sdhci->phase_map.phase[host->timing]; |
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aspeed_sdhci_phases_to_taps(dev, rate, params, taps); |
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aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); |
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dev_dbg(dev, |
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"Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n", |
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taps->in & ASPEED_SDHCI_NR_TAPS, |
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taps->out & ASPEED_SDHCI_NR_TAPS, |
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params->in_deg, params->out_deg, rate, host->timing); |
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} |
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static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
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{ |
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struct sdhci_pltfm_host *pltfm_host; |
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unsigned long parent, bus; |
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struct aspeed_sdhci *sdhci; |
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int div; |
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u16 clk; |
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pltfm_host = sdhci_priv(host); |
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sdhci = sdhci_pltfm_priv(pltfm_host); |
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parent = clk_get_rate(pltfm_host->clk); |
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
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if (clock == 0) |
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return; |
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if (WARN_ON(clock > host->max_clk)) |
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clock = host->max_clk; |
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/* |
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* Regarding the AST2600: |
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* |
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* If (EMMC12C[7:6], EMMC12C[15:8] == 0) then |
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* period of SDCLK = period of SDMCLK. |
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* |
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* If (EMMC12C[7:6], EMMC12C[15:8] != 0) then |
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* period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) |
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* |
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* If you keep EMMC12C[7:6] = 0 and EMMC12C[15:8] as one-hot, |
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* 0x1/0x2/0x4/etc, you will find it is compatible to AST2400 or AST2500 |
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* |
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* Keep the one-hot behaviour for backwards compatibility except for |
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* supporting the value 0 in (EMMC12C[7:6], EMMC12C[15:8]), and capture |
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* the 0-value capability in clk_div_start. |
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*/ |
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for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) { |
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bus = parent / div; |
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if (bus <= clock) |
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break; |
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} |
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div >>= 1; |
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clk = div << SDHCI_DIVIDER_SHIFT; |
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aspeed_sdhci_configure_phase(host, bus); |
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sdhci_enable_clk(host, clk); |
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} |
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static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) |
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{ |
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if (host->mmc->f_max) |
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return host->mmc->f_max; |
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return sdhci_pltfm_clk_get_max_clock(host); |
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} |
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static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) |
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{ |
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struct sdhci_pltfm_host *pltfm_priv; |
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struct aspeed_sdhci *aspeed_sdhci; |
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struct aspeed_sdc *aspeed_sdc; |
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u8 ctrl; |
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pltfm_priv = sdhci_priv(host); |
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aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); |
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aspeed_sdc = aspeed_sdhci->parent; |
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/* Set/clear 8-bit mode */ |
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aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci, |
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width == MMC_BUS_WIDTH_8); |
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/* Set/clear 1 or 4 bit mode */ |
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
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if (width == MMC_BUS_WIDTH_4) |
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ctrl |= SDHCI_CTRL_4BITBUS; |
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else |
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ctrl &= ~SDHCI_CTRL_4BITBUS; |
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
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} |
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static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg) |
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{ |
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u32 val = readl(host->ioaddr + reg); |
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if (unlikely(reg == SDHCI_PRESENT_STATE) && |
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(host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)) |
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val ^= SDHCI_CARD_PRESENT; |
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return val; |
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} |
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static const struct sdhci_ops aspeed_sdhci_ops = { |
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.read_l = aspeed_sdhci_readl, |
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.set_clock = aspeed_sdhci_set_clock, |
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.get_max_clock = aspeed_sdhci_get_max_clock, |
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.set_bus_width = aspeed_sdhci_set_bus_width, |
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.get_timeout_clock = sdhci_pltfm_clk_get_max_clock, |
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.reset = sdhci_reset, |
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.set_uhs_signaling = sdhci_set_uhs_signaling, |
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}; |
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static const struct sdhci_pltfm_data aspeed_sdhci_pdata = { |
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.ops = &aspeed_sdhci_ops, |
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
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}; |
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static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, |
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struct resource *res) |
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{ |
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resource_size_t delta; |
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if (!res || resource_type(res) != IORESOURCE_MEM) |
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return -EINVAL; |
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if (res->start < dev->parent->res->start) |
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return -EINVAL; |
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delta = res->start - dev->parent->res->start; |
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if (delta & (0x100 - 1)) |
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return -EINVAL; |
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return (delta / 0x100) - 1; |
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} |
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static int aspeed_sdhci_probe(struct platform_device *pdev) |
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{ |
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const struct aspeed_sdhci_pdata *aspeed_pdata; |
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struct device_node *np = pdev->dev.of_node; |
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struct sdhci_pltfm_host *pltfm_host; |
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struct aspeed_sdhci *dev; |
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struct sdhci_host *host; |
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struct resource *res; |
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int slot; |
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int ret; |
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aspeed_pdata = of_device_get_match_data(&pdev->dev); |
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if (!aspeed_pdata) { |
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dev_err(&pdev->dev, "Missing platform configuration data\n"); |
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return -EINVAL; |
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} |
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host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); |
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if (IS_ERR(host)) |
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return PTR_ERR(host); |
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pltfm_host = sdhci_priv(host); |
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dev = sdhci_pltfm_priv(pltfm_host); |
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dev->pdata = aspeed_pdata; |
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dev->parent = dev_get_drvdata(pdev->dev.parent); |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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slot = aspeed_sdhci_calculate_slot(dev, res); |
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if (slot < 0) |
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return slot; |
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else if (slot >= 2) |
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return -EINVAL; |
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if (slot < dev->pdata->nr_phase_descs) { |
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dev->phase_desc = &dev->pdata->phase_desc[slot]; |
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} else { |
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dev_info(&pdev->dev, |
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"Phase control not supported for slot %d\n", slot); |
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dev->phase_desc = NULL; |
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} |
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dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; |
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dev_info(&pdev->dev, "Configured for slot %d\n", slot); |
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sdhci_get_of_property(pdev); |
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if (of_property_read_bool(np, "mmc-hs200-1_8v") || |
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of_property_read_bool(np, "sd-uhs-sdr104")) { |
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aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, |
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true, slot); |
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} |
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if (of_property_read_bool(np, "sd-uhs-sdr104")) { |
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aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, |
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true, slot); |
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} |
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pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(pltfm_host->clk)) |
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return PTR_ERR(pltfm_host->clk); |
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ret = clk_prepare_enable(pltfm_host->clk); |
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if (ret) { |
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dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); |
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goto err_pltfm_free; |
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} |
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ret = mmc_of_parse(host->mmc); |
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if (ret) |
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goto err_sdhci_add; |
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if (dev->phase_desc) |
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mmc_of_parse_clk_phase(host->mmc, &dev->phase_map); |
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ret = sdhci_add_host(host); |
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if (ret) |
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goto err_sdhci_add; |
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return 0; |
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err_sdhci_add: |
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clk_disable_unprepare(pltfm_host->clk); |
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err_pltfm_free: |
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sdhci_pltfm_free(pdev); |
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return ret; |
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} |
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static int aspeed_sdhci_remove(struct platform_device *pdev) |
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{ |
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struct sdhci_pltfm_host *pltfm_host; |
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struct sdhci_host *host; |
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int dead = 0; |
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host = platform_get_drvdata(pdev); |
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pltfm_host = sdhci_priv(host); |
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sdhci_remove_host(host, dead); |
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clk_disable_unprepare(pltfm_host->clk); |
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sdhci_pltfm_free(pdev); |
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return 0; |
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} |
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static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = { |
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.clk_div_start = 2, |
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}; |
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static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { |
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/* SDHCI/Slot 0 */ |
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[0] = { |
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.in = { |
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.tap_mask = ASPEED_SDC_S0_PHASE_IN, |
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.enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, |
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.enable_value = 1, |
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}, |
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.out = { |
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.tap_mask = ASPEED_SDC_S0_PHASE_OUT, |
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.enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, |
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.enable_value = 3, |
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}, |
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}, |
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/* SDHCI/Slot 1 */ |
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[1] = { |
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.in = { |
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.tap_mask = ASPEED_SDC_S1_PHASE_IN, |
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.enable_mask = ASPEED_SDC_S1_PHASE_IN_EN, |
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.enable_value = 1, |
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}, |
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.out = { |
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.tap_mask = ASPEED_SDC_S1_PHASE_OUT, |
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.enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, |
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.enable_value = 3, |
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}, |
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}, |
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}; |
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static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = { |
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.clk_div_start = 1, |
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.phase_desc = ast2600_sdhci_phase, |
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.nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase), |
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}; |
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static const struct of_device_id aspeed_sdhci_of_match[] = { |
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{ .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, }, |
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{ .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, }, |
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{ .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, }, |
|
{ } |
|
}; |
|
|
|
static struct platform_driver aspeed_sdhci_driver = { |
|
.driver = { |
|
.name = "sdhci-aspeed", |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.of_match_table = aspeed_sdhci_of_match, |
|
}, |
|
.probe = aspeed_sdhci_probe, |
|
.remove = aspeed_sdhci_remove, |
|
}; |
|
|
|
static int aspeed_sdc_probe(struct platform_device *pdev) |
|
|
|
{ |
|
struct device_node *parent, *child; |
|
struct aspeed_sdc *sdc; |
|
int ret; |
|
|
|
sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); |
|
if (!sdc) |
|
return -ENOMEM; |
|
|
|
spin_lock_init(&sdc->lock); |
|
|
|
sdc->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(sdc->clk)) |
|
return PTR_ERR(sdc->clk); |
|
|
|
ret = clk_prepare_enable(sdc->clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Unable to enable SDCLK\n"); |
|
return ret; |
|
} |
|
|
|
sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res); |
|
if (IS_ERR(sdc->regs)) { |
|
ret = PTR_ERR(sdc->regs); |
|
goto err_clk; |
|
} |
|
|
|
dev_set_drvdata(&pdev->dev, sdc); |
|
|
|
parent = pdev->dev.of_node; |
|
for_each_available_child_of_node(parent, child) { |
|
struct platform_device *cpdev; |
|
|
|
cpdev = of_platform_device_create(child, NULL, &pdev->dev); |
|
if (!cpdev) { |
|
of_node_put(child); |
|
ret = -ENODEV; |
|
goto err_clk; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
err_clk: |
|
clk_disable_unprepare(sdc->clk); |
|
return ret; |
|
} |
|
|
|
static int aspeed_sdc_remove(struct platform_device *pdev) |
|
{ |
|
struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); |
|
|
|
clk_disable_unprepare(sdc->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id aspeed_sdc_of_match[] = { |
|
{ .compatible = "aspeed,ast2400-sd-controller", }, |
|
{ .compatible = "aspeed,ast2500-sd-controller", }, |
|
{ .compatible = "aspeed,ast2600-sd-controller", }, |
|
{ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); |
|
|
|
static struct platform_driver aspeed_sdc_driver = { |
|
.driver = { |
|
.name = "sd-controller-aspeed", |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.pm = &sdhci_pltfm_pmops, |
|
.of_match_table = aspeed_sdc_of_match, |
|
}, |
|
.probe = aspeed_sdc_probe, |
|
.remove = aspeed_sdc_remove, |
|
}; |
|
|
|
#if defined(CONFIG_MMC_SDHCI_OF_ASPEED_TEST) |
|
#include "sdhci-of-aspeed-test.c" |
|
#endif |
|
|
|
static int __init aspeed_sdc_init(void) |
|
{ |
|
int rc; |
|
|
|
rc = platform_driver_register(&aspeed_sdhci_driver); |
|
if (rc < 0) |
|
return rc; |
|
|
|
rc = platform_driver_register(&aspeed_sdc_driver); |
|
if (rc < 0) |
|
platform_driver_unregister(&aspeed_sdhci_driver); |
|
|
|
return rc; |
|
} |
|
module_init(aspeed_sdc_init); |
|
|
|
static void __exit aspeed_sdc_exit(void) |
|
{ |
|
platform_driver_unregister(&aspeed_sdc_driver); |
|
platform_driver_unregister(&aspeed_sdhci_driver); |
|
} |
|
module_exit(aspeed_sdc_exit); |
|
|
|
MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); |
|
MODULE_AUTHOR("Ryan Chen <[email protected]>"); |
|
MODULE_AUTHOR("Andrew Jeffery <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|