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843 lines
23 KiB
843 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell MMC/SD/SDIO driver |
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* |
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* Authors: Maen Suleiman, Nicolas Pitre |
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* Copyright (C) 2008-2009 Marvell Ltd. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/platform_device.h> |
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#include <linux/mbus.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/scatterlist.h> |
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#include <linux/irq.h> |
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#include <linux/clk.h> |
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#include <linux/of_irq.h> |
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#include <linux/mmc/host.h> |
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#include <linux/mmc/slot-gpio.h> |
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#include <linux/sizes.h> |
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#include <asm/unaligned.h> |
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#include "mvsdio.h" |
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#define DRIVER_NAME "mvsdio" |
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static int maxfreq; |
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static int nodma; |
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struct mvsd_host { |
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void __iomem *base; |
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struct mmc_request *mrq; |
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spinlock_t lock; |
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unsigned int xfer_mode; |
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unsigned int intr_en; |
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unsigned int ctrl; |
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unsigned int pio_size; |
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void *pio_ptr; |
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unsigned int sg_frags; |
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unsigned int ns_per_clk; |
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unsigned int clock; |
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unsigned int base_clock; |
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struct timer_list timer; |
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struct mmc_host *mmc; |
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struct device *dev; |
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struct clk *clk; |
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}; |
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#define mvsd_write(offs, val) writel(val, iobase + (offs)) |
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#define mvsd_read(offs) readl(iobase + (offs)) |
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static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) |
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{ |
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void __iomem *iobase = host->base; |
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unsigned int tmout; |
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int tmout_index; |
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/* |
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* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE |
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* register is sometimes not set before a while when some |
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* "unusual" data block sizes are used (such as with the SWITCH |
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* command), even despite the fact that the XFER_DONE interrupt |
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* was raised. And if another data transfer starts before |
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* this bit comes to good sense (which eventually happens by |
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* itself) then the new transfer simply fails with a timeout. |
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*/ |
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if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { |
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unsigned long t = jiffies + HZ; |
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unsigned int hw_state, count = 0; |
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do { |
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hw_state = mvsd_read(MVSD_HW_STATE); |
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if (time_after(jiffies, t)) { |
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dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); |
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break; |
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} |
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count++; |
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} while (!(hw_state & (1 << 13))); |
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dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " |
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"(hw=0x%04x, count=%d, jiffies=%ld)\n", |
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hw_state, count, jiffies - (t - HZ)); |
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} |
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/* If timeout=0 then maximum timeout index is used. */ |
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tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); |
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tmout += data->timeout_clks; |
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tmout_index = fls(tmout - 1) - 12; |
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if (tmout_index < 0) |
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tmout_index = 0; |
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if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) |
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tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; |
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dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", |
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(data->flags & MMC_DATA_READ) ? "read" : "write", |
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(u32)sg_virt(data->sg), data->blocks, data->blksz, |
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tmout, tmout_index); |
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host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; |
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host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); |
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mvsd_write(MVSD_HOST_CTRL, host->ctrl); |
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mvsd_write(MVSD_BLK_COUNT, data->blocks); |
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mvsd_write(MVSD_BLK_SIZE, data->blksz); |
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if (nodma || (data->blksz | data->sg->offset) & 3 || |
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((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) { |
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/* |
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* We cannot do DMA on a buffer which offset or size |
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* is not aligned on a 4-byte boundary. |
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* |
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* It also appears the host to card DMA can corrupt |
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* data when the buffer is not aligned on a 64 byte |
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* boundary. |
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*/ |
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host->pio_size = data->blocks * data->blksz; |
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host->pio_ptr = sg_virt(data->sg); |
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if (!nodma) |
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dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n", |
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host->pio_ptr, host->pio_size); |
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return 1; |
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} else { |
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dma_addr_t phys_addr; |
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host->sg_frags = dma_map_sg(mmc_dev(host->mmc), |
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data->sg, data->sg_len, |
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mmc_get_dma_dir(data)); |
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phys_addr = sg_dma_address(data->sg); |
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mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); |
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mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); |
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return 0; |
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} |
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} |
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static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) |
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{ |
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struct mvsd_host *host = mmc_priv(mmc); |
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void __iomem *iobase = host->base; |
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struct mmc_command *cmd = mrq->cmd; |
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u32 cmdreg = 0, xfer = 0, intr = 0; |
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unsigned long flags; |
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unsigned int timeout; |
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BUG_ON(host->mrq != NULL); |
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host->mrq = mrq; |
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dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", |
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cmd->opcode, mvsd_read(MVSD_HW_STATE)); |
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cmdreg = MVSD_CMD_INDEX(cmd->opcode); |
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if (cmd->flags & MMC_RSP_BUSY) |
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cmdreg |= MVSD_CMD_RSP_48BUSY; |
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else if (cmd->flags & MMC_RSP_136) |
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cmdreg |= MVSD_CMD_RSP_136; |
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else if (cmd->flags & MMC_RSP_PRESENT) |
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cmdreg |= MVSD_CMD_RSP_48; |
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else |
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cmdreg |= MVSD_CMD_RSP_NONE; |
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if (cmd->flags & MMC_RSP_CRC) |
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cmdreg |= MVSD_CMD_CHECK_CMDCRC; |
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if (cmd->flags & MMC_RSP_OPCODE) |
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cmdreg |= MVSD_CMD_INDX_CHECK; |
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if (cmd->flags & MMC_RSP_PRESENT) { |
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cmdreg |= MVSD_UNEXPECTED_RESP; |
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intr |= MVSD_NOR_UNEXP_RSP; |
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} |
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if (mrq->data) { |
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struct mmc_data *data = mrq->data; |
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int pio; |
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cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; |
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xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; |
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if (data->flags & MMC_DATA_READ) |
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xfer |= MVSD_XFER_MODE_TO_HOST; |
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pio = mvsd_setup_data(host, data); |
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if (pio) { |
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xfer |= MVSD_XFER_MODE_PIO; |
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/* PIO section of mvsd_irq has comments on those bits */ |
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if (data->flags & MMC_DATA_WRITE) |
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intr |= MVSD_NOR_TX_AVAIL; |
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else if (host->pio_size > 32) |
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intr |= MVSD_NOR_RX_FIFO_8W; |
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else |
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intr |= MVSD_NOR_RX_READY; |
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} |
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if (data->stop) { |
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struct mmc_command *stop = data->stop; |
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u32 cmd12reg = 0; |
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mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); |
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mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); |
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if (stop->flags & MMC_RSP_BUSY) |
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cmd12reg |= MVSD_AUTOCMD12_BUSY; |
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if (stop->flags & MMC_RSP_OPCODE) |
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cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; |
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cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); |
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mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); |
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xfer |= MVSD_XFER_MODE_AUTO_CMD12; |
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intr |= MVSD_NOR_AUTOCMD12_DONE; |
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} else { |
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intr |= MVSD_NOR_XFER_DONE; |
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} |
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} else { |
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intr |= MVSD_NOR_CMD_DONE; |
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} |
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mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); |
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mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); |
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spin_lock_irqsave(&host->lock, flags); |
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host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; |
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host->xfer_mode |= xfer; |
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mvsd_write(MVSD_XFER_MODE, host->xfer_mode); |
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mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); |
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mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); |
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mvsd_write(MVSD_CMD, cmdreg); |
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host->intr_en &= MVSD_NOR_CARD_INT; |
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host->intr_en |= intr | MVSD_NOR_ERROR; |
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mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
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mvsd_write(MVSD_ERR_INTR_EN, 0xffff); |
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timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000; |
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mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout)); |
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spin_unlock_irqrestore(&host->lock, flags); |
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} |
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static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, |
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u32 err_status) |
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{ |
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void __iomem *iobase = host->base; |
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if (cmd->flags & MMC_RSP_136) { |
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unsigned int response[8], i; |
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for (i = 0; i < 8; i++) |
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response[i] = mvsd_read(MVSD_RSP(i)); |
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cmd->resp[0] = ((response[0] & 0x03ff) << 22) | |
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((response[1] & 0xffff) << 6) | |
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((response[2] & 0xfc00) >> 10); |
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cmd->resp[1] = ((response[2] & 0x03ff) << 22) | |
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((response[3] & 0xffff) << 6) | |
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((response[4] & 0xfc00) >> 10); |
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cmd->resp[2] = ((response[4] & 0x03ff) << 22) | |
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((response[5] & 0xffff) << 6) | |
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((response[6] & 0xfc00) >> 10); |
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cmd->resp[3] = ((response[6] & 0x03ff) << 22) | |
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((response[7] & 0x3fff) << 8); |
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} else if (cmd->flags & MMC_RSP_PRESENT) { |
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unsigned int response[3], i; |
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for (i = 0; i < 3; i++) |
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response[i] = mvsd_read(MVSD_RSP(i)); |
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cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | |
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((response[1] & 0xffff) << (14 - 8)) | |
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((response[0] & 0x03ff) << (30 - 8)); |
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cmd->resp[1] = ((response[0] & 0xfc00) >> 10); |
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cmd->resp[2] = 0; |
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cmd->resp[3] = 0; |
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} |
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if (err_status & MVSD_ERR_CMD_TIMEOUT) { |
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cmd->error = -ETIMEDOUT; |
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} else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | |
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MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { |
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cmd->error = -EILSEQ; |
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} |
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err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | |
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MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | |
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MVSD_ERR_CMD_STARTBIT); |
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return err_status; |
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} |
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static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, |
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u32 err_status) |
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{ |
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void __iomem *iobase = host->base; |
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if (host->pio_ptr) { |
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host->pio_ptr = NULL; |
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host->pio_size = 0; |
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} else { |
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, |
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mmc_get_dma_dir(data)); |
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} |
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if (err_status & MVSD_ERR_DATA_TIMEOUT) |
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data->error = -ETIMEDOUT; |
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else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) |
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data->error = -EILSEQ; |
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else if (err_status & MVSD_ERR_XFER_SIZE) |
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data->error = -EBADE; |
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err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | |
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MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); |
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dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", |
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mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); |
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data->bytes_xfered = |
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(data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; |
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/* We can't be sure about the last block when errors are detected */ |
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if (data->bytes_xfered && data->error) |
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data->bytes_xfered -= data->blksz; |
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/* Handle Auto cmd 12 response */ |
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if (data->stop) { |
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unsigned int response[3], i; |
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for (i = 0; i < 3; i++) |
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response[i] = mvsd_read(MVSD_AUTO_RSP(i)); |
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data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | |
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((response[1] & 0xffff) << (14 - 8)) | |
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((response[0] & 0x03ff) << (30 - 8)); |
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data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); |
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data->stop->resp[2] = 0; |
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data->stop->resp[3] = 0; |
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if (err_status & MVSD_ERR_AUTOCMD12) { |
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u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); |
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dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); |
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if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) |
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data->stop->error = -ENOEXEC; |
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else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) |
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data->stop->error = -ETIMEDOUT; |
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else if (err_cmd12) |
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data->stop->error = -EILSEQ; |
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err_status &= ~MVSD_ERR_AUTOCMD12; |
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} |
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} |
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return err_status; |
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} |
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static irqreturn_t mvsd_irq(int irq, void *dev) |
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{ |
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struct mvsd_host *host = dev; |
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void __iomem *iobase = host->base; |
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u32 intr_status, intr_done_mask; |
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int irq_handled = 0; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", |
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intr_status, mvsd_read(MVSD_NOR_INTR_EN), |
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mvsd_read(MVSD_HW_STATE)); |
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/* |
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* It looks like, SDIO IP can issue one late, spurious irq |
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* although all irqs should be disabled. To work around this, |
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* bail out early, if we didn't expect any irqs to occur. |
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*/ |
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if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) { |
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dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", |
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mvsd_read(MVSD_NOR_INTR_STATUS), |
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mvsd_read(MVSD_NOR_INTR_EN), |
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mvsd_read(MVSD_ERR_INTR_STATUS), |
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mvsd_read(MVSD_ERR_INTR_EN)); |
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return IRQ_HANDLED; |
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} |
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spin_lock(&host->lock); |
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/* PIO handling, if needed. Messy business... */ |
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if (host->pio_size && |
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(intr_status & host->intr_en & |
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(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { |
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u16 *p = host->pio_ptr; |
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int s = host->pio_size; |
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while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { |
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readsw(iobase + MVSD_FIFO, p, 16); |
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p += 16; |
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s -= 32; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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} |
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/* |
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* Normally we'd use < 32 here, but the RX_FIFO_8W bit |
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* doesn't appear to assert when there is exactly 32 bytes |
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* (8 words) left to fetch in a transfer. |
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*/ |
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if (s <= 32) { |
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while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { |
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put_unaligned(mvsd_read(MVSD_FIFO), p++); |
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put_unaligned(mvsd_read(MVSD_FIFO), p++); |
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s -= 4; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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} |
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if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { |
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u16 val[2] = {0, 0}; |
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val[0] = mvsd_read(MVSD_FIFO); |
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val[1] = mvsd_read(MVSD_FIFO); |
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memcpy(p, ((void *)&val) + 4 - s, s); |
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s = 0; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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} |
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if (s == 0) { |
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host->intr_en &= |
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~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); |
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mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
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} else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { |
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host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; |
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host->intr_en |= MVSD_NOR_RX_READY; |
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mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
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} |
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} |
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dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", |
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s, intr_status, mvsd_read(MVSD_HW_STATE)); |
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host->pio_ptr = p; |
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host->pio_size = s; |
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irq_handled = 1; |
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} else if (host->pio_size && |
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(intr_status & host->intr_en & |
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(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { |
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u16 *p = host->pio_ptr; |
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int s = host->pio_size; |
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/* |
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* The TX_FIFO_8W bit is unreliable. When set, bursting |
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* 16 halfwords all at once in the FIFO drops data. Actually |
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* TX_AVAIL does go off after only one word is pushed even if |
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* TX_FIFO_8W remains set. |
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*/ |
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while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { |
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mvsd_write(MVSD_FIFO, get_unaligned(p++)); |
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mvsd_write(MVSD_FIFO, get_unaligned(p++)); |
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s -= 4; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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} |
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if (s < 4) { |
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if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { |
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u16 val[2] = {0, 0}; |
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memcpy(((void *)&val) + 4 - s, p, s); |
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mvsd_write(MVSD_FIFO, val[0]); |
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mvsd_write(MVSD_FIFO, val[1]); |
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s = 0; |
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intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); |
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} |
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if (s == 0) { |
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host->intr_en &= |
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~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); |
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mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
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} |
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} |
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dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", |
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s, intr_status, mvsd_read(MVSD_HW_STATE)); |
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host->pio_ptr = p; |
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host->pio_size = s; |
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irq_handled = 1; |
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} |
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|
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mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); |
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|
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intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | |
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MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; |
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if (intr_status & host->intr_en & ~intr_done_mask) { |
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struct mmc_request *mrq = host->mrq; |
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struct mmc_command *cmd = mrq->cmd; |
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u32 err_status = 0; |
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|
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del_timer(&host->timer); |
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host->mrq = NULL; |
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|
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host->intr_en &= MVSD_NOR_CARD_INT; |
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mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
|
mvsd_write(MVSD_ERR_INTR_EN, 0); |
|
|
|
spin_unlock(&host->lock); |
|
|
|
if (intr_status & MVSD_NOR_UNEXP_RSP) { |
|
cmd->error = -EPROTO; |
|
} else if (intr_status & MVSD_NOR_ERROR) { |
|
err_status = mvsd_read(MVSD_ERR_INTR_STATUS); |
|
dev_dbg(host->dev, "err 0x%04x\n", err_status); |
|
} |
|
|
|
err_status = mvsd_finish_cmd(host, cmd, err_status); |
|
if (mrq->data) |
|
err_status = mvsd_finish_data(host, mrq->data, err_status); |
|
if (err_status) { |
|
dev_err(host->dev, "unhandled error status %#04x\n", |
|
err_status); |
|
cmd->error = -ENOMSG; |
|
} |
|
|
|
mmc_request_done(host->mmc, mrq); |
|
irq_handled = 1; |
|
} else |
|
spin_unlock(&host->lock); |
|
|
|
if (intr_status & MVSD_NOR_CARD_INT) { |
|
mmc_signal_sdio_irq(host->mmc); |
|
irq_handled = 1; |
|
} |
|
|
|
if (irq_handled) |
|
return IRQ_HANDLED; |
|
|
|
dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n", |
|
intr_status, host->intr_en, host->pio_size); |
|
return IRQ_NONE; |
|
} |
|
|
|
static void mvsd_timeout_timer(struct timer_list *t) |
|
{ |
|
struct mvsd_host *host = from_timer(host, t, timer); |
|
void __iomem *iobase = host->base; |
|
struct mmc_request *mrq; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&host->lock, flags); |
|
mrq = host->mrq; |
|
if (mrq) { |
|
dev_err(host->dev, "Timeout waiting for hardware interrupt.\n"); |
|
dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n", |
|
mvsd_read(MVSD_HW_STATE), |
|
mvsd_read(MVSD_NOR_INTR_STATUS), |
|
mvsd_read(MVSD_NOR_INTR_EN)); |
|
|
|
host->mrq = NULL; |
|
|
|
mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); |
|
|
|
host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; |
|
mvsd_write(MVSD_XFER_MODE, host->xfer_mode); |
|
|
|
host->intr_en &= MVSD_NOR_CARD_INT; |
|
mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
|
mvsd_write(MVSD_ERR_INTR_EN, 0); |
|
mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); |
|
|
|
mrq->cmd->error = -ETIMEDOUT; |
|
mvsd_finish_cmd(host, mrq->cmd, 0); |
|
if (mrq->data) { |
|
mrq->data->error = -ETIMEDOUT; |
|
mvsd_finish_data(host, mrq->data, 0); |
|
} |
|
} |
|
spin_unlock_irqrestore(&host->lock, flags); |
|
|
|
if (mrq) |
|
mmc_request_done(host->mmc, mrq); |
|
} |
|
|
|
static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) |
|
{ |
|
struct mvsd_host *host = mmc_priv(mmc); |
|
void __iomem *iobase = host->base; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&host->lock, flags); |
|
if (enable) { |
|
host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; |
|
host->intr_en |= MVSD_NOR_CARD_INT; |
|
} else { |
|
host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; |
|
host->intr_en &= ~MVSD_NOR_CARD_INT; |
|
} |
|
mvsd_write(MVSD_XFER_MODE, host->xfer_mode); |
|
mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); |
|
spin_unlock_irqrestore(&host->lock, flags); |
|
} |
|
|
|
static void mvsd_power_up(struct mvsd_host *host) |
|
{ |
|
void __iomem *iobase = host->base; |
|
dev_dbg(host->dev, "power up\n"); |
|
mvsd_write(MVSD_NOR_INTR_EN, 0); |
|
mvsd_write(MVSD_ERR_INTR_EN, 0); |
|
mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); |
|
mvsd_write(MVSD_XFER_MODE, 0); |
|
mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); |
|
mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); |
|
mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); |
|
mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); |
|
} |
|
|
|
static void mvsd_power_down(struct mvsd_host *host) |
|
{ |
|
void __iomem *iobase = host->base; |
|
dev_dbg(host->dev, "power down\n"); |
|
mvsd_write(MVSD_NOR_INTR_EN, 0); |
|
mvsd_write(MVSD_ERR_INTR_EN, 0); |
|
mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); |
|
mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); |
|
mvsd_write(MVSD_NOR_STATUS_EN, 0); |
|
mvsd_write(MVSD_ERR_STATUS_EN, 0); |
|
mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); |
|
mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); |
|
} |
|
|
|
static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
|
{ |
|
struct mvsd_host *host = mmc_priv(mmc); |
|
void __iomem *iobase = host->base; |
|
u32 ctrl_reg = 0; |
|
|
|
if (ios->power_mode == MMC_POWER_UP) |
|
mvsd_power_up(host); |
|
|
|
if (ios->clock == 0) { |
|
mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); |
|
mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); |
|
host->clock = 0; |
|
dev_dbg(host->dev, "clock off\n"); |
|
} else if (ios->clock != host->clock) { |
|
u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; |
|
if (m > MVSD_BASE_DIV_MAX) |
|
m = MVSD_BASE_DIV_MAX; |
|
mvsd_write(MVSD_CLK_DIV, m); |
|
host->clock = ios->clock; |
|
host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); |
|
dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", |
|
ios->clock, host->base_clock / (m+1), m); |
|
} |
|
|
|
/* default transfer mode */ |
|
ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; |
|
ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; |
|
|
|
/* default to maximum timeout */ |
|
ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; |
|
ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; |
|
|
|
if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) |
|
ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; |
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4) |
|
ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; |
|
|
|
/* |
|
* The HI_SPEED_EN bit is causing trouble with many (but not all) |
|
* high speed SD, SDHC and SDIO cards. Not enabling that bit |
|
* makes all cards work. So let's just ignore that bit for now |
|
* and revisit this issue if problems for not enabling this bit |
|
* are ever reported. |
|
*/ |
|
#if 0 |
|
if (ios->timing == MMC_TIMING_MMC_HS || |
|
ios->timing == MMC_TIMING_SD_HS) |
|
ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; |
|
#endif |
|
|
|
host->ctrl = ctrl_reg; |
|
mvsd_write(MVSD_HOST_CTRL, ctrl_reg); |
|
dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, |
|
(ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? |
|
"push-pull" : "open-drain", |
|
(ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? |
|
"4bit-width" : "1bit-width", |
|
(ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? |
|
"high-speed" : ""); |
|
|
|
if (ios->power_mode == MMC_POWER_OFF) |
|
mvsd_power_down(host); |
|
} |
|
|
|
static const struct mmc_host_ops mvsd_ops = { |
|
.request = mvsd_request, |
|
.get_ro = mmc_gpio_get_ro, |
|
.set_ios = mvsd_set_ios, |
|
.enable_sdio_irq = mvsd_enable_sdio_irq, |
|
}; |
|
|
|
static void |
|
mv_conf_mbus_windows(struct mvsd_host *host, |
|
const struct mbus_dram_target_info *dram) |
|
{ |
|
void __iomem *iobase = host->base; |
|
int i; |
|
|
|
for (i = 0; i < 4; i++) { |
|
writel(0, iobase + MVSD_WINDOW_CTRL(i)); |
|
writel(0, iobase + MVSD_WINDOW_BASE(i)); |
|
} |
|
|
|
for (i = 0; i < dram->num_cs; i++) { |
|
const struct mbus_dram_window *cs = dram->cs + i; |
|
writel(((cs->size - 1) & 0xffff0000) | |
|
(cs->mbus_attr << 8) | |
|
(dram->mbus_dram_target_id << 4) | 1, |
|
iobase + MVSD_WINDOW_CTRL(i)); |
|
writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); |
|
} |
|
} |
|
|
|
static int mvsd_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct mmc_host *mmc = NULL; |
|
struct mvsd_host *host = NULL; |
|
const struct mbus_dram_target_info *dram; |
|
int ret, irq; |
|
|
|
if (!np) { |
|
dev_err(&pdev->dev, "no DT node\n"); |
|
return -ENODEV; |
|
} |
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return -ENXIO; |
|
|
|
mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); |
|
if (!mmc) { |
|
ret = -ENOMEM; |
|
goto out; |
|
} |
|
|
|
host = mmc_priv(mmc); |
|
host->mmc = mmc; |
|
host->dev = &pdev->dev; |
|
|
|
/* |
|
* Some non-DT platforms do not pass a clock, and the clock |
|
* frequency is passed through platform_data. On DT platforms, |
|
* a clock must always be passed, even if there is no gatable |
|
* clock associated to the SDIO interface (it can simply be a |
|
* fixed rate clock). |
|
*/ |
|
host->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(host->clk)) { |
|
dev_err(&pdev->dev, "no clock associated\n"); |
|
ret = -EINVAL; |
|
goto out; |
|
} |
|
clk_prepare_enable(host->clk); |
|
|
|
mmc->ops = &mvsd_ops; |
|
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
|
|
|
mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); |
|
mmc->f_max = MVSD_CLOCKRATE_MAX; |
|
|
|
mmc->max_blk_size = 2048; |
|
mmc->max_blk_count = 65535; |
|
|
|
mmc->max_segs = 1; |
|
mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; |
|
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
|
|
|
host->base_clock = clk_get_rate(host->clk) / 2; |
|
ret = mmc_of_parse(mmc); |
|
if (ret < 0) |
|
goto out; |
|
if (maxfreq) |
|
mmc->f_max = maxfreq; |
|
|
|
spin_lock_init(&host->lock); |
|
|
|
host->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(host->base)) { |
|
ret = PTR_ERR(host->base); |
|
goto out; |
|
} |
|
|
|
/* (Re-)program MBUS remapping windows if we are asked to. */ |
|
dram = mv_mbus_dram_info(); |
|
if (dram) |
|
mv_conf_mbus_windows(host, dram); |
|
|
|
mvsd_power_down(host); |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); |
|
if (ret) { |
|
dev_err(&pdev->dev, "cannot assign irq %d\n", irq); |
|
goto out; |
|
} |
|
|
|
timer_setup(&host->timer, mvsd_timeout_timer, 0); |
|
platform_set_drvdata(pdev, mmc); |
|
ret = mmc_add_host(mmc); |
|
if (ret) |
|
goto out; |
|
|
|
if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) |
|
dev_dbg(&pdev->dev, "using GPIO for card detection\n"); |
|
else |
|
dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n"); |
|
|
|
return 0; |
|
|
|
out: |
|
if (mmc) { |
|
if (!IS_ERR(host->clk)) |
|
clk_disable_unprepare(host->clk); |
|
mmc_free_host(mmc); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int mvsd_remove(struct platform_device *pdev) |
|
{ |
|
struct mmc_host *mmc = platform_get_drvdata(pdev); |
|
|
|
struct mvsd_host *host = mmc_priv(mmc); |
|
|
|
mmc_remove_host(mmc); |
|
del_timer_sync(&host->timer); |
|
mvsd_power_down(host); |
|
|
|
if (!IS_ERR(host->clk)) |
|
clk_disable_unprepare(host->clk); |
|
mmc_free_host(mmc); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id mvsdio_dt_ids[] = { |
|
{ .compatible = "marvell,orion-sdio" }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, mvsdio_dt_ids); |
|
|
|
static struct platform_driver mvsd_driver = { |
|
.probe = mvsd_probe, |
|
.remove = mvsd_remove, |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.of_match_table = mvsdio_dt_ids, |
|
}, |
|
}; |
|
|
|
module_platform_driver(mvsd_driver); |
|
|
|
/* maximum card clock frequency (default 50MHz) */ |
|
module_param(maxfreq, int, 0); |
|
|
|
/* force PIO transfers all the time */ |
|
module_param(nodma, int, 0); |
|
|
|
MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); |
|
MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:mvsdio");
|
|
|