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772 lines
21 KiB
772 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller |
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* |
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* Copyright (C) 2015 Endless Mobile, Inc. |
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* Author: Carlo Caione <[email protected]> |
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* Copyright (C) 2017 Martin Blumenstingl <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/platform_device.h> |
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#include <linux/of_platform.h> |
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#include <linux/timer.h> |
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#include <linux/types.h> |
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#include <linux/mmc/host.h> |
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#include <linux/mmc/mmc.h> |
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#include <linux/mmc/sdio.h> |
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#include <linux/mmc/slot-gpio.h> |
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#define MESON_MX_SDIO_ARGU 0x00 |
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#define MESON_MX_SDIO_SEND 0x04 |
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#define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0) |
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#define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8) |
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#define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16) |
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#define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17) |
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#define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18) |
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#define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19) |
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#define MESON_MX_SDIO_SEND_DATA BIT(20) |
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#define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21) |
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#define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24) |
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#define MESON_MX_SDIO_CONF 0x08 |
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#define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0 |
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#define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10 |
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#define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10) |
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#define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11) |
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#define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12) |
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#define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18) |
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#define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19) |
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#define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20) |
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#define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21) |
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#define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23) |
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#define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29) |
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#define MESON_MX_SDIO_IRQS 0x0c |
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#define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0) |
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#define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4) |
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#define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5) |
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#define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6) |
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#define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7) |
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#define MESON_MX_SDIO_IRQS_IF_INT BIT(8) |
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#define MESON_MX_SDIO_IRQS_CMD_INT BIT(9) |
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#define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12) |
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#define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16) |
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#define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17) |
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#define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18) |
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#define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19) |
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#define MESON_MX_SDIO_IRQC 0x10 |
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#define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3) |
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#define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4) |
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#define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6) |
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#define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8) |
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#define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9) |
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#define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10) |
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#define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15) |
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#define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30) |
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#define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31) |
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#define MESON_MX_SDIO_MULT 0x14 |
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#define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0) |
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#define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2) |
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#define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3) |
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#define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4) |
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#define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5) |
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#define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8) |
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#define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10) |
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#define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11) |
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#define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12) |
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#define MESON_MX_SDIO_ADDR 0x18 |
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#define MESON_MX_SDIO_EXT 0x1c |
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#define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16) |
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#define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024) |
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#define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) |
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#define MESON_MX_SDIO_MAX_SLOTS 3 |
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struct meson_mx_mmc_host { |
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struct device *controller_dev; |
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struct clk *parent_clk; |
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struct clk *core_clk; |
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struct clk_divider cfg_div; |
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struct clk *cfg_div_clk; |
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struct clk_fixed_factor fixed_factor; |
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struct clk *fixed_factor_clk; |
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void __iomem *base; |
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int irq; |
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spinlock_t irq_lock; |
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struct timer_list cmd_timeout; |
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unsigned int slot_id; |
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struct mmc_host *mmc; |
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struct mmc_request *mrq; |
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struct mmc_command *cmd; |
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int error; |
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}; |
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static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, |
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u32 val) |
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{ |
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struct meson_mx_mmc_host *host = mmc_priv(mmc); |
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u32 regval; |
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regval = readl(host->base + reg); |
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regval &= ~mask; |
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regval |= (val & mask); |
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writel(regval, host->base + reg); |
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} |
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static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host) |
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{ |
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writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); |
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udelay(2); |
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} |
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static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd) |
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{ |
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if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) |
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return cmd->mrq->cmd; |
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else if (mmc_op_multi(cmd->opcode) && |
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(!cmd->mrq->sbc || cmd->error || cmd->data->error)) |
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return cmd->mrq->stop; |
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else |
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return NULL; |
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} |
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static void meson_mx_mmc_start_cmd(struct mmc_host *mmc, |
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struct mmc_command *cmd) |
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{ |
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struct meson_mx_mmc_host *host = mmc_priv(mmc); |
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unsigned int pack_size; |
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unsigned long irqflags, timeout; |
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u32 mult, send = 0, ext = 0; |
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host->cmd = cmd; |
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if (cmd->busy_timeout) |
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timeout = msecs_to_jiffies(cmd->busy_timeout); |
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else |
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timeout = msecs_to_jiffies(1000); |
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switch (mmc_resp_type(cmd)) { |
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case MMC_RSP_R1: |
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case MMC_RSP_R1B: |
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case MMC_RSP_R3: |
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/* 7 (CMD) + 32 (response) + 7 (CRC) -1 */ |
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send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45); |
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break; |
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case MMC_RSP_R2: |
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/* 7 (CMD) + 120 (response) + 7 (CRC) -1 */ |
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send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133); |
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send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8; |
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break; |
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default: |
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break; |
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} |
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if (!(cmd->flags & MMC_RSP_CRC)) |
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send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7; |
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if (cmd->flags & MMC_RSP_BUSY) |
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send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY; |
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if (cmd->data) { |
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send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, |
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(cmd->data->blocks - 1)); |
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pack_size = cmd->data->blksz * BITS_PER_BYTE; |
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if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
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pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4; |
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else |
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pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1; |
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ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, |
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pack_size); |
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if (cmd->data->flags & MMC_DATA_WRITE) |
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send |= MESON_MX_SDIO_SEND_DATA; |
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else |
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send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA; |
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cmd->data->bytes_xfered = 0; |
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} |
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send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK, |
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(0x40 | cmd->opcode)); |
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spin_lock_irqsave(&host->irq_lock, irqflags); |
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mult = readl(host->base + MESON_MX_SDIO_MULT); |
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mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK; |
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mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id); |
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mult |= BIT(31); |
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writel(mult, host->base + MESON_MX_SDIO_MULT); |
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/* enable the CMD done interrupt */ |
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meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC, |
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MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN, |
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MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); |
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/* clear pending interrupts */ |
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meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS, |
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MESON_MX_SDIO_IRQS_CMD_INT, |
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MESON_MX_SDIO_IRQS_CMD_INT); |
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writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); |
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writel(ext, host->base + MESON_MX_SDIO_EXT); |
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writel(send, host->base + MESON_MX_SDIO_SEND); |
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spin_unlock_irqrestore(&host->irq_lock, irqflags); |
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mod_timer(&host->cmd_timeout, jiffies + timeout); |
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} |
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static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host) |
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{ |
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struct mmc_request *mrq; |
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mrq = host->mrq; |
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if (host->cmd->error) |
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meson_mx_mmc_soft_reset(host); |
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host->mrq = NULL; |
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host->cmd = NULL; |
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mmc_request_done(host->mmc, mrq); |
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} |
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static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
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{ |
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struct meson_mx_mmc_host *host = mmc_priv(mmc); |
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unsigned short vdd = ios->vdd; |
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unsigned long clk_rate = ios->clock; |
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switch (ios->bus_width) { |
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case MMC_BUS_WIDTH_1: |
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meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, |
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MESON_MX_SDIO_CONF_BUS_WIDTH, 0); |
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break; |
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case MMC_BUS_WIDTH_4: |
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meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, |
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MESON_MX_SDIO_CONF_BUS_WIDTH, |
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MESON_MX_SDIO_CONF_BUS_WIDTH); |
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break; |
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case MMC_BUS_WIDTH_8: |
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default: |
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dev_err(mmc_dev(mmc), "unsupported bus width: %d\n", |
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ios->bus_width); |
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host->error = -EINVAL; |
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return; |
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} |
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host->error = clk_set_rate(host->cfg_div_clk, ios->clock); |
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if (host->error) { |
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dev_warn(mmc_dev(mmc), |
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"failed to set MMC clock to %lu: %d\n", |
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clk_rate, host->error); |
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return; |
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} |
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mmc->actual_clock = clk_get_rate(host->cfg_div_clk); |
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switch (ios->power_mode) { |
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case MMC_POWER_OFF: |
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vdd = 0; |
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fallthrough; |
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case MMC_POWER_UP: |
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if (!IS_ERR(mmc->supply.vmmc)) { |
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host->error = mmc_regulator_set_ocr(mmc, |
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mmc->supply.vmmc, |
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vdd); |
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if (host->error) |
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return; |
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} |
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break; |
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} |
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} |
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static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq) |
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{ |
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struct mmc_data *data = mrq->data; |
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int dma_len; |
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struct scatterlist *sg; |
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if (!data) |
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return 0; |
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sg = data->sg; |
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if (sg->offset & 3 || sg->length & 3) { |
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dev_err(mmc_dev(mmc), |
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"unaligned scatterlist: offset %x length %d\n", |
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sg->offset, sg->length); |
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return -EINVAL; |
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} |
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dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, |
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mmc_get_dma_dir(data)); |
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if (dma_len <= 0) { |
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dev_err(mmc_dev(mmc), "dma_map_sg failed\n"); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
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{ |
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struct meson_mx_mmc_host *host = mmc_priv(mmc); |
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struct mmc_command *cmd = mrq->cmd; |
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if (!host->error) |
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host->error = meson_mx_mmc_map_dma(mmc, mrq); |
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if (host->error) { |
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cmd->error = host->error; |
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mmc_request_done(mmc, mrq); |
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return; |
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} |
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host->mrq = mrq; |
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if (mrq->data) |
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writel(sg_dma_address(mrq->data->sg), |
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host->base + MESON_MX_SDIO_ADDR); |
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if (mrq->sbc) |
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meson_mx_mmc_start_cmd(mmc, mrq->sbc); |
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else |
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meson_mx_mmc_start_cmd(mmc, mrq->cmd); |
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} |
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static void meson_mx_mmc_read_response(struct mmc_host *mmc, |
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struct mmc_command *cmd) |
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{ |
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struct meson_mx_mmc_host *host = mmc_priv(mmc); |
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u32 mult; |
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int i, resp[4]; |
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mult = readl(host->base + MESON_MX_SDIO_MULT); |
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mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX; |
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mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK; |
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mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0); |
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writel(mult, host->base + MESON_MX_SDIO_MULT); |
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if (cmd->flags & MMC_RSP_136) { |
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for (i = 0; i <= 3; i++) |
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resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); |
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cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff); |
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cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff); |
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cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff); |
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cmd->resp[3] = (resp[3] << 8); |
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} else if (cmd->flags & MMC_RSP_PRESENT) { |
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cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); |
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} |
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} |
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static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host, |
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u32 irqs, u32 send) |
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{ |
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struct mmc_command *cmd = host->cmd; |
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|
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/* |
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* NOTE: even though it shouldn't happen we sometimes get command |
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* interrupts twice (at least this is what it looks like). Ideally |
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* we find out why this happens and warn here as soon as it occurs. |
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*/ |
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if (!cmd) |
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return IRQ_HANDLED; |
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cmd->error = 0; |
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meson_mx_mmc_read_response(host->mmc, cmd); |
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if (cmd->data) { |
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if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) || |
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(irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK))) |
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cmd->error = -EILSEQ; |
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} else { |
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if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) || |
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(send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7))) |
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cmd->error = -EILSEQ; |
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} |
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return IRQ_WAKE_THREAD; |
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} |
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static irqreturn_t meson_mx_mmc_irq(int irq, void *data) |
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{ |
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struct meson_mx_mmc_host *host = (void *) data; |
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u32 irqs, send; |
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irqreturn_t ret; |
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spin_lock(&host->irq_lock); |
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irqs = readl(host->base + MESON_MX_SDIO_IRQS); |
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send = readl(host->base + MESON_MX_SDIO_SEND); |
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if (irqs & MESON_MX_SDIO_IRQS_CMD_INT) |
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ret = meson_mx_mmc_process_cmd_irq(host, irqs, send); |
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else |
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ret = IRQ_HANDLED; |
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/* finally ACK all pending interrupts */ |
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writel(irqs, host->base + MESON_MX_SDIO_IRQS); |
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spin_unlock(&host->irq_lock); |
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return ret; |
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} |
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static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data) |
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{ |
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struct meson_mx_mmc_host *host = (void *) irq_data; |
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struct mmc_command *cmd = host->cmd, *next_cmd; |
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if (WARN_ON(!cmd)) |
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return IRQ_HANDLED; |
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del_timer_sync(&host->cmd_timeout); |
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if (cmd->data) { |
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dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, |
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cmd->data->sg_len, |
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mmc_get_dma_dir(cmd->data)); |
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cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; |
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} |
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next_cmd = meson_mx_mmc_get_next_cmd(cmd); |
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if (next_cmd) |
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meson_mx_mmc_start_cmd(host->mmc, next_cmd); |
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else |
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meson_mx_mmc_request_done(host); |
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return IRQ_HANDLED; |
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} |
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static void meson_mx_mmc_timeout(struct timer_list *t) |
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{ |
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struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout); |
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unsigned long irqflags; |
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u32 irqc; |
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spin_lock_irqsave(&host->irq_lock, irqflags); |
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|
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/* disable the CMD interrupt */ |
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irqc = readl(host->base + MESON_MX_SDIO_IRQC); |
|
irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN; |
|
writel(irqc, host->base + MESON_MX_SDIO_IRQC); |
|
|
|
spin_unlock_irqrestore(&host->irq_lock, irqflags); |
|
|
|
/* |
|
* skip the timeout handling if the interrupt handler already processed |
|
* the command. |
|
*/ |
|
if (!host->cmd) |
|
return; |
|
|
|
dev_dbg(mmc_dev(host->mmc), |
|
"Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n", |
|
host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), |
|
readl(host->base + MESON_MX_SDIO_ARGU)); |
|
|
|
host->cmd->error = -ETIMEDOUT; |
|
|
|
meson_mx_mmc_request_done(host); |
|
} |
|
|
|
static struct mmc_host_ops meson_mx_mmc_ops = { |
|
.request = meson_mx_mmc_request, |
|
.set_ios = meson_mx_mmc_set_ios, |
|
.get_cd = mmc_gpio_get_cd, |
|
.get_ro = mmc_gpio_get_ro, |
|
}; |
|
|
|
static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent) |
|
{ |
|
struct device_node *slot_node; |
|
struct platform_device *pdev; |
|
|
|
/* |
|
* TODO: the MMC core framework currently does not support |
|
* controllers with multiple slots properly. So we only register |
|
* the first slot for now |
|
*/ |
|
slot_node = of_get_compatible_child(parent->of_node, "mmc-slot"); |
|
if (!slot_node) { |
|
dev_warn(parent, "no 'mmc-slot' sub-node found\n"); |
|
return ERR_PTR(-ENOENT); |
|
} |
|
|
|
pdev = of_platform_device_create(slot_node, NULL, parent); |
|
of_node_put(slot_node); |
|
|
|
return pdev; |
|
} |
|
|
|
static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host) |
|
{ |
|
struct mmc_host *mmc = host->mmc; |
|
struct device *slot_dev = mmc_dev(mmc); |
|
int ret; |
|
|
|
if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) { |
|
dev_err(slot_dev, "missing 'reg' property\n"); |
|
return -EINVAL; |
|
} |
|
|
|
if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) { |
|
dev_err(slot_dev, "invalid 'reg' property value %d\n", |
|
host->slot_id); |
|
return -EINVAL; |
|
} |
|
|
|
/* Get regulators and the supported OCR mask */ |
|
ret = mmc_regulator_get_supply(mmc); |
|
if (ret) |
|
return ret; |
|
|
|
mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE; |
|
mmc->max_seg_size = mmc->max_req_size; |
|
mmc->max_blk_count = |
|
FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, |
|
0xffffffff); |
|
mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, |
|
0xffffffff); |
|
mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS); |
|
mmc->max_blk_size /= BITS_PER_BYTE; |
|
|
|
/* Get the min and max supported clock rates */ |
|
mmc->f_min = clk_round_rate(host->cfg_div_clk, 1); |
|
mmc->f_max = clk_round_rate(host->cfg_div_clk, |
|
clk_get_rate(host->parent_clk)); |
|
|
|
mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY; |
|
mmc->ops = &meson_mx_mmc_ops; |
|
|
|
ret = mmc_of_parse(mmc); |
|
if (ret) |
|
return ret; |
|
|
|
ret = mmc_add_host(mmc); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host) |
|
{ |
|
struct clk_init_data init; |
|
const char *clk_div_parent, *clk_fixed_factor_parent; |
|
|
|
clk_fixed_factor_parent = __clk_get_name(host->parent_clk); |
|
init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, |
|
"%s#fixed_factor", |
|
dev_name(host->controller_dev)); |
|
if (!init.name) |
|
return -ENOMEM; |
|
|
|
init.ops = &clk_fixed_factor_ops; |
|
init.flags = 0; |
|
init.parent_names = &clk_fixed_factor_parent; |
|
init.num_parents = 1; |
|
host->fixed_factor.div = 2; |
|
host->fixed_factor.mult = 1; |
|
host->fixed_factor.hw.init = &init; |
|
|
|
host->fixed_factor_clk = devm_clk_register(host->controller_dev, |
|
&host->fixed_factor.hw); |
|
if (WARN_ON(IS_ERR(host->fixed_factor_clk))) |
|
return PTR_ERR(host->fixed_factor_clk); |
|
|
|
clk_div_parent = __clk_get_name(host->fixed_factor_clk); |
|
init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, |
|
"%s#div", dev_name(host->controller_dev)); |
|
if (!init.name) |
|
return -ENOMEM; |
|
|
|
init.ops = &clk_divider_ops; |
|
init.flags = CLK_SET_RATE_PARENT; |
|
init.parent_names = &clk_div_parent; |
|
init.num_parents = 1; |
|
host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; |
|
host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; |
|
host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; |
|
host->cfg_div.hw.init = &init; |
|
host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO; |
|
|
|
host->cfg_div_clk = devm_clk_register(host->controller_dev, |
|
&host->cfg_div.hw); |
|
if (WARN_ON(IS_ERR(host->cfg_div_clk))) |
|
return PTR_ERR(host->cfg_div_clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int meson_mx_mmc_probe(struct platform_device *pdev) |
|
{ |
|
struct platform_device *slot_pdev; |
|
struct mmc_host *mmc; |
|
struct meson_mx_mmc_host *host; |
|
int ret, irq; |
|
u32 conf; |
|
|
|
slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev); |
|
if (!slot_pdev) |
|
return -ENODEV; |
|
else if (IS_ERR(slot_pdev)) |
|
return PTR_ERR(slot_pdev); |
|
|
|
mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev); |
|
if (!mmc) { |
|
ret = -ENOMEM; |
|
goto error_unregister_slot_pdev; |
|
} |
|
|
|
host = mmc_priv(mmc); |
|
host->mmc = mmc; |
|
host->controller_dev = &pdev->dev; |
|
|
|
spin_lock_init(&host->irq_lock); |
|
timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0); |
|
|
|
platform_set_drvdata(pdev, host); |
|
|
|
host->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(host->base)) { |
|
ret = PTR_ERR(host->base); |
|
goto error_free_mmc; |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
ret = irq; |
|
goto error_free_mmc; |
|
} |
|
|
|
ret = devm_request_threaded_irq(host->controller_dev, irq, |
|
meson_mx_mmc_irq, |
|
meson_mx_mmc_irq_thread, IRQF_ONESHOT, |
|
NULL, host); |
|
if (ret) |
|
goto error_free_mmc; |
|
|
|
host->core_clk = devm_clk_get(host->controller_dev, "core"); |
|
if (IS_ERR(host->core_clk)) { |
|
ret = PTR_ERR(host->core_clk); |
|
goto error_free_mmc; |
|
} |
|
|
|
host->parent_clk = devm_clk_get(host->controller_dev, "clkin"); |
|
if (IS_ERR(host->parent_clk)) { |
|
ret = PTR_ERR(host->parent_clk); |
|
goto error_free_mmc; |
|
} |
|
|
|
ret = meson_mx_mmc_register_clks(host); |
|
if (ret) |
|
goto error_free_mmc; |
|
|
|
ret = clk_prepare_enable(host->core_clk); |
|
if (ret) { |
|
dev_err(host->controller_dev, "Failed to enable core clock\n"); |
|
goto error_free_mmc; |
|
} |
|
|
|
ret = clk_prepare_enable(host->cfg_div_clk); |
|
if (ret) { |
|
dev_err(host->controller_dev, "Failed to enable MMC clock\n"); |
|
goto error_disable_core_clk; |
|
} |
|
|
|
conf = 0; |
|
conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39); |
|
conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3); |
|
conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2); |
|
conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2); |
|
writel(conf, host->base + MESON_MX_SDIO_CONF); |
|
|
|
meson_mx_mmc_soft_reset(host); |
|
|
|
ret = meson_mx_mmc_add_host(host); |
|
if (ret) |
|
goto error_disable_clks; |
|
|
|
return 0; |
|
|
|
error_disable_clks: |
|
clk_disable_unprepare(host->cfg_div_clk); |
|
error_disable_core_clk: |
|
clk_disable_unprepare(host->core_clk); |
|
error_free_mmc: |
|
mmc_free_host(mmc); |
|
error_unregister_slot_pdev: |
|
of_platform_device_destroy(&slot_pdev->dev, NULL); |
|
return ret; |
|
} |
|
|
|
static int meson_mx_mmc_remove(struct platform_device *pdev) |
|
{ |
|
struct meson_mx_mmc_host *host = platform_get_drvdata(pdev); |
|
struct device *slot_dev = mmc_dev(host->mmc); |
|
|
|
del_timer_sync(&host->cmd_timeout); |
|
|
|
mmc_remove_host(host->mmc); |
|
|
|
of_platform_device_destroy(slot_dev, NULL); |
|
|
|
clk_disable_unprepare(host->cfg_div_clk); |
|
clk_disable_unprepare(host->core_clk); |
|
|
|
mmc_free_host(host->mmc); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id meson_mx_mmc_of_match[] = { |
|
{ .compatible = "amlogic,meson8-sdio", }, |
|
{ .compatible = "amlogic,meson8b-sdio", }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match); |
|
|
|
static struct platform_driver meson_mx_mmc_driver = { |
|
.probe = meson_mx_mmc_probe, |
|
.remove = meson_mx_mmc_remove, |
|
.driver = { |
|
.name = "meson-mx-sdio", |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.of_match_table = of_match_ptr(meson_mx_mmc_of_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(meson_mx_mmc_driver); |
|
|
|
MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver"); |
|
MODULE_AUTHOR("Carlo Caione <[email protected]>"); |
|
MODULE_AUTHOR("Martin Blumenstingl <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|