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955 lines
28 KiB
955 lines
28 KiB
/** |
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* Broadcom Secondary Memory Interface driver |
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* |
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* Written by Luke Wren <[email protected]> |
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* Copyright (c) 2015, Raspberry Pi (Trading) Ltd. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions, and the following disclaimer, |
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* without modification. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The names of the above-listed copyright holders may not be used |
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* to endorse or promote products derived from this software without |
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* specific prior written permission. |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") version 2, as published by the Free |
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* Software Foundation. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/mm.h> |
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#include <linux/slab.h> |
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#include <linux/pagemap.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmaengine.h> |
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#include <linux/semaphore.h> |
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#include <linux/spinlock.h> |
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#include <linux/io.h> |
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#define BCM2835_SMI_IMPLEMENTATION |
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#include <linux/broadcom/bcm2835_smi.h> |
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#define DRIVER_NAME "smi-bcm2835" |
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#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE) |
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#define DMA_WRITE_TO_MEM true |
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#define DMA_READ_FROM_MEM false |
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struct bcm2835_smi_instance { |
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struct device *dev; |
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struct smi_settings settings; |
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__iomem void *smi_regs_ptr; |
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dma_addr_t smi_regs_busaddr; |
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struct dma_chan *dma_chan; |
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struct dma_slave_config dma_config; |
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struct bcm2835_smi_bounce_info bounce; |
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|
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struct scatterlist buffer_sgl; |
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|
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struct clk *clk; |
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/* Sometimes we are called into in an atomic context (e.g. by |
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JFFS2 + MTD) so we can't use a mutex */ |
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spinlock_t transaction_lock; |
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}; |
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|
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/**************************************************************************** |
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* |
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* SMI peripheral setup |
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* |
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***************************************************************************/ |
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static inline void write_smi_reg(struct bcm2835_smi_instance *inst, |
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u32 val, unsigned reg) |
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{ |
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writel(val, inst->smi_regs_ptr + reg); |
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} |
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static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) |
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{ |
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return readl(inst->smi_regs_ptr + reg); |
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} |
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/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */ |
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#define _CONCAT(x, y) x##y |
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#define CONCAT(x, y) _CONCAT(x, y) |
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#define SET_BIT_FIELD(dest, field, bits) ((dest) = \ |
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((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \ |
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CONCAT(field, _MASK))) |
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#define GET_BIT_FIELD(src, field) (((src) & \ |
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CONCAT(field, _MASK)) >> CONCAT(field, _OFFS)) |
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|
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static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst, |
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const char *label) |
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{ |
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dev_err(inst->dev, "SMI context dump: %s", label); |
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dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS)); |
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dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL)); |
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dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0)); |
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dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0)); |
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dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC)); |
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dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD)); |
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dev_err(inst->dev, " "); |
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} |
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static inline void smi_dump_context(struct bcm2835_smi_instance *inst) |
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{ |
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smi_dump_context_labelled(inst, ""); |
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} |
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static void smi_get_default_settings(struct bcm2835_smi_instance *inst) |
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{ |
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struct smi_settings *settings = &inst->settings; |
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settings->data_width = SMI_WIDTH_16BIT; |
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settings->pack_data = true; |
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settings->read_setup_time = 1; |
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settings->read_hold_time = 1; |
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settings->read_pace_time = 1; |
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settings->read_strobe_time = 3; |
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settings->write_setup_time = settings->read_setup_time; |
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settings->write_hold_time = settings->read_hold_time; |
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settings->write_pace_time = settings->read_pace_time; |
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settings->write_strobe_time = settings->read_strobe_time; |
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settings->dma_enable = true; |
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settings->dma_passthrough_enable = false; |
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settings->dma_read_thresh = 0x01; |
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settings->dma_write_thresh = 0x3f; |
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settings->dma_panic_read_thresh = 0x20; |
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settings->dma_panic_write_thresh = 0x20; |
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} |
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void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst) |
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{ |
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struct smi_settings *settings = &inst->settings; |
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int smidsr_temp = 0, smidsw_temp = 0, smics_temp, |
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smidcs_temp, smidc_temp = 0; |
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spin_lock(&inst->transaction_lock); |
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/* temporarily disable the peripheral: */ |
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smics_temp = read_smi_reg(inst, SMICS); |
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write_smi_reg(inst, 0, SMICS); |
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smidcs_temp = read_smi_reg(inst, SMIDCS); |
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write_smi_reg(inst, 0, SMIDCS); |
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if (settings->pack_data) |
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smics_temp |= SMICS_PXLDAT; |
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else |
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smics_temp &= ~SMICS_PXLDAT; |
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SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width); |
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SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time); |
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SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time); |
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SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time); |
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SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time); |
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write_smi_reg(inst, smidsr_temp, SMIDSR0); |
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SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width); |
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if (settings->data_width == SMI_WIDTH_8BIT) |
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smidsw_temp |= SMIDSW_WSWAP; |
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else |
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smidsw_temp &= ~SMIDSW_WSWAP; |
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SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time); |
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SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time); |
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SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time); |
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SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE, |
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settings->write_strobe_time); |
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write_smi_reg(inst, smidsw_temp, SMIDSW0); |
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SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh); |
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SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh); |
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SET_BIT_FIELD(smidc_temp, SMIDC_PANICR, |
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settings->dma_panic_read_thresh); |
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SET_BIT_FIELD(smidc_temp, SMIDC_PANICW, |
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settings->dma_panic_write_thresh); |
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if (settings->dma_passthrough_enable) { |
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smidc_temp |= SMIDC_DMAP; |
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smidsr_temp |= SMIDSR_RDREQ; |
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write_smi_reg(inst, smidsr_temp, SMIDSR0); |
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smidsw_temp |= SMIDSW_WDREQ; |
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write_smi_reg(inst, smidsw_temp, SMIDSW0); |
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} else |
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smidc_temp &= ~SMIDC_DMAP; |
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if (settings->dma_enable) |
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smidc_temp |= SMIDC_DMAEN; |
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else |
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smidc_temp &= ~SMIDC_DMAEN; |
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write_smi_reg(inst, smidc_temp, SMIDC); |
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/* re-enable (if was previously enabled) */ |
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write_smi_reg(inst, smics_temp, SMICS); |
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write_smi_reg(inst, smidcs_temp, SMIDCS); |
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spin_unlock(&inst->transaction_lock); |
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} |
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EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings); |
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struct smi_settings *bcm2835_smi_get_settings_from_regs |
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(struct bcm2835_smi_instance *inst) |
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{ |
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struct smi_settings *settings = &inst->settings; |
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int smidsr, smidsw, smidc; |
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spin_lock(&inst->transaction_lock); |
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smidsr = read_smi_reg(inst, SMIDSR0); |
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smidsw = read_smi_reg(inst, SMIDSW0); |
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smidc = read_smi_reg(inst, SMIDC); |
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settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? |
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true : false; |
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settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); |
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settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); |
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settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); |
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settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); |
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settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); |
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settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); |
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settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); |
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settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); |
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settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); |
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settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); |
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settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); |
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settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); |
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settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); |
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settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; |
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settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; |
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spin_unlock(&inst->transaction_lock); |
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return settings; |
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} |
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EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs); |
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static inline void smi_set_address(struct bcm2835_smi_instance *inst, |
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unsigned int address) |
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{ |
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int smia_temp = 0, smida_temp = 0; |
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SET_BIT_FIELD(smia_temp, SMIA_ADDR, address); |
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SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address); |
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/* Write to both address registers - user doesn't care whether we're |
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doing programmed or direct transfers. */ |
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write_smi_reg(inst, smia_temp, SMIA); |
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write_smi_reg(inst, smida_temp, SMIDA); |
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} |
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static void smi_setup_regs(struct bcm2835_smi_instance *inst) |
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{ |
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dev_dbg(inst->dev, "Initialising SMI registers..."); |
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/* Disable the peripheral if already enabled */ |
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write_smi_reg(inst, 0, SMICS); |
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write_smi_reg(inst, 0, SMIDCS); |
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smi_get_default_settings(inst); |
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bcm2835_smi_set_regs_from_settings(inst); |
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smi_set_address(inst, 0); |
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write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS); |
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write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE, |
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SMIDCS); |
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} |
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/**************************************************************************** |
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* |
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* Low-level SMI access functions |
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* Other modules should use the exported higher-level functions e.g. |
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* bcm2835_smi_write_buf() unless they have a good reason to use these |
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* |
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***************************************************************************/ |
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static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst) |
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{ |
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int timeout = 0; |
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write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS); |
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write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS); |
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/* Make sure things happen in the right order...*/ |
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mb(); |
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while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && |
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++timeout < 10000) |
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; |
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if (timeout < 10000) |
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return read_smi_reg(inst, SMIDD); |
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dev_err(inst->dev, |
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"SMI direct read timed out (is the clock set up correctly?)"); |
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return 0; |
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} |
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static inline void smi_write_single_word(struct bcm2835_smi_instance *inst, |
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uint32_t data) |
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{ |
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int timeout = 0; |
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write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS); |
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write_smi_reg(inst, data, SMIDD); |
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write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START, |
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SMIDCS); |
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while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && |
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++timeout < 10000) |
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; |
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if (timeout >= 10000) |
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dev_err(inst->dev, |
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"SMI direct write timed out (is the clock set up correctly?)"); |
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} |
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|
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/* Initiates a programmed read into the read FIFO. It is up to the caller to |
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* read data from the FIFO - either via paced DMA transfer, |
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* or polling SMICS_RXD to check whether data is available. |
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* SMICS_ACTIVE will go low upon completion. */ |
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static void smi_init_programmed_read(struct bcm2835_smi_instance *inst, |
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int num_transfers) |
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{ |
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int smics_temp; |
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/* Disable the peripheral: */ |
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smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); |
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write_smi_reg(inst, smics_temp, SMICS); |
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while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) |
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; |
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|
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/* Program the transfer count: */ |
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write_smi_reg(inst, num_transfers, SMIL); |
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|
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/* re-enable and start: */ |
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smics_temp |= SMICS_ENABLE; |
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write_smi_reg(inst, smics_temp, SMICS); |
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smics_temp |= SMICS_CLEAR; |
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/* Just to be certain: */ |
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mb(); |
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while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) |
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; |
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write_smi_reg(inst, smics_temp, SMICS); |
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smics_temp |= SMICS_START; |
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write_smi_reg(inst, smics_temp, SMICS); |
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} |
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/* Initiates a programmed write sequence, using data from the write FIFO. |
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* It is up to the caller to initiate a DMA transfer before calling, |
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* or use another method to keep the write FIFO topped up. |
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* SMICS_ACTIVE will go low upon completion. |
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*/ |
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static void smi_init_programmed_write(struct bcm2835_smi_instance *inst, |
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int num_transfers) |
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{ |
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int smics_temp; |
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|
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/* Disable the peripheral: */ |
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smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; |
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write_smi_reg(inst, smics_temp, SMICS); |
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while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) |
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; |
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|
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/* Program the transfer count: */ |
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write_smi_reg(inst, num_transfers, SMIL); |
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|
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/* setup, re-enable and start: */ |
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smics_temp |= SMICS_WRITE | SMICS_ENABLE; |
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write_smi_reg(inst, smics_temp, SMICS); |
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smics_temp |= SMICS_START; |
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write_smi_reg(inst, smics_temp, SMICS); |
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} |
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|
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/* Initiate a read and then poll FIFO for data, reading out as it appears. */ |
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static void smi_read_fifo(struct bcm2835_smi_instance *inst, |
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uint32_t *dest, int n_bytes) |
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{ |
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if (read_smi_reg(inst, SMICS) & SMICS_RXD) { |
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smi_dump_context_labelled(inst, |
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"WARNING: read FIFO not empty at start of read call."); |
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while (read_smi_reg(inst, SMICS)) |
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; |
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} |
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|
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/* Dispatch the read: */ |
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if (inst->settings.data_width == SMI_WIDTH_8BIT) |
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smi_init_programmed_read(inst, n_bytes); |
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else if (inst->settings.data_width == SMI_WIDTH_16BIT) |
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smi_init_programmed_read(inst, n_bytes / 2); |
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else { |
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dev_err(inst->dev, "Unsupported data width for read."); |
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return; |
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} |
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/* Poll FIFO to keep it empty */ |
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while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) |
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if (read_smi_reg(inst, SMICS) & SMICS_RXD) |
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*dest++ = read_smi_reg(inst, SMID); |
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|
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/* Ensure that the FIFO is emptied */ |
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if (read_smi_reg(inst, SMICS) & SMICS_RXD) { |
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int fifo_count; |
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|
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fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), |
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SMIFD_FCNT); |
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while (fifo_count--) |
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*dest++ = read_smi_reg(inst, SMID); |
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} |
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|
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if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) |
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smi_dump_context_labelled(inst, |
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"WARNING: transaction finished but done bit not set."); |
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|
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if (read_smi_reg(inst, SMICS) & SMICS_RXD) |
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smi_dump_context_labelled(inst, |
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"WARNING: read FIFO not empty at end of read call."); |
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|
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} |
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/* Initiate a write, and then keep the FIFO topped up. */ |
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static void smi_write_fifo(struct bcm2835_smi_instance *inst, |
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uint32_t *src, int n_bytes) |
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{ |
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int i, timeout = 0; |
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|
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/* Empty FIFOs if not already so */ |
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if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) { |
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smi_dump_context_labelled(inst, |
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"WARNING: write fifo not empty at start of write call."); |
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write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR, |
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SMICS); |
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} |
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/* Initiate the transfer */ |
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if (inst->settings.data_width == SMI_WIDTH_8BIT) |
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smi_init_programmed_write(inst, n_bytes); |
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else if (inst->settings.data_width == SMI_WIDTH_16BIT) |
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smi_init_programmed_write(inst, n_bytes / 2); |
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else { |
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dev_err(inst->dev, "Unsupported data width for write."); |
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return; |
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} |
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/* Fill the FIFO: */ |
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for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) { |
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while (!(read_smi_reg(inst, SMICS) & SMICS_TXD)) |
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; |
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write_smi_reg(inst, *src++, SMID); |
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} |
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/* Busy wait... */ |
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while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout < |
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1000000) |
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; |
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if (timeout >= 1000000) |
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smi_dump_context_labelled(inst, |
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"Timed out on write operation!"); |
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if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) |
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smi_dump_context_labelled(inst, |
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"WARNING: FIFO not empty at end of write operation."); |
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} |
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|
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/**************************************************************************** |
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* |
|
* SMI DMA operations |
|
* |
|
***************************************************************************/ |
|
|
|
/* Disable SMI and put it into the correct direction before doing DMA setup. |
|
Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */ |
|
static void smi_disable(struct bcm2835_smi_instance *inst, |
|
enum dma_transfer_direction direction) |
|
{ |
|
int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; |
|
|
|
if (direction == DMA_DEV_TO_MEM) |
|
smics_temp &= ~SMICS_WRITE; |
|
else |
|
smics_temp |= SMICS_WRITE; |
|
write_smi_reg(inst, smics_temp, SMICS); |
|
while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) |
|
; |
|
} |
|
|
|
static struct scatterlist *smi_scatterlist_from_buffer( |
|
struct bcm2835_smi_instance *inst, |
|
dma_addr_t buf, |
|
size_t len, |
|
struct scatterlist *sg) |
|
{ |
|
sg_init_table(sg, 1); |
|
sg_dma_address(sg) = buf; |
|
sg_dma_len(sg) = len; |
|
return sg; |
|
} |
|
|
|
static void smi_dma_callback_user_copy(void *param) |
|
{ |
|
/* Notify the bottom half that a chunk is ready for user copy */ |
|
struct bcm2835_smi_instance *inst = |
|
(struct bcm2835_smi_instance *)param; |
|
|
|
up(&inst->bounce.callback_sem); |
|
} |
|
|
|
/* Creates a descriptor, assigns the given callback, and submits the |
|
descriptor to dmaengine. Does not block - can queue up multiple |
|
descriptors and then wait for them all to complete. |
|
sg_len is the number of control blocks, NOT the number of bytes. |
|
dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM. |
|
callback can be NULL - in this case it is not called. */ |
|
static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl( |
|
struct bcm2835_smi_instance *inst, |
|
struct scatterlist *sgl, |
|
size_t sg_len, |
|
enum dma_transfer_direction dir, |
|
dma_async_tx_callback callback) |
|
{ |
|
struct dma_async_tx_descriptor *desc; |
|
|
|
desc = dmaengine_prep_slave_sg(inst->dma_chan, |
|
sgl, |
|
sg_len, |
|
dir, |
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK | |
|
DMA_PREP_FENCE); |
|
if (!desc) { |
|
dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); |
|
write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE, |
|
SMICS); |
|
while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) |
|
cpu_relax(); |
|
write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE, |
|
SMICS); |
|
return NULL; |
|
} |
|
desc->callback = callback; |
|
desc->callback_param = inst; |
|
if (dmaengine_submit(desc) < 0) |
|
return NULL; |
|
return desc; |
|
} |
|
|
|
/* NB this function blocks until the transfer is complete */ |
|
static void |
|
smi_dma_read_sgl(struct bcm2835_smi_instance *inst, |
|
struct scatterlist *sgl, size_t sg_len, size_t n_bytes) |
|
{ |
|
struct dma_async_tx_descriptor *desc; |
|
|
|
/* Disable SMI and set to read before dispatching DMA - if SMI is in |
|
* write mode and TX fifo is empty, it will generate a DREQ which may |
|
* cause the read DMA to complete before the SMI read command is even |
|
* dispatched! We want to dispatch DMA before SMI read so that reading |
|
* is gapless, for logic analyser. |
|
*/ |
|
|
|
smi_disable(inst, DMA_DEV_TO_MEM); |
|
|
|
desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL); |
|
dma_async_issue_pending(inst->dma_chan); |
|
|
|
if (inst->settings.data_width == SMI_WIDTH_8BIT) |
|
smi_init_programmed_read(inst, n_bytes); |
|
else |
|
smi_init_programmed_read(inst, n_bytes / 2); |
|
|
|
if (dma_wait_for_async_tx(desc) == DMA_ERROR) |
|
smi_dump_context_labelled(inst, "DMA timeout!"); |
|
} |
|
|
|
static void |
|
smi_dma_write_sgl(struct bcm2835_smi_instance *inst, |
|
struct scatterlist *sgl, size_t sg_len, size_t n_bytes) |
|
{ |
|
struct dma_async_tx_descriptor *desc; |
|
|
|
if (inst->settings.data_width == SMI_WIDTH_8BIT) |
|
smi_init_programmed_write(inst, n_bytes); |
|
else |
|
smi_init_programmed_write(inst, n_bytes / 2); |
|
|
|
desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL); |
|
dma_async_issue_pending(inst->dma_chan); |
|
|
|
if (dma_wait_for_async_tx(desc) == DMA_ERROR) |
|
smi_dump_context_labelled(inst, "DMA timeout!"); |
|
else |
|
/* Wait for SMI to finish our writes */ |
|
while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) |
|
cpu_relax(); |
|
} |
|
|
|
ssize_t bcm2835_smi_user_dma( |
|
struct bcm2835_smi_instance *inst, |
|
enum dma_transfer_direction dma_dir, |
|
char __user *user_ptr, size_t count, |
|
struct bcm2835_smi_bounce_info **bounce) |
|
{ |
|
int chunk_no = 0, chunk_size, count_left = count; |
|
struct scatterlist *sgl; |
|
void (*init_trans_func)(struct bcm2835_smi_instance *, int); |
|
|
|
spin_lock(&inst->transaction_lock); |
|
|
|
if (dma_dir == DMA_DEV_TO_MEM) |
|
init_trans_func = smi_init_programmed_read; |
|
else |
|
init_trans_func = smi_init_programmed_write; |
|
|
|
smi_disable(inst, dma_dir); |
|
|
|
sema_init(&inst->bounce.callback_sem, 0); |
|
if (bounce) |
|
*bounce = &inst->bounce; |
|
while (count_left) { |
|
chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? |
|
DMA_BOUNCE_BUFFER_SIZE : count_left; |
|
if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) { |
|
sgl = |
|
&inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; |
|
} else { |
|
sgl = smi_scatterlist_from_buffer( |
|
inst, |
|
inst->bounce.phys[ |
|
chunk_no % DMA_BOUNCE_BUFFER_COUNT], |
|
chunk_size, |
|
&inst->buffer_sgl); |
|
} |
|
|
|
if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir, |
|
smi_dma_callback_user_copy |
|
)) { |
|
dev_err(inst->dev, "sgl submit failed"); |
|
count = 0; |
|
goto out; |
|
} |
|
count_left -= chunk_size; |
|
chunk_no++; |
|
} |
|
dma_async_issue_pending(inst->dma_chan); |
|
|
|
if (inst->settings.data_width == SMI_WIDTH_8BIT) |
|
init_trans_func(inst, count); |
|
else if (inst->settings.data_width == SMI_WIDTH_16BIT) |
|
init_trans_func(inst, count / 2); |
|
out: |
|
spin_unlock(&inst->transaction_lock); |
|
return count; |
|
} |
|
EXPORT_SYMBOL(bcm2835_smi_user_dma); |
|
|
|
|
|
/**************************************************************************** |
|
* |
|
* High level buffer transfer functions - for use by other drivers |
|
* |
|
***************************************************************************/ |
|
|
|
/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */ |
|
void bcm2835_smi_write_buf( |
|
struct bcm2835_smi_instance *inst, |
|
const void *buf, size_t n_bytes) |
|
{ |
|
int odd_bytes = n_bytes & 0x3; |
|
|
|
n_bytes -= odd_bytes; |
|
|
|
spin_lock(&inst->transaction_lock); |
|
|
|
if (n_bytes > DMA_THRESHOLD_BYTES) { |
|
dma_addr_t phy_addr = dma_map_single( |
|
inst->dev, |
|
(void *)buf, |
|
n_bytes, |
|
DMA_TO_DEVICE); |
|
struct scatterlist *sgl = |
|
smi_scatterlist_from_buffer(inst, phy_addr, n_bytes, |
|
&inst->buffer_sgl); |
|
|
|
if (!sgl) { |
|
smi_dump_context_labelled(inst, |
|
"Error: could not create scatterlist for write!"); |
|
goto out; |
|
} |
|
smi_dma_write_sgl(inst, sgl, 1, n_bytes); |
|
|
|
dma_unmap_single |
|
(inst->dev, phy_addr, n_bytes, DMA_TO_DEVICE); |
|
} else if (n_bytes) { |
|
smi_write_fifo(inst, (uint32_t *) buf, n_bytes); |
|
} |
|
buf += n_bytes; |
|
|
|
if (inst->settings.data_width == SMI_WIDTH_8BIT) { |
|
while (odd_bytes--) |
|
smi_write_single_word(inst, *(uint8_t *) (buf++)); |
|
} else { |
|
while (odd_bytes >= 2) { |
|
smi_write_single_word(inst, *(uint16_t *)buf); |
|
buf += 2; |
|
odd_bytes -= 2; |
|
} |
|
if (odd_bytes) { |
|
/* Reading an odd number of bytes on a 16 bit bus is |
|
a user bug. It's kinder to fail early and tell them |
|
than to e.g. transparently give them the bottom byte |
|
of a 16 bit transfer. */ |
|
dev_err(inst->dev, |
|
"WARNING: odd number of bytes specified for wide transfer."); |
|
dev_err(inst->dev, |
|
"At least one byte dropped as a result."); |
|
dump_stack(); |
|
} |
|
} |
|
out: |
|
spin_unlock(&inst->transaction_lock); |
|
} |
|
EXPORT_SYMBOL(bcm2835_smi_write_buf); |
|
|
|
void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst, |
|
void *buf, size_t n_bytes) |
|
{ |
|
|
|
/* SMI is inherently 32-bit, which causes surprising amounts of mess |
|
for bytes % 4 != 0. Easiest to avoid this mess altogether |
|
by handling remainder separately. */ |
|
int odd_bytes = n_bytes & 0x3; |
|
|
|
spin_lock(&inst->transaction_lock); |
|
n_bytes -= odd_bytes; |
|
if (n_bytes > DMA_THRESHOLD_BYTES) { |
|
dma_addr_t phy_addr = dma_map_single(inst->dev, |
|
buf, n_bytes, |
|
DMA_FROM_DEVICE); |
|
struct scatterlist *sgl = smi_scatterlist_from_buffer( |
|
inst, phy_addr, n_bytes, |
|
&inst->buffer_sgl); |
|
if (!sgl) { |
|
smi_dump_context_labelled(inst, |
|
"Error: could not create scatterlist for read!"); |
|
goto out; |
|
} |
|
smi_dma_read_sgl(inst, sgl, 1, n_bytes); |
|
dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_FROM_DEVICE); |
|
} else if (n_bytes) { |
|
smi_read_fifo(inst, (uint32_t *)buf, n_bytes); |
|
} |
|
buf += n_bytes; |
|
|
|
if (inst->settings.data_width == SMI_WIDTH_8BIT) { |
|
while (odd_bytes--) |
|
*((uint8_t *) (buf++)) = smi_read_single_word(inst); |
|
} else { |
|
while (odd_bytes >= 2) { |
|
*(uint16_t *) buf = smi_read_single_word(inst); |
|
buf += 2; |
|
odd_bytes -= 2; |
|
} |
|
if (odd_bytes) { |
|
dev_err(inst->dev, |
|
"WARNING: odd number of bytes specified for wide transfer."); |
|
dev_err(inst->dev, |
|
"At least one byte dropped as a result."); |
|
dump_stack(); |
|
} |
|
} |
|
out: |
|
spin_unlock(&inst->transaction_lock); |
|
} |
|
EXPORT_SYMBOL(bcm2835_smi_read_buf); |
|
|
|
void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, |
|
unsigned int address) |
|
{ |
|
spin_lock(&inst->transaction_lock); |
|
smi_set_address(inst, address); |
|
spin_unlock(&inst->transaction_lock); |
|
} |
|
EXPORT_SYMBOL(bcm2835_smi_set_address); |
|
|
|
struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node) |
|
{ |
|
struct platform_device *pdev; |
|
|
|
if (!node) |
|
return NULL; |
|
|
|
pdev = of_find_device_by_node(node); |
|
if (!pdev) |
|
return NULL; |
|
|
|
return platform_get_drvdata(pdev); |
|
} |
|
EXPORT_SYMBOL(bcm2835_smi_get); |
|
|
|
/**************************************************************************** |
|
* |
|
* bcm2835_smi_probe - called when the driver is loaded. |
|
* |
|
***************************************************************************/ |
|
|
|
static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst) |
|
{ |
|
int i, rv = 0; |
|
|
|
inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx"); |
|
|
|
inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID; |
|
inst->dma_config.dst_addr = inst->dma_config.src_addr; |
|
/* Direction unimportant - always overridden by prep_slave_sg */ |
|
inst->dma_config.direction = DMA_DEV_TO_MEM; |
|
dmaengine_slave_config(inst->dma_chan, &inst->dma_config); |
|
/* Alloc and map bounce buffers */ |
|
for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) { |
|
inst->bounce.buffer[i] = |
|
dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE, |
|
&inst->bounce.phys[i], |
|
GFP_KERNEL); |
|
if (!inst->bounce.buffer[i]) { |
|
dev_err(inst->dev, "Could not allocate buffer!"); |
|
rv = -ENOMEM; |
|
break; |
|
} |
|
smi_scatterlist_from_buffer( |
|
inst, |
|
inst->bounce.phys[i], |
|
DMA_BOUNCE_BUFFER_SIZE, |
|
&inst->bounce.sgl[i] |
|
); |
|
} |
|
|
|
return rv; |
|
} |
|
|
|
static int bcm2835_smi_probe(struct platform_device *pdev) |
|
{ |
|
int err; |
|
struct device *dev = &pdev->dev; |
|
struct device_node *node = dev->of_node; |
|
struct resource *ioresource; |
|
struct bcm2835_smi_instance *inst; |
|
const __be32 *addr; |
|
|
|
/* We require device tree support */ |
|
if (!node) |
|
return -EINVAL; |
|
/* Allocate buffers and instance data */ |
|
inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance), |
|
GFP_KERNEL); |
|
if (!inst) |
|
return -ENOMEM; |
|
|
|
inst->dev = dev; |
|
spin_lock_init(&inst->transaction_lock); |
|
|
|
ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource); |
|
if (IS_ERR(inst->smi_regs_ptr)) { |
|
err = PTR_ERR(inst->smi_regs_ptr); |
|
goto err; |
|
} |
|
addr = of_get_address(node, 0, NULL, NULL); |
|
inst->smi_regs_busaddr = be32_to_cpu(*addr); |
|
|
|
err = bcm2835_smi_dma_setup(inst); |
|
if (err) |
|
goto err; |
|
|
|
/* request clock */ |
|
inst->clk = devm_clk_get(dev, NULL); |
|
if (!inst->clk) |
|
goto err; |
|
clk_prepare_enable(inst->clk); |
|
|
|
/* Finally, do peripheral setup */ |
|
smi_setup_regs(inst); |
|
|
|
platform_set_drvdata(pdev, inst); |
|
|
|
dev_info(inst->dev, "initialised"); |
|
|
|
return 0; |
|
err: |
|
kfree(inst); |
|
return err; |
|
} |
|
|
|
/**************************************************************************** |
|
* |
|
* bcm2835_smi_remove - called when the driver is unloaded. |
|
* |
|
***************************************************************************/ |
|
|
|
static int bcm2835_smi_remove(struct platform_device *pdev) |
|
{ |
|
struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev); |
|
struct device *dev = inst->dev; |
|
|
|
dmaengine_terminate_all(inst->dma_chan); |
|
dma_release_channel(inst->dma_chan); |
|
|
|
clk_disable_unprepare(inst->clk); |
|
|
|
dev_info(dev, "SMI device removed - OK"); |
|
return 0; |
|
} |
|
|
|
/**************************************************************************** |
|
* |
|
* Register the driver with device tree |
|
* |
|
***************************************************************************/ |
|
|
|
static const struct of_device_id bcm2835_smi_of_match[] = { |
|
{.compatible = "brcm,bcm2835-smi",}, |
|
{ /* sentinel */ }, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match); |
|
|
|
static struct platform_driver bcm2835_smi_driver = { |
|
.probe = bcm2835_smi_probe, |
|
.remove = bcm2835_smi_remove, |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.owner = THIS_MODULE, |
|
.of_match_table = bcm2835_smi_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(bcm2835_smi_driver); |
|
|
|
MODULE_ALIAS("platform:smi-bcm2835"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface"); |
|
MODULE_AUTHOR("Luke Wren <[email protected]>");
|
|
|