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273 lines
6.9 KiB
273 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Renesas IRQC Driver |
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* |
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* Copyright (C) 2013 Magnus Damm |
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*/ |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/err.h> |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/pm_runtime.h> |
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#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ |
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#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */ |
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#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */ |
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#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */ |
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#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) |
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/* SYS-CPU vs. RT-CPU */ |
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#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */ |
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#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */ |
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#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */ |
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#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */ |
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#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */ |
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#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */ |
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#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */ |
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#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */ |
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#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */ |
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#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) |
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/* IRQn Configuration Register */ |
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struct irqc_irq { |
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int hw_irq; |
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int requested_irq; |
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struct irqc_priv *p; |
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}; |
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struct irqc_priv { |
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void __iomem *iomem; |
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void __iomem *cpu_int_base; |
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struct irqc_irq irq[IRQC_IRQ_MAX]; |
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unsigned int number_of_irqs; |
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struct device *dev; |
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struct irq_chip_generic *gc; |
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struct irq_domain *irq_domain; |
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atomic_t wakeup_path; |
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}; |
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static struct irqc_priv *irq_data_to_priv(struct irq_data *data) |
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{ |
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return data->domain->host_data; |
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} |
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static void irqc_dbg(struct irqc_irq *i, char *str) |
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{ |
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dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq); |
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} |
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static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { |
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[IRQ_TYPE_LEVEL_LOW] = 0x01, |
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[IRQ_TYPE_LEVEL_HIGH] = 0x02, |
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[IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */ |
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[IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */ |
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[IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */ |
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}; |
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static int irqc_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct irqc_priv *p = irq_data_to_priv(d); |
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int hw_irq = irqd_to_hwirq(d); |
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unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; |
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u32 tmp; |
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irqc_dbg(&p->irq[hw_irq], "sense"); |
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if (!value) |
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return -EINVAL; |
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tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); |
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tmp &= ~0x3f; |
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tmp |= value; |
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iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); |
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return 0; |
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} |
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static int irqc_irq_set_wake(struct irq_data *d, unsigned int on) |
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{ |
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struct irqc_priv *p = irq_data_to_priv(d); |
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int hw_irq = irqd_to_hwirq(d); |
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irq_set_irq_wake(p->irq[hw_irq].requested_irq, on); |
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if (on) |
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atomic_inc(&p->wakeup_path); |
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else |
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atomic_dec(&p->wakeup_path); |
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return 0; |
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} |
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static irqreturn_t irqc_irq_handler(int irq, void *dev_id) |
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{ |
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struct irqc_irq *i = dev_id; |
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struct irqc_priv *p = i->p; |
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u32 bit = BIT(i->hw_irq); |
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irqc_dbg(i, "demux1"); |
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if (ioread32(p->iomem + DETECT_STATUS) & bit) { |
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iowrite32(bit, p->iomem + DETECT_STATUS); |
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irqc_dbg(i, "demux2"); |
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generic_handle_domain_irq(p->irq_domain, i->hw_irq); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static int irqc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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const char *name = dev_name(dev); |
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struct irqc_priv *p; |
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int ret; |
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int k; |
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
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if (!p) |
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return -ENOMEM; |
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p->dev = dev; |
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platform_set_drvdata(pdev, p); |
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pm_runtime_enable(dev); |
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pm_runtime_get_sync(dev); |
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/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ |
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for (k = 0; k < IRQC_IRQ_MAX; k++) { |
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ret = platform_get_irq_optional(pdev, k); |
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if (ret == -ENXIO) |
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break; |
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if (ret < 0) |
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goto err_runtime_pm_disable; |
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p->irq[k].p = p; |
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p->irq[k].hw_irq = k; |
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p->irq[k].requested_irq = ret; |
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} |
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p->number_of_irqs = k; |
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if (p->number_of_irqs < 1) { |
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dev_err(dev, "not enough IRQ resources\n"); |
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ret = -EINVAL; |
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goto err_runtime_pm_disable; |
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} |
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/* ioremap IOMEM and setup read/write callbacks */ |
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p->iomem = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(p->iomem)) { |
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ret = PTR_ERR(p->iomem); |
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goto err_runtime_pm_disable; |
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} |
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p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ |
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p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs, |
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&irq_generic_chip_ops, p); |
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if (!p->irq_domain) { |
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ret = -ENXIO; |
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dev_err(dev, "cannot initialize irq domain\n"); |
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goto err_runtime_pm_disable; |
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} |
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ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs, |
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1, "irqc", handle_level_irq, |
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0, 0, IRQ_GC_INIT_NESTED_LOCK); |
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if (ret) { |
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dev_err(dev, "cannot allocate generic chip\n"); |
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goto err_remove_domain; |
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} |
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p->gc = irq_get_domain_generic_chip(p->irq_domain, 0); |
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p->gc->reg_base = p->cpu_int_base; |
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p->gc->chip_types[0].regs.enable = IRQC_EN_SET; |
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p->gc->chip_types[0].regs.disable = IRQC_EN_STS; |
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p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; |
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p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; |
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p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type; |
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p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake; |
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p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; |
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irq_domain_set_pm_device(p->irq_domain, dev); |
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/* request interrupts one by one */ |
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for (k = 0; k < p->number_of_irqs; k++) { |
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if (devm_request_irq(dev, p->irq[k].requested_irq, |
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irqc_irq_handler, 0, name, &p->irq[k])) { |
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dev_err(dev, "failed to request IRQ\n"); |
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ret = -ENOENT; |
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goto err_remove_domain; |
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} |
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} |
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dev_info(dev, "driving %d irqs\n", p->number_of_irqs); |
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return 0; |
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err_remove_domain: |
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irq_domain_remove(p->irq_domain); |
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err_runtime_pm_disable: |
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pm_runtime_put(dev); |
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pm_runtime_disable(dev); |
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return ret; |
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} |
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static int irqc_remove(struct platform_device *pdev) |
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{ |
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struct irqc_priv *p = platform_get_drvdata(pdev); |
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irq_domain_remove(p->irq_domain); |
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pm_runtime_put(&pdev->dev); |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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static int __maybe_unused irqc_suspend(struct device *dev) |
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{ |
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struct irqc_priv *p = dev_get_drvdata(dev); |
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if (atomic_read(&p->wakeup_path)) |
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device_set_wakeup_path(dev); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL); |
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static const struct of_device_id irqc_dt_ids[] = { |
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{ .compatible = "renesas,irqc", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, irqc_dt_ids); |
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static struct platform_driver irqc_device_driver = { |
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.probe = irqc_probe, |
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.remove = irqc_remove, |
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.driver = { |
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.name = "renesas_irqc", |
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.of_match_table = irqc_dt_ids, |
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.pm = &irqc_pm_ops, |
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} |
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}; |
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static int __init irqc_init(void) |
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{ |
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return platform_driver_register(&irqc_device_driver); |
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} |
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postcore_initcall(irqc_init); |
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static void __exit irqc_exit(void) |
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{ |
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platform_driver_unregister(&irqc_device_driver); |
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} |
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module_exit(irqc_exit); |
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MODULE_AUTHOR("Magnus Damm"); |
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MODULE_DESCRIPTION("Renesas IRQC Driver"); |
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MODULE_LICENSE("GPL v2");
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