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1474 lines
36 KiB
1474 lines
36 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2021 Analog Devices, Inc. |
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* Author: Cosmin Tanislav <[email protected]> |
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*/ |
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|
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#include <asm/unaligned.h> |
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#include <linux/bitfield.h> |
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#include <linux/crc8.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/sysfs.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/interrupt.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/property.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/spi/spi.h> |
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#include <dt-bindings/iio/addac/adi,ad74413r.h> |
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|
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#define AD74413R_CRC_POLYNOMIAL 0x7 |
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DECLARE_CRC8_TABLE(ad74413r_crc8_table); |
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#define AD74413R_CHANNEL_MAX 4 |
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#define AD74413R_FRAME_SIZE 4 |
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struct ad74413r_chip_info { |
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const char *name; |
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bool hart_support; |
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}; |
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struct ad74413r_channel_config { |
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u32 func; |
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bool gpo_comparator; |
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bool initialized; |
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}; |
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struct ad74413r_channels { |
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struct iio_chan_spec *channels; |
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unsigned int num_channels; |
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}; |
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struct ad74413r_state { |
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struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX]; |
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unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX]; |
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unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX]; |
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struct gpio_chip gpo_gpiochip; |
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struct gpio_chip comp_gpiochip; |
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struct completion adc_data_completion; |
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unsigned int num_gpo_gpios; |
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unsigned int num_comparator_gpios; |
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u32 sense_resistor_ohms; |
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|
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/* |
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* Synchronize consecutive operations when doing a one-shot |
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* conversion and when updating the ADC samples SPI message. |
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*/ |
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struct mutex lock; |
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const struct ad74413r_chip_info *chip_info; |
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struct spi_device *spi; |
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struct regulator *refin_reg; |
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struct regmap *regmap; |
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struct device *dev; |
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struct iio_trigger *trig; |
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size_t adc_active_channels; |
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struct spi_message adc_samples_msg; |
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struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; |
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|
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/* |
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* DMA (thus cache coherency maintenance) may require the |
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* transfer buffers to live in their own cache lines. |
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*/ |
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struct { |
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u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; |
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s64 timestamp; |
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} adc_samples_buf __aligned(IIO_DMA_MINALIGN); |
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u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; |
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u8 reg_tx_buf[AD74413R_FRAME_SIZE]; |
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u8 reg_rx_buf[AD74413R_FRAME_SIZE]; |
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}; |
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#define AD74413R_REG_NOP 0x00 |
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#define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x)) |
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#define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0) |
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#define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x)) |
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#define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5) |
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#define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3) |
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#define AD74413R_ADC_RANGE_10V 0b000 |
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#define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001 |
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#define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010 |
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#define AD74413R_ADC_RANGE_5V_BI_DIR 0b011 |
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#define AD74413R_ADC_REJECTION_50_60 0b00 |
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#define AD74413R_ADC_REJECTION_NONE 0b01 |
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#define AD74413R_ADC_REJECTION_50_60_HART 0b10 |
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#define AD74413R_ADC_REJECTION_HART 0b11 |
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#define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x)) |
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#define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0) |
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#define AD74413R_DIN_DEBOUNCE_LEN BIT(5) |
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|
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#define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x)) |
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#define AD74413R_DAC_CODE_MAX GENMASK(12, 0) |
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#define AD74413R_DAC_VOLTAGE_MAX 11000 |
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#define AD74413R_REG_GPO_PAR_DATA 0x0d |
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#define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x)) |
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#define AD74413R_GPO_CONFIG_DATA_MASK BIT(3) |
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#define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0) |
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#define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000 |
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#define AD74413R_GPO_CONFIG_LOGIC 0b001 |
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#define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010 |
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#define AD74413R_GPO_CONFIG_COMPARATOR 0b011 |
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#define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100 |
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|
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#define AD74413R_REG_ADC_CONV_CTRL 0x23 |
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#define AD74413R_CONV_SEQ_MASK GENMASK(9, 8) |
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#define AD74413R_CONV_SEQ_ON 0b00 |
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#define AD74413R_CONV_SEQ_SINGLE 0b01 |
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#define AD74413R_CONV_SEQ_CONTINUOUS 0b10 |
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#define AD74413R_CONV_SEQ_OFF 0b11 |
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#define AD74413R_CH_EN_MASK(x) BIT(x) |
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|
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#define AD74413R_REG_DIN_COMP_OUT 0x25 |
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#define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x)) |
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#define AD74413R_ADC_RESULT_MAX GENMASK(15, 0) |
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#define AD74413R_REG_READ_SELECT 0x41 |
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#define AD74413R_REG_CMD_KEY 0x44 |
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#define AD74413R_CMD_KEY_LDAC 0x953a |
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#define AD74413R_CMD_KEY_RESET1 0x15fa |
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#define AD74413R_CMD_KEY_RESET2 0xaf51 |
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static const int ad74413r_adc_sampling_rates[] = { |
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20, 4800, |
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}; |
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static const int ad74413r_adc_sampling_rates_hart[] = { |
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10, 20, 1200, 4800, |
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}; |
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static int ad74413r_crc(u8 *buf) |
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{ |
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return crc8(ad74413r_crc8_table, buf, 3, 0); |
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} |
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static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf) |
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{ |
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buf[0] = reg; |
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put_unaligned_be16(val, &buf[1]); |
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buf[3] = ad74413r_crc(buf); |
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} |
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static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val) |
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{ |
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struct ad74413r_state *st = context; |
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ad74413r_format_reg_write(reg, val, st->reg_tx_buf); |
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return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); |
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} |
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static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf) |
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{ |
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u8 expected_crc = ad74413r_crc(buf); |
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if (buf[3] != expected_crc) { |
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dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", |
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buf[3], buf[0], buf[1], buf[2]); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val) |
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{ |
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struct ad74413r_state *st = context; |
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struct spi_transfer reg_read_xfer[] = { |
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{ |
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.tx_buf = st->reg_tx_buf, |
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.len = AD74413R_FRAME_SIZE, |
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.cs_change = 1, |
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}, |
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{ |
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.rx_buf = st->reg_rx_buf, |
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.len = AD74413R_FRAME_SIZE, |
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}, |
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}; |
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int ret; |
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ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg, |
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st->reg_tx_buf); |
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ret = spi_sync_transfer(st->spi, reg_read_xfer, |
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ARRAY_SIZE(reg_read_xfer)); |
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if (ret) |
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return ret; |
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ret = ad74413r_crc_check(st, st->reg_rx_buf); |
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if (ret) |
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return ret; |
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*val = get_unaligned_be16(&st->reg_rx_buf[1]); |
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return 0; |
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} |
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static const struct regmap_config ad74413r_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 16, |
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.reg_read = ad74413r_reg_read, |
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.reg_write = ad74413r_reg_write, |
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}; |
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static int ad74413r_set_gpo_config(struct ad74413r_state *st, |
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unsigned int offset, u8 mode) |
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{ |
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return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset), |
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AD74413R_GPO_CONFIG_SELECT_MASK, mode); |
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} |
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static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = { |
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0, 13, 18, 24, 32, 42, 56, 75, |
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100, 130, 180, 240, 320, 420, 560, 750, |
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1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500, |
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10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000, |
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}; |
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static int ad74413r_set_comp_debounce(struct ad74413r_state *st, |
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unsigned int offset, |
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unsigned int debounce) |
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{ |
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unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1; |
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unsigned int i; |
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for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++) |
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if (debounce <= ad74413r_debounce_map[i]) { |
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val = i; |
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break; |
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} |
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return regmap_update_bits(st->regmap, |
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AD74413R_REG_DIN_CONFIG_X(offset), |
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AD74413R_DIN_DEBOUNCE_MASK, |
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val); |
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} |
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static void ad74413r_gpio_set(struct gpio_chip *chip, |
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unsigned int offset, int val) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned int real_offset = st->gpo_gpio_offsets[offset]; |
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int ret; |
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ret = ad74413r_set_gpo_config(st, real_offset, |
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AD74413R_GPO_CONFIG_LOGIC); |
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if (ret) |
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return; |
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regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset), |
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AD74413R_GPO_CONFIG_DATA_MASK, |
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val ? AD74413R_GPO_CONFIG_DATA_MASK : 0); |
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} |
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static void ad74413r_gpio_set_multiple(struct gpio_chip *chip, |
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unsigned long *mask, |
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unsigned long *bits) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned long real_mask = 0; |
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unsigned long real_bits = 0; |
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unsigned int offset; |
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int ret; |
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for_each_set_bit(offset, mask, chip->ngpio) { |
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unsigned int real_offset = st->gpo_gpio_offsets[offset]; |
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ret = ad74413r_set_gpo_config(st, real_offset, |
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AD74413R_GPO_CONFIG_LOGIC_PARALLEL); |
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if (ret) |
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return; |
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real_mask |= BIT(real_offset); |
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if (*bits & offset) |
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real_bits |= BIT(real_offset); |
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} |
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regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA, |
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real_mask, real_bits); |
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} |
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static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned int real_offset = st->comp_gpio_offsets[offset]; |
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unsigned int status; |
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int ret; |
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ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status); |
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if (ret) |
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return ret; |
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status &= BIT(real_offset); |
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return status ? 1 : 0; |
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} |
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static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, |
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unsigned long *mask, |
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unsigned long *bits) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned int offset; |
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unsigned int val; |
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int ret; |
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ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val); |
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if (ret) |
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return ret; |
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for_each_set_bit(offset, mask, chip->ngpio) { |
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unsigned int real_offset = st->comp_gpio_offsets[offset]; |
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__assign_bit(offset, bits, val & BIT(real_offset)); |
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} |
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return ret; |
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} |
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static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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return GPIO_LINE_DIRECTION_OUT; |
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} |
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static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip, |
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unsigned int offset, |
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unsigned long config) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned int real_offset = st->gpo_gpio_offsets[offset]; |
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switch (pinconf_to_config_param(config)) { |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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return ad74413r_set_gpo_config(st, real_offset, |
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AD74413R_GPO_CONFIG_100K_PULL_DOWN); |
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
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return ad74413r_set_gpo_config(st, real_offset, |
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AD74413R_GPO_CONFIG_HIGH_IMPEDANCE); |
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default: |
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return -ENOTSUPP; |
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} |
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} |
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static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip, |
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unsigned int offset, |
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unsigned long config) |
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{ |
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struct ad74413r_state *st = gpiochip_get_data(chip); |
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unsigned int real_offset = st->comp_gpio_offsets[offset]; |
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|
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switch (pinconf_to_config_param(config)) { |
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case PIN_CONFIG_INPUT_DEBOUNCE: |
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return ad74413r_set_comp_debounce(st, real_offset, |
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pinconf_to_config_argument(config)); |
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default: |
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return -ENOTSUPP; |
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} |
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} |
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static int ad74413r_reset(struct ad74413r_state *st) |
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{ |
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int ret; |
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ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY, |
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AD74413R_CMD_KEY_RESET1); |
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if (ret) |
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return ret; |
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|
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return regmap_write(st->regmap, AD74413R_REG_CMD_KEY, |
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AD74413R_CMD_KEY_RESET2); |
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} |
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static int ad74413r_set_channel_dac_code(struct ad74413r_state *st, |
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unsigned int channel, int dac_code) |
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{ |
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struct reg_sequence reg_seq[2] = { |
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{ AD74413R_REG_DAC_CODE_X(channel), dac_code }, |
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{ AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC }, |
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}; |
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|
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return regmap_multi_reg_write(st->regmap, reg_seq, 2); |
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} |
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static int ad74413r_set_channel_function(struct ad74413r_state *st, |
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unsigned int channel, u8 func) |
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{ |
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return regmap_update_bits(st->regmap, |
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AD74413R_REG_CH_FUNC_SETUP_X(channel), |
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AD74413R_CH_FUNC_SETUP_MASK, func); |
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} |
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static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st, |
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unsigned int status) |
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{ |
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int ret; |
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|
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/* |
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* These bits do not clear when a conversion completes. |
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* To enable a subsequent conversion, repeat the write. |
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*/ |
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ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, |
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AD74413R_CONV_SEQ_MASK, |
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FIELD_PREP(AD74413R_CONV_SEQ_MASK, status)); |
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if (ret) |
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return ret; |
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|
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/* |
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* Wait 100us before starting conversions. |
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*/ |
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usleep_range(100, 120); |
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|
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return 0; |
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} |
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|
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static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st, |
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unsigned int channel, |
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bool status) |
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{ |
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return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, |
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AD74413R_CH_EN_MASK(channel), |
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status ? AD74413R_CH_EN_MASK(channel) : 0); |
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} |
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|
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static int ad74413r_get_adc_range(struct ad74413r_state *st, |
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unsigned int channel, |
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unsigned int *val) |
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{ |
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int ret; |
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|
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ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); |
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if (ret) |
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return ret; |
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|
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*val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val); |
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|
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return 0; |
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} |
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|
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static int ad74413r_get_adc_rejection(struct ad74413r_state *st, |
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unsigned int channel, |
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unsigned int *val) |
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{ |
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int ret; |
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|
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ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); |
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if (ret) |
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return ret; |
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|
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*val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val); |
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|
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return 0; |
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} |
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|
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static int ad74413r_set_adc_rejection(struct ad74413r_state *st, |
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unsigned int channel, |
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unsigned int val) |
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{ |
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return regmap_update_bits(st->regmap, |
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AD74413R_REG_ADC_CONFIG_X(channel), |
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AD74413R_ADC_CONFIG_REJECTION_MASK, |
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FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK, |
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val)); |
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} |
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|
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static int ad74413r_rejection_to_rate(struct ad74413r_state *st, |
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unsigned int rej, int *val) |
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{ |
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switch (rej) { |
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case AD74413R_ADC_REJECTION_50_60: |
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*val = 20; |
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return 0; |
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case AD74413R_ADC_REJECTION_NONE: |
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*val = 4800; |
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return 0; |
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case AD74413R_ADC_REJECTION_50_60_HART: |
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*val = 10; |
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return 0; |
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case AD74413R_ADC_REJECTION_HART: |
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*val = 1200; |
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return 0; |
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default: |
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dev_err(st->dev, "ADC rejection invalid\n"); |
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return -EINVAL; |
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} |
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} |
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|
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static int ad74413r_rate_to_rejection(struct ad74413r_state *st, |
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int rate, unsigned int *val) |
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{ |
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switch (rate) { |
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case 20: |
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*val = AD74413R_ADC_REJECTION_50_60; |
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return 0; |
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case 4800: |
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*val = AD74413R_ADC_REJECTION_NONE; |
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return 0; |
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case 10: |
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*val = AD74413R_ADC_REJECTION_50_60_HART; |
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return 0; |
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case 1200: |
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*val = AD74413R_ADC_REJECTION_HART; |
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return 0; |
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default: |
|
dev_err(st->dev, "ADC rate invalid\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_range_to_voltage_range(struct ad74413r_state *st, |
|
unsigned int range, int *val) |
|
{ |
|
switch (range) { |
|
case AD74413R_ADC_RANGE_10V: |
|
*val = 10000; |
|
return 0; |
|
case AD74413R_ADC_RANGE_2P5V_EXT_POW: |
|
case AD74413R_ADC_RANGE_2P5V_INT_POW: |
|
*val = 2500; |
|
return 0; |
|
case AD74413R_ADC_RANGE_5V_BI_DIR: |
|
*val = 5000; |
|
return 0; |
|
default: |
|
dev_err(st->dev, "ADC range invalid\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st, |
|
unsigned int range, int *val) |
|
{ |
|
switch (range) { |
|
case AD74413R_ADC_RANGE_10V: |
|
case AD74413R_ADC_RANGE_2P5V_EXT_POW: |
|
*val = 0; |
|
return 0; |
|
case AD74413R_ADC_RANGE_2P5V_INT_POW: |
|
case AD74413R_ADC_RANGE_5V_BI_DIR: |
|
*val = -2500; |
|
return 0; |
|
default: |
|
dev_err(st->dev, "ADC range invalid\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st, |
|
unsigned int range, int *val) |
|
{ |
|
switch (range) { |
|
case AD74413R_ADC_RANGE_10V: |
|
case AD74413R_ADC_RANGE_2P5V_EXT_POW: |
|
*val = 0; |
|
return 0; |
|
case AD74413R_ADC_RANGE_2P5V_INT_POW: |
|
*val = -((int)AD74413R_ADC_RESULT_MAX); |
|
return 0; |
|
case AD74413R_ADC_RANGE_5V_BI_DIR: |
|
*val = -((int)AD74413R_ADC_RESULT_MAX / 2); |
|
return 0; |
|
default: |
|
dev_err(st->dev, "ADC range invalid\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st, |
|
int *val, int *val2) |
|
{ |
|
*val = AD74413R_DAC_VOLTAGE_MAX; |
|
*val2 = AD74413R_DAC_CODE_MAX; |
|
|
|
return IIO_VAL_FRACTIONAL; |
|
} |
|
|
|
static int ad74413r_get_output_current_scale(struct ad74413r_state *st, |
|
int *val, int *val2) |
|
{ |
|
*val = regulator_get_voltage(st->refin_reg); |
|
*val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000; |
|
|
|
return IIO_VAL_FRACTIONAL; |
|
} |
|
|
|
static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st, |
|
unsigned int channel, |
|
int *val, int *val2) |
|
{ |
|
unsigned int range; |
|
int ret; |
|
|
|
ret = ad74413r_get_adc_range(st, channel, &range); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_range_to_voltage_range(st, range, val); |
|
if (ret) |
|
return ret; |
|
|
|
*val2 = AD74413R_ADC_RESULT_MAX; |
|
|
|
return IIO_VAL_FRACTIONAL; |
|
} |
|
|
|
static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st, |
|
unsigned int channel, int *val) |
|
{ |
|
unsigned int range; |
|
int ret; |
|
|
|
ret = ad74413r_get_adc_range(st, channel, &range); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_range_to_voltage_offset_raw(st, range, val); |
|
if (ret) |
|
return ret; |
|
|
|
return IIO_VAL_INT; |
|
} |
|
|
|
static int ad74413r_get_input_current_scale(struct ad74413r_state *st, |
|
unsigned int channel, int *val, |
|
int *val2) |
|
{ |
|
unsigned int range; |
|
int ret; |
|
|
|
ret = ad74413r_get_adc_range(st, channel, &range); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_range_to_voltage_range(st, range, val); |
|
if (ret) |
|
return ret; |
|
|
|
*val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms; |
|
|
|
return IIO_VAL_FRACTIONAL; |
|
} |
|
|
|
static int ad74413_get_input_current_offset(struct ad74413r_state *st, |
|
unsigned int channel, int *val) |
|
{ |
|
unsigned int range; |
|
int voltage_range; |
|
int voltage_offset; |
|
int ret; |
|
|
|
ret = ad74413r_get_adc_range(st, channel, &range); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_range_to_voltage_range(st, range, &voltage_range); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset); |
|
if (ret) |
|
return ret; |
|
|
|
*val = voltage_offset * AD74413R_ADC_RESULT_MAX / voltage_range; |
|
|
|
return IIO_VAL_INT; |
|
} |
|
|
|
static int ad74413r_get_adc_rate(struct ad74413r_state *st, |
|
unsigned int channel, int *val) |
|
{ |
|
unsigned int rejection; |
|
int ret; |
|
|
|
ret = ad74413r_get_adc_rejection(st, channel, &rejection); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_rejection_to_rate(st, rejection, val); |
|
if (ret) |
|
return ret; |
|
|
|
return IIO_VAL_INT; |
|
} |
|
|
|
static int ad74413r_set_adc_rate(struct ad74413r_state *st, |
|
unsigned int channel, int val) |
|
{ |
|
unsigned int rejection; |
|
int ret; |
|
|
|
ret = ad74413r_rate_to_rejection(st, val, &rejection); |
|
if (ret) |
|
return ret; |
|
|
|
return ad74413r_set_adc_rejection(st, channel, rejection); |
|
} |
|
|
|
static irqreturn_t ad74413r_trigger_handler(int irq, void *p) |
|
{ |
|
struct iio_poll_func *pf = p; |
|
struct iio_dev *indio_dev = pf->indio_dev; |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
u8 *rx_buf = st->adc_samples_buf.rx_buf; |
|
unsigned int i; |
|
int ret; |
|
|
|
ret = spi_sync(st->spi, &st->adc_samples_msg); |
|
if (ret) |
|
goto out; |
|
|
|
for (i = 0; i < st->adc_active_channels; i++) |
|
ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]); |
|
|
|
iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf, |
|
iio_get_time_ns(indio_dev)); |
|
|
|
out: |
|
iio_trigger_notify_done(indio_dev->trig); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data) |
|
{ |
|
struct iio_dev *indio_dev = data; |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
if (iio_buffer_enabled(indio_dev)) |
|
iio_trigger_poll(st->trig); |
|
else |
|
complete(&st->adc_data_completion); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int _ad74413r_get_single_adc_result(struct ad74413r_state *st, |
|
unsigned int channel, int *val) |
|
{ |
|
unsigned int uval; |
|
int ret; |
|
|
|
reinit_completion(&st->adc_data_completion); |
|
|
|
ret = ad74413r_set_adc_channel_enable(st, channel, true); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE); |
|
if (ret) |
|
return ret; |
|
|
|
ret = wait_for_completion_timeout(&st->adc_data_completion, |
|
msecs_to_jiffies(1000)); |
|
if (!ret) { |
|
ret = -ETIMEDOUT; |
|
return ret; |
|
} |
|
|
|
ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel), |
|
&uval); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); |
|
if (ret) |
|
return ret; |
|
|
|
ret = ad74413r_set_adc_channel_enable(st, channel, false); |
|
if (ret) |
|
return ret; |
|
|
|
*val = uval; |
|
|
|
return IIO_VAL_INT; |
|
} |
|
|
|
static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev, |
|
unsigned int channel, int *val) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
int ret; |
|
|
|
ret = iio_device_claim_direct_mode(indio_dev); |
|
if (ret) |
|
return ret; |
|
|
|
mutex_lock(&st->lock); |
|
ret = _ad74413r_get_single_adc_result(st, channel, val); |
|
mutex_unlock(&st->lock); |
|
|
|
iio_device_release_direct_mode(indio_dev); |
|
|
|
return ret; |
|
} |
|
|
|
static void ad74413r_adc_to_resistance_result(int adc_result, int *val) |
|
{ |
|
if (adc_result == AD74413R_ADC_RESULT_MAX) |
|
adc_result = AD74413R_ADC_RESULT_MAX - 1; |
|
|
|
*val = DIV_ROUND_CLOSEST(adc_result * 2100, |
|
AD74413R_ADC_RESULT_MAX - adc_result); |
|
} |
|
|
|
static int ad74413r_update_scan_mode(struct iio_dev *indio_dev, |
|
const unsigned long *active_scan_mask) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
struct spi_transfer *xfer = st->adc_samples_xfer; |
|
u8 *rx_buf = st->adc_samples_buf.rx_buf; |
|
u8 *tx_buf = st->adc_samples_tx_buf; |
|
unsigned int channel; |
|
int ret = -EINVAL; |
|
|
|
mutex_lock(&st->lock); |
|
|
|
spi_message_init(&st->adc_samples_msg); |
|
st->adc_active_channels = 0; |
|
|
|
for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { |
|
ret = ad74413r_set_adc_channel_enable(st, channel, false); |
|
if (ret) |
|
goto out; |
|
} |
|
|
|
if (*active_scan_mask == 0) |
|
goto out; |
|
|
|
/* |
|
* The read select register is used to select which register's value |
|
* will be sent by the slave on the next SPI frame. |
|
* |
|
* Create an SPI message that, on each step, writes to the read select |
|
* register to select the ADC result of the next enabled channel, and |
|
* reads the ADC result of the previous enabled channel. |
|
* |
|
* Example: |
|
* W: [WCH1] [WCH2] [WCH2] [WCH3] [ ] |
|
* R: [ ] [RCH1] [RCH2] [RCH3] [RCH4] |
|
*/ |
|
|
|
for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { |
|
ret = ad74413r_set_adc_channel_enable(st, channel, true); |
|
if (ret) |
|
goto out; |
|
|
|
st->adc_active_channels++; |
|
|
|
if (xfer == st->adc_samples_xfer) |
|
xfer->rx_buf = NULL; |
|
else |
|
xfer->rx_buf = rx_buf; |
|
|
|
xfer->tx_buf = tx_buf; |
|
xfer->len = AD74413R_FRAME_SIZE; |
|
xfer->cs_change = 1; |
|
|
|
ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, |
|
AD74413R_REG_ADC_RESULT_X(channel), |
|
tx_buf); |
|
|
|
spi_message_add_tail(xfer, &st->adc_samples_msg); |
|
|
|
tx_buf += AD74413R_FRAME_SIZE; |
|
if (xfer != st->adc_samples_xfer) |
|
rx_buf += AD74413R_FRAME_SIZE; |
|
xfer++; |
|
} |
|
|
|
xfer->rx_buf = rx_buf; |
|
xfer->tx_buf = NULL; |
|
xfer->len = AD74413R_FRAME_SIZE; |
|
xfer->cs_change = 0; |
|
|
|
spi_message_add_tail(xfer, &st->adc_samples_msg); |
|
|
|
out: |
|
mutex_unlock(&st->lock); |
|
|
|
return ret; |
|
} |
|
|
|
static int ad74413r_buffer_postenable(struct iio_dev *indio_dev) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS); |
|
} |
|
|
|
static int ad74413r_buffer_predisable(struct iio_dev *indio_dev) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); |
|
} |
|
|
|
static int ad74413r_read_raw(struct iio_dev *indio_dev, |
|
struct iio_chan_spec const *chan, |
|
int *val, int *val2, long info) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
switch (info) { |
|
case IIO_CHAN_INFO_SCALE: |
|
switch (chan->type) { |
|
case IIO_VOLTAGE: |
|
if (chan->output) |
|
return ad74413r_get_output_voltage_scale(st, |
|
val, val2); |
|
else |
|
return ad74413r_get_input_voltage_scale(st, |
|
chan->channel, val, val2); |
|
case IIO_CURRENT: |
|
if (chan->output) |
|
return ad74413r_get_output_current_scale(st, |
|
val, val2); |
|
else |
|
return ad74413r_get_input_current_scale(st, |
|
chan->channel, val, val2); |
|
default: |
|
return -EINVAL; |
|
} |
|
case IIO_CHAN_INFO_OFFSET: |
|
switch (chan->type) { |
|
case IIO_VOLTAGE: |
|
return ad74413r_get_input_voltage_offset(st, |
|
chan->channel, val); |
|
case IIO_CURRENT: |
|
return ad74413_get_input_current_offset(st, |
|
chan->channel, val); |
|
default: |
|
return -EINVAL; |
|
} |
|
case IIO_CHAN_INFO_RAW: |
|
if (chan->output) |
|
return -EINVAL; |
|
|
|
return ad74413r_get_single_adc_result(indio_dev, chan->channel, |
|
val); |
|
case IIO_CHAN_INFO_PROCESSED: { |
|
int ret; |
|
|
|
ret = ad74413r_get_single_adc_result(indio_dev, chan->channel, |
|
val); |
|
if (ret) |
|
return ret; |
|
|
|
ad74413r_adc_to_resistance_result(*val, val); |
|
|
|
return ret; |
|
} |
|
case IIO_CHAN_INFO_SAMP_FREQ: |
|
return ad74413r_get_adc_rate(st, chan->channel, val); |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_write_raw(struct iio_dev *indio_dev, |
|
struct iio_chan_spec const *chan, |
|
int val, int val2, long info) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
switch (info) { |
|
case IIO_CHAN_INFO_RAW: |
|
if (!chan->output) |
|
return -EINVAL; |
|
|
|
if (val < 0 || val > AD74413R_DAC_CODE_MAX) { |
|
dev_err(st->dev, "Invalid DAC code\n"); |
|
return -EINVAL; |
|
} |
|
|
|
return ad74413r_set_channel_dac_code(st, chan->channel, val); |
|
case IIO_CHAN_INFO_SAMP_FREQ: |
|
return ad74413r_set_adc_rate(st, chan->channel, val); |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ad74413r_read_avail(struct iio_dev *indio_dev, |
|
struct iio_chan_spec const *chan, |
|
const int **vals, int *type, int *length, |
|
long info) |
|
{ |
|
struct ad74413r_state *st = iio_priv(indio_dev); |
|
|
|
switch (info) { |
|
case IIO_CHAN_INFO_SAMP_FREQ: |
|
if (st->chip_info->hart_support) { |
|
*vals = ad74413r_adc_sampling_rates_hart; |
|
*length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart); |
|
} else { |
|
*vals = ad74413r_adc_sampling_rates; |
|
*length = ARRAY_SIZE(ad74413r_adc_sampling_rates); |
|
} |
|
*type = IIO_VAL_INT; |
|
return IIO_AVAIL_LIST; |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static const struct iio_buffer_setup_ops ad74413r_buffer_ops = { |
|
.postenable = &ad74413r_buffer_postenable, |
|
.predisable = &ad74413r_buffer_predisable, |
|
}; |
|
|
|
static const struct iio_trigger_ops ad74413r_trigger_ops = { |
|
.validate_device = iio_trigger_validate_own_device, |
|
}; |
|
|
|
static const struct iio_info ad74413r_info = { |
|
.read_raw = &ad74413r_read_raw, |
|
.write_raw = &ad74413r_write_raw, |
|
.read_avail = &ad74413r_read_avail, |
|
.update_scan_mode = &ad74413r_update_scan_mode, |
|
}; |
|
|
|
#define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \ |
|
{ \ |
|
.type = (_type), \ |
|
.indexed = 1, \ |
|
.output = 1, \ |
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ |
|
| (extra_mask_separate), \ |
|
} |
|
|
|
#define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \ |
|
{ \ |
|
.type = (_type), \ |
|
.indexed = 1, \ |
|
.output = 0, \ |
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ |
|
| BIT(IIO_CHAN_INFO_SAMP_FREQ) \ |
|
| (extra_mask_separate), \ |
|
.info_mask_separate_available = \ |
|
BIT(IIO_CHAN_INFO_SAMP_FREQ), \ |
|
.scan_type = { \ |
|
.sign = 'u', \ |
|
.realbits = 16, \ |
|
.storagebits = 32, \ |
|
.shift = 8, \ |
|
.endianness = IIO_BE, \ |
|
}, \ |
|
} |
|
|
|
#define AD74413R_ADC_VOLTAGE_CHANNEL \ |
|
AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \ |
|
| BIT(IIO_CHAN_INFO_OFFSET)) |
|
|
|
#define AD74413R_ADC_CURRENT_CHANNEL \ |
|
AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \ |
|
| BIT(IIO_CHAN_INFO_OFFSET)) |
|
|
|
static struct iio_chan_spec ad74413r_voltage_output_channels[] = { |
|
AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)), |
|
AD74413R_ADC_CURRENT_CHANNEL, |
|
}; |
|
|
|
static struct iio_chan_spec ad74413r_current_output_channels[] = { |
|
AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)), |
|
AD74413R_ADC_VOLTAGE_CHANNEL, |
|
}; |
|
|
|
static struct iio_chan_spec ad74413r_voltage_input_channels[] = { |
|
AD74413R_ADC_VOLTAGE_CHANNEL, |
|
}; |
|
|
|
static struct iio_chan_spec ad74413r_current_input_channels[] = { |
|
AD74413R_ADC_CURRENT_CHANNEL, |
|
}; |
|
|
|
static struct iio_chan_spec ad74413r_resistance_input_channels[] = { |
|
AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)), |
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}; |
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|
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static struct iio_chan_spec ad74413r_digital_input_channels[] = { |
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AD74413R_ADC_VOLTAGE_CHANNEL, |
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}; |
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|
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#define _AD74413R_CHANNELS(_channels) \ |
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{ \ |
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.channels = _channels, \ |
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.num_channels = ARRAY_SIZE(_channels), \ |
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} |
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|
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#define AD74413R_CHANNELS(name) \ |
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_AD74413R_CHANNELS(ad74413r_ ## name ## _channels) |
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|
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static const struct ad74413r_channels ad74413r_channels_map[] = { |
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[CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input), |
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[CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output), |
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[CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output), |
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[CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input), |
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[CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input), |
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[CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input), |
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[CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input), |
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[CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input), |
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[CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input), |
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[CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input), |
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[CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input), |
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}; |
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|
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static int ad74413r_parse_channel_config(struct iio_dev *indio_dev, |
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struct fwnode_handle *channel_node) |
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{ |
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struct ad74413r_state *st = iio_priv(indio_dev); |
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struct ad74413r_channel_config *config; |
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u32 index; |
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int ret; |
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|
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ret = fwnode_property_read_u32(channel_node, "reg", &index); |
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if (ret) { |
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dev_err(st->dev, "Failed to read channel reg: %d\n", ret); |
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return ret; |
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} |
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|
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if (index >= AD74413R_CHANNEL_MAX) { |
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dev_err(st->dev, "Channel index %u is too large\n", index); |
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return -EINVAL; |
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} |
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|
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config = &st->channel_configs[index]; |
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if (config->initialized) { |
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dev_err(st->dev, "Channel %u already initialized\n", index); |
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return -EINVAL; |
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} |
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|
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config->func = CH_FUNC_HIGH_IMPEDANCE; |
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fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func); |
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|
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if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) { |
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dev_err(st->dev, "Invalid channel function %u\n", config->func); |
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return -EINVAL; |
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} |
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|
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if (!st->chip_info->hart_support && |
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(config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART || |
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config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) { |
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dev_err(st->dev, "Unsupported HART function %u\n", config->func); |
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return -EINVAL; |
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} |
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|
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if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || |
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config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) |
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st->num_comparator_gpios++; |
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|
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config->gpo_comparator = fwnode_property_read_bool(channel_node, |
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"adi,gpo-comparator"); |
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|
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if (!config->gpo_comparator) |
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st->num_gpo_gpios++; |
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|
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indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels; |
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|
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config->initialized = true; |
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|
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return 0; |
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} |
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|
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static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev) |
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{ |
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struct ad74413r_state *st = iio_priv(indio_dev); |
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struct fwnode_handle *channel_node = NULL; |
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int ret; |
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|
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fwnode_for_each_available_child_node(dev_fwnode(st->dev), channel_node) { |
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ret = ad74413r_parse_channel_config(indio_dev, channel_node); |
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if (ret) |
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goto put_channel_node; |
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} |
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|
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return 0; |
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|
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put_channel_node: |
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fwnode_handle_put(channel_node); |
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|
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return ret; |
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} |
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|
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static int ad74413r_setup_channels(struct iio_dev *indio_dev) |
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{ |
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struct ad74413r_state *st = iio_priv(indio_dev); |
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struct ad74413r_channel_config *config; |
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struct iio_chan_spec *channels, *chans; |
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unsigned int i, num_chans, chan_i; |
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int ret; |
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|
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channels = devm_kcalloc(st->dev, sizeof(*channels), |
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indio_dev->num_channels, GFP_KERNEL); |
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if (!channels) |
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return -ENOMEM; |
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|
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indio_dev->channels = channels; |
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|
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for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { |
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config = &st->channel_configs[i]; |
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chans = ad74413r_channels_map[config->func].channels; |
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num_chans = ad74413r_channels_map[config->func].num_channels; |
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|
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memcpy(channels, chans, num_chans * sizeof(*chans)); |
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|
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for (chan_i = 0; chan_i < num_chans; chan_i++) { |
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struct iio_chan_spec *chan = &channels[chan_i]; |
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|
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chan->channel = i; |
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if (chan->output) |
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chan->scan_index = -1; |
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else |
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chan->scan_index = i; |
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} |
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|
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ret = ad74413r_set_channel_function(st, i, config->func); |
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if (ret) |
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return ret; |
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|
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channels += num_chans; |
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} |
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|
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return 0; |
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} |
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|
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static int ad74413r_setup_gpios(struct ad74413r_state *st) |
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{ |
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struct ad74413r_channel_config *config; |
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unsigned int comp_gpio_i = 0; |
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unsigned int gpo_gpio_i = 0; |
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unsigned int i; |
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u8 gpo_config; |
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int ret; |
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|
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for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { |
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config = &st->channel_configs[i]; |
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|
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if (config->gpo_comparator) { |
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gpo_config = AD74413R_GPO_CONFIG_COMPARATOR; |
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} else { |
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gpo_config = AD74413R_GPO_CONFIG_LOGIC; |
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st->gpo_gpio_offsets[gpo_gpio_i++] = i; |
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} |
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|
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if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || |
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config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) |
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st->comp_gpio_offsets[comp_gpio_i++] = i; |
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|
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ret = ad74413r_set_gpo_config(st, i, gpo_config); |
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if (ret) |
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return ret; |
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} |
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|
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return 0; |
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} |
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|
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static void ad74413r_regulator_disable(void *regulator) |
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{ |
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regulator_disable(regulator); |
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} |
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|
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static int ad74413r_probe(struct spi_device *spi) |
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{ |
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struct ad74413r_state *st; |
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struct iio_dev *indio_dev; |
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int ret; |
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|
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
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if (!indio_dev) |
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return -ENOMEM; |
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|
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st = iio_priv(indio_dev); |
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|
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st->spi = spi; |
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st->dev = &spi->dev; |
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st->chip_info = device_get_match_data(&spi->dev); |
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mutex_init(&st->lock); |
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init_completion(&st->adc_data_completion); |
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|
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st->regmap = devm_regmap_init(st->dev, NULL, st, |
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&ad74413r_regmap_config); |
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if (IS_ERR(st->regmap)) |
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return PTR_ERR(st->regmap); |
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|
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st->refin_reg = devm_regulator_get(st->dev, "refin"); |
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if (IS_ERR(st->refin_reg)) |
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return dev_err_probe(st->dev, PTR_ERR(st->refin_reg), |
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"Failed to get refin regulator\n"); |
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|
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ret = regulator_enable(st->refin_reg); |
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if (ret) |
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return ret; |
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|
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ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable, |
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st->refin_reg); |
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if (ret) |
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return ret; |
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|
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st->sense_resistor_ohms = 100000000; |
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device_property_read_u32(st->dev, "shunt-resistor-micro-ohms", |
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&st->sense_resistor_ohms); |
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st->sense_resistor_ohms /= 1000000; |
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|
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st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d", |
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st->chip_info->name, iio_device_id(indio_dev)); |
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if (!st->trig) |
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return -ENOMEM; |
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|
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st->trig->ops = &ad74413r_trigger_ops; |
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iio_trigger_set_drvdata(st->trig, st); |
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|
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ret = devm_iio_trigger_register(st->dev, st->trig); |
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if (ret) |
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return ret; |
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|
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indio_dev->name = st->chip_info->name; |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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indio_dev->info = &ad74413r_info; |
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indio_dev->trig = iio_trigger_get(st->trig); |
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|
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ret = ad74413r_reset(st); |
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if (ret) |
|
return ret; |
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|
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ret = ad74413r_parse_channel_configs(indio_dev); |
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if (ret) |
|
return ret; |
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|
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ret = ad74413r_setup_channels(indio_dev); |
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if (ret) |
|
return ret; |
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|
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ret = ad74413r_setup_gpios(st); |
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if (ret) |
|
return ret; |
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|
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if (st->num_gpo_gpios) { |
|
st->gpo_gpiochip.owner = THIS_MODULE; |
|
st->gpo_gpiochip.label = st->chip_info->name; |
|
st->gpo_gpiochip.base = -1; |
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st->gpo_gpiochip.ngpio = st->num_gpo_gpios; |
|
st->gpo_gpiochip.parent = st->dev; |
|
st->gpo_gpiochip.can_sleep = true; |
|
st->gpo_gpiochip.set = ad74413r_gpio_set; |
|
st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple; |
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st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config; |
|
st->gpo_gpiochip.get_direction = |
|
ad74413r_gpio_get_gpo_direction; |
|
|
|
ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st); |
|
if (ret) |
|
return ret; |
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} |
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|
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if (st->num_comparator_gpios) { |
|
st->comp_gpiochip.owner = THIS_MODULE; |
|
st->comp_gpiochip.label = st->chip_info->name; |
|
st->comp_gpiochip.base = -1; |
|
st->comp_gpiochip.ngpio = st->num_comparator_gpios; |
|
st->comp_gpiochip.parent = st->dev; |
|
st->comp_gpiochip.can_sleep = true; |
|
st->comp_gpiochip.get = ad74413r_gpio_get; |
|
st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple; |
|
st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config; |
|
st->comp_gpiochip.get_direction = |
|
ad74413r_gpio_get_comp_direction; |
|
|
|
ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt, |
|
0, st->chip_info->name, indio_dev); |
|
if (ret) |
|
return dev_err_probe(st->dev, ret, "Failed to request irq\n"); |
|
|
|
ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev, |
|
&iio_pollfunc_store_time, |
|
&ad74413r_trigger_handler, |
|
&ad74413r_buffer_ops); |
|
if (ret) |
|
return ret; |
|
|
|
return devm_iio_device_register(st->dev, indio_dev); |
|
} |
|
|
|
static int ad74413r_unregister_driver(struct spi_driver *spi) |
|
{ |
|
spi_unregister_driver(spi); |
|
|
|
return 0; |
|
} |
|
|
|
static int __init ad74413r_register_driver(struct spi_driver *spi) |
|
{ |
|
crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL); |
|
|
|
return spi_register_driver(spi); |
|
} |
|
|
|
static const struct ad74413r_chip_info ad74412r_chip_info_data = { |
|
.hart_support = false, |
|
.name = "ad74412r", |
|
}; |
|
|
|
static const struct ad74413r_chip_info ad74413r_chip_info_data = { |
|
.hart_support = true, |
|
.name = "ad74413r", |
|
}; |
|
|
|
static const struct of_device_id ad74413r_dt_id[] = { |
|
{ |
|
.compatible = "adi,ad74412r", |
|
.data = &ad74412r_chip_info_data, |
|
}, |
|
{ |
|
.compatible = "adi,ad74413r", |
|
.data = &ad74413r_chip_info_data, |
|
}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, ad74413r_dt_id); |
|
|
|
static struct spi_driver ad74413r_driver = { |
|
.driver = { |
|
.name = "ad74413r", |
|
.of_match_table = ad74413r_dt_id, |
|
}, |
|
.probe = ad74413r_probe, |
|
}; |
|
|
|
module_driver(ad74413r_driver, |
|
ad74413r_register_driver, |
|
ad74413r_unregister_driver); |
|
|
|
MODULE_AUTHOR("Cosmin Tanislav <[email protected]>"); |
|
MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC"); |
|
MODULE_LICENSE("GPL v2");
|
|
|