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586 lines
14 KiB
586 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// Copyright (c) 2018-2021 Intel Corporation |
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#include <linux/auxiliary_bus.h> |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/hwmon.h> |
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#include <linux/jiffies.h> |
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#include <linux/module.h> |
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#include <linux/peci.h> |
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#include <linux/peci-cpu.h> |
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#include <linux/units.h> |
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#include "common.h" |
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#define CORE_NUMS_MAX 64 |
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#define BASE_CHANNEL_NUMS 5 |
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#define CPUTEMP_CHANNEL_NUMS (BASE_CHANNEL_NUMS + CORE_NUMS_MAX) |
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#define TEMP_TARGET_FAN_TEMP_MASK GENMASK(15, 8) |
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#define TEMP_TARGET_REF_TEMP_MASK GENMASK(23, 16) |
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#define TEMP_TARGET_TJ_OFFSET_MASK GENMASK(29, 24) |
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#define DTS_MARGIN_MASK GENMASK(15, 0) |
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#define PCS_MODULE_TEMP_MASK GENMASK(15, 0) |
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struct resolved_cores_reg { |
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u8 bus; |
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u8 dev; |
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u8 func; |
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u8 offset; |
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}; |
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struct cpu_info { |
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struct resolved_cores_reg *reg; |
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u8 min_peci_revision; |
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s32 (*thermal_margin_to_millidegree)(u16 val); |
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}; |
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struct peci_temp_target { |
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s32 tcontrol; |
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s32 tthrottle; |
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s32 tjmax; |
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struct peci_sensor_state state; |
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}; |
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enum peci_temp_target_type { |
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tcontrol_type, |
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tthrottle_type, |
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tjmax_type, |
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crit_hyst_type, |
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}; |
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struct peci_cputemp { |
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struct peci_device *peci_dev; |
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struct device *dev; |
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const char *name; |
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const struct cpu_info *gen_info; |
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struct { |
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struct peci_temp_target target; |
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struct peci_sensor_data die; |
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struct peci_sensor_data dts; |
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struct peci_sensor_data core[CORE_NUMS_MAX]; |
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} temp; |
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const char **coretemp_label; |
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DECLARE_BITMAP(core_mask, CORE_NUMS_MAX); |
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}; |
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enum cputemp_channels { |
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channel_die, |
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channel_dts, |
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channel_tcontrol, |
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channel_tthrottle, |
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channel_tjmax, |
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channel_core, |
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}; |
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static const char * const cputemp_label[BASE_CHANNEL_NUMS] = { |
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"Die", |
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"DTS", |
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"Tcontrol", |
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"Tthrottle", |
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"Tjmax", |
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}; |
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static int update_temp_target(struct peci_cputemp *priv) |
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{ |
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s32 tthrottle_offset, tcontrol_margin; |
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u32 pcs; |
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int ret; |
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if (!peci_sensor_need_update(&priv->temp.target.state)) |
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return 0; |
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ret = peci_pcs_read(priv->peci_dev, PECI_PCS_TEMP_TARGET, 0, &pcs); |
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if (ret) |
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return ret; |
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priv->temp.target.tjmax = |
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FIELD_GET(TEMP_TARGET_REF_TEMP_MASK, pcs) * MILLIDEGREE_PER_DEGREE; |
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tcontrol_margin = FIELD_GET(TEMP_TARGET_FAN_TEMP_MASK, pcs); |
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tcontrol_margin = sign_extend32(tcontrol_margin, 7) * MILLIDEGREE_PER_DEGREE; |
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priv->temp.target.tcontrol = priv->temp.target.tjmax - tcontrol_margin; |
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tthrottle_offset = FIELD_GET(TEMP_TARGET_TJ_OFFSET_MASK, pcs) * MILLIDEGREE_PER_DEGREE; |
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priv->temp.target.tthrottle = priv->temp.target.tjmax - tthrottle_offset; |
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peci_sensor_mark_updated(&priv->temp.target.state); |
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return 0; |
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} |
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static int get_temp_target(struct peci_cputemp *priv, enum peci_temp_target_type type, long *val) |
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{ |
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int ret; |
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mutex_lock(&priv->temp.target.state.lock); |
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ret = update_temp_target(priv); |
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if (ret) |
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goto unlock; |
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switch (type) { |
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case tcontrol_type: |
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*val = priv->temp.target.tcontrol; |
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break; |
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case tthrottle_type: |
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*val = priv->temp.target.tthrottle; |
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break; |
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case tjmax_type: |
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*val = priv->temp.target.tjmax; |
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break; |
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case crit_hyst_type: |
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*val = priv->temp.target.tjmax - priv->temp.target.tcontrol; |
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break; |
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default: |
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ret = -EOPNOTSUPP; |
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break; |
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} |
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unlock: |
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mutex_unlock(&priv->temp.target.state.lock); |
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return ret; |
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} |
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/* |
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* Error codes: |
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* 0x8000: General sensor error |
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* 0x8001: Reserved |
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* 0x8002: Underflow on reading value |
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* 0x8003-0x81ff: Reserved |
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*/ |
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static bool dts_valid(u16 val) |
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{ |
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return val < 0x8000 || val > 0x81ff; |
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} |
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/* |
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* Processors return a value of DTS reading in S10.6 fixed point format |
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* (16 bits: 10-bit signed magnitude, 6-bit fraction). |
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*/ |
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static s32 dts_ten_dot_six_to_millidegree(u16 val) |
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{ |
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return sign_extend32(val, 15) * MILLIDEGREE_PER_DEGREE / 64; |
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} |
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/* |
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* For older processors, thermal margin reading is returned in S8.8 fixed |
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* point format (16 bits: 8-bit signed magnitude, 8-bit fraction). |
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*/ |
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static s32 dts_eight_dot_eight_to_millidegree(u16 val) |
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{ |
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return sign_extend32(val, 15) * MILLIDEGREE_PER_DEGREE / 256; |
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} |
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static int get_die_temp(struct peci_cputemp *priv, long *val) |
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{ |
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int ret = 0; |
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long tjmax; |
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u16 temp; |
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mutex_lock(&priv->temp.die.state.lock); |
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if (!peci_sensor_need_update(&priv->temp.die.state)) |
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goto skip_update; |
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ret = peci_temp_read(priv->peci_dev, &temp); |
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if (ret) |
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goto err_unlock; |
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if (!dts_valid(temp)) { |
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ret = -EIO; |
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goto err_unlock; |
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} |
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ret = get_temp_target(priv, tjmax_type, &tjmax); |
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if (ret) |
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goto err_unlock; |
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priv->temp.die.value = (s32)tjmax + dts_ten_dot_six_to_millidegree(temp); |
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peci_sensor_mark_updated(&priv->temp.die.state); |
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skip_update: |
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*val = priv->temp.die.value; |
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err_unlock: |
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mutex_unlock(&priv->temp.die.state.lock); |
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return ret; |
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} |
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static int get_dts(struct peci_cputemp *priv, long *val) |
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{ |
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int ret = 0; |
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u16 thermal_margin; |
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long tcontrol; |
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u32 pcs; |
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mutex_lock(&priv->temp.dts.state.lock); |
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if (!peci_sensor_need_update(&priv->temp.dts.state)) |
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goto skip_update; |
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ret = peci_pcs_read(priv->peci_dev, PECI_PCS_THERMAL_MARGIN, 0, &pcs); |
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if (ret) |
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goto err_unlock; |
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thermal_margin = FIELD_GET(DTS_MARGIN_MASK, pcs); |
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if (!dts_valid(thermal_margin)) { |
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ret = -EIO; |
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goto err_unlock; |
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} |
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ret = get_temp_target(priv, tcontrol_type, &tcontrol); |
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if (ret) |
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goto err_unlock; |
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/* Note that the tcontrol should be available before calling it */ |
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priv->temp.dts.value = |
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(s32)tcontrol - priv->gen_info->thermal_margin_to_millidegree(thermal_margin); |
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peci_sensor_mark_updated(&priv->temp.dts.state); |
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skip_update: |
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*val = priv->temp.dts.value; |
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err_unlock: |
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mutex_unlock(&priv->temp.dts.state.lock); |
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return ret; |
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} |
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static int get_core_temp(struct peci_cputemp *priv, int core_index, long *val) |
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{ |
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int ret = 0; |
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u16 core_dts_margin; |
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long tjmax; |
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u32 pcs; |
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mutex_lock(&priv->temp.core[core_index].state.lock); |
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if (!peci_sensor_need_update(&priv->temp.core[core_index].state)) |
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goto skip_update; |
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ret = peci_pcs_read(priv->peci_dev, PECI_PCS_MODULE_TEMP, core_index, &pcs); |
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if (ret) |
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goto err_unlock; |
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core_dts_margin = FIELD_GET(PCS_MODULE_TEMP_MASK, pcs); |
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if (!dts_valid(core_dts_margin)) { |
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ret = -EIO; |
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goto err_unlock; |
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} |
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ret = get_temp_target(priv, tjmax_type, &tjmax); |
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if (ret) |
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goto err_unlock; |
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/* Note that the tjmax should be available before calling it */ |
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priv->temp.core[core_index].value = |
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(s32)tjmax + dts_ten_dot_six_to_millidegree(core_dts_margin); |
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peci_sensor_mark_updated(&priv->temp.core[core_index].state); |
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skip_update: |
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*val = priv->temp.core[core_index].value; |
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err_unlock: |
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mutex_unlock(&priv->temp.core[core_index].state.lock); |
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return ret; |
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} |
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static int cputemp_read_string(struct device *dev, enum hwmon_sensor_types type, |
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u32 attr, int channel, const char **str) |
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{ |
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struct peci_cputemp *priv = dev_get_drvdata(dev); |
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if (attr != hwmon_temp_label) |
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return -EOPNOTSUPP; |
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*str = channel < channel_core ? |
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cputemp_label[channel] : priv->coretemp_label[channel - channel_core]; |
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return 0; |
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} |
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static int cputemp_read(struct device *dev, enum hwmon_sensor_types type, |
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u32 attr, int channel, long *val) |
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{ |
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struct peci_cputemp *priv = dev_get_drvdata(dev); |
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switch (attr) { |
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case hwmon_temp_input: |
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switch (channel) { |
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case channel_die: |
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return get_die_temp(priv, val); |
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case channel_dts: |
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return get_dts(priv, val); |
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case channel_tcontrol: |
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return get_temp_target(priv, tcontrol_type, val); |
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case channel_tthrottle: |
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return get_temp_target(priv, tthrottle_type, val); |
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case channel_tjmax: |
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return get_temp_target(priv, tjmax_type, val); |
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default: |
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return get_core_temp(priv, channel - channel_core, val); |
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} |
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break; |
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case hwmon_temp_max: |
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return get_temp_target(priv, tcontrol_type, val); |
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case hwmon_temp_crit: |
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return get_temp_target(priv, tjmax_type, val); |
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case hwmon_temp_crit_hyst: |
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return get_temp_target(priv, crit_hyst_type, val); |
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default: |
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return -EOPNOTSUPP; |
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} |
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return 0; |
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} |
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static umode_t cputemp_is_visible(const void *data, enum hwmon_sensor_types type, |
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u32 attr, int channel) |
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{ |
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const struct peci_cputemp *priv = data; |
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if (channel > CPUTEMP_CHANNEL_NUMS) |
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return 0; |
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if (channel < channel_core) |
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return 0444; |
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if (test_bit(channel - channel_core, priv->core_mask)) |
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return 0444; |
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return 0; |
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} |
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static int init_core_mask(struct peci_cputemp *priv) |
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{ |
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struct peci_device *peci_dev = priv->peci_dev; |
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struct resolved_cores_reg *reg = priv->gen_info->reg; |
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u64 core_mask; |
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u32 data; |
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int ret; |
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/* Get the RESOLVED_CORES register value */ |
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switch (peci_dev->info.model) { |
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case INTEL_FAM6_ICELAKE_X: |
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case INTEL_FAM6_ICELAKE_D: |
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ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev, |
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reg->func, reg->offset + 4, &data); |
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if (ret) |
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return ret; |
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core_mask = (u64)data << 32; |
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ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev, |
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reg->func, reg->offset, &data); |
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if (ret) |
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return ret; |
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core_mask |= data; |
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break; |
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default: |
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ret = peci_pci_local_read(peci_dev, reg->bus, reg->dev, |
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reg->func, reg->offset, &data); |
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if (ret) |
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return ret; |
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core_mask = data; |
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break; |
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} |
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if (!core_mask) |
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return -EIO; |
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bitmap_from_u64(priv->core_mask, core_mask); |
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return 0; |
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} |
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static int create_temp_label(struct peci_cputemp *priv) |
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{ |
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unsigned long core_max = find_last_bit(priv->core_mask, CORE_NUMS_MAX); |
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int i; |
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priv->coretemp_label = devm_kzalloc(priv->dev, core_max * sizeof(char *), GFP_KERNEL); |
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if (!priv->coretemp_label) |
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return -ENOMEM; |
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for_each_set_bit(i, priv->core_mask, CORE_NUMS_MAX) { |
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priv->coretemp_label[i] = devm_kasprintf(priv->dev, GFP_KERNEL, "Core %d", i); |
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if (!priv->coretemp_label[i]) |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static void check_resolved_cores(struct peci_cputemp *priv) |
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{ |
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/* |
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* Failure to resolve cores is non-critical, we're still able to |
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* provide other sensor data. |
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*/ |
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if (init_core_mask(priv)) |
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return; |
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if (create_temp_label(priv)) |
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bitmap_zero(priv->core_mask, CORE_NUMS_MAX); |
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} |
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static void sensor_init(struct peci_cputemp *priv) |
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{ |
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int i; |
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mutex_init(&priv->temp.target.state.lock); |
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mutex_init(&priv->temp.die.state.lock); |
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mutex_init(&priv->temp.dts.state.lock); |
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for_each_set_bit(i, priv->core_mask, CORE_NUMS_MAX) |
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mutex_init(&priv->temp.core[i].state.lock); |
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} |
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static const struct hwmon_ops peci_cputemp_ops = { |
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.is_visible = cputemp_is_visible, |
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.read_string = cputemp_read_string, |
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.read = cputemp_read, |
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}; |
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static const struct hwmon_channel_info *peci_cputemp_info[] = { |
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HWMON_CHANNEL_INFO(temp, |
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/* Die temperature */ |
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HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | |
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HWMON_T_CRIT | HWMON_T_CRIT_HYST, |
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/* DTS margin */ |
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HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | |
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HWMON_T_CRIT | HWMON_T_CRIT_HYST, |
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/* Tcontrol temperature */ |
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HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_CRIT, |
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/* Tthrottle temperature */ |
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HWMON_T_LABEL | HWMON_T_INPUT, |
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/* Tjmax temperature */ |
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HWMON_T_LABEL | HWMON_T_INPUT, |
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/* Core temperature - for all core channels */ |
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[channel_core ... CPUTEMP_CHANNEL_NUMS - 1] = |
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HWMON_T_LABEL | HWMON_T_INPUT), |
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NULL |
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}; |
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static const struct hwmon_chip_info peci_cputemp_chip_info = { |
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.ops = &peci_cputemp_ops, |
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.info = peci_cputemp_info, |
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}; |
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static int peci_cputemp_probe(struct auxiliary_device *adev, |
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const struct auxiliary_device_id *id) |
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{ |
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struct device *dev = &adev->dev; |
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struct peci_device *peci_dev = to_peci_device(dev->parent); |
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struct peci_cputemp *priv; |
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struct device *hwmon_dev; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->name = devm_kasprintf(dev, GFP_KERNEL, "peci_cputemp.cpu%d", |
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peci_dev->info.socket_id); |
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if (!priv->name) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->peci_dev = peci_dev; |
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priv->gen_info = (const struct cpu_info *)id->driver_data; |
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/* |
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* This is just a sanity check. Since we're using commands that are |
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* guaranteed to be supported on a given platform, we should never see |
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* revision lower than expected. |
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*/ |
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if (peci_dev->info.peci_revision < priv->gen_info->min_peci_revision) |
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dev_warn(priv->dev, |
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"Unexpected PECI revision %#x, some features may be unavailable\n", |
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peci_dev->info.peci_revision); |
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check_resolved_cores(priv); |
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sensor_init(priv); |
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hwmon_dev = devm_hwmon_device_register_with_info(priv->dev, priv->name, |
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priv, &peci_cputemp_chip_info, NULL); |
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return PTR_ERR_OR_ZERO(hwmon_dev); |
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} |
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/* |
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* RESOLVED_CORES PCI configuration register may have different location on |
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* different platforms. |
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*/ |
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static struct resolved_cores_reg resolved_cores_reg_hsx = { |
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.bus = 1, |
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.dev = 30, |
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.func = 3, |
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.offset = 0xb4, |
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}; |
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static struct resolved_cores_reg resolved_cores_reg_icx = { |
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.bus = 14, |
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.dev = 30, |
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.func = 3, |
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.offset = 0xd0, |
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}; |
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static const struct cpu_info cpu_hsx = { |
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.reg = &resolved_cores_reg_hsx, |
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.min_peci_revision = 0x33, |
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.thermal_margin_to_millidegree = &dts_eight_dot_eight_to_millidegree, |
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}; |
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static const struct cpu_info cpu_icx = { |
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.reg = &resolved_cores_reg_icx, |
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.min_peci_revision = 0x40, |
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.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree, |
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}; |
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static const struct auxiliary_device_id peci_cputemp_ids[] = { |
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{ |
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.name = "peci_cpu.cputemp.hsx", |
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.driver_data = (kernel_ulong_t)&cpu_hsx, |
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}, |
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{ |
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.name = "peci_cpu.cputemp.bdx", |
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.driver_data = (kernel_ulong_t)&cpu_hsx, |
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}, |
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{ |
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.name = "peci_cpu.cputemp.bdxd", |
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.driver_data = (kernel_ulong_t)&cpu_hsx, |
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}, |
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{ |
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.name = "peci_cpu.cputemp.skx", |
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.driver_data = (kernel_ulong_t)&cpu_hsx, |
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}, |
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{ |
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.name = "peci_cpu.cputemp.icx", |
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.driver_data = (kernel_ulong_t)&cpu_icx, |
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}, |
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{ |
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.name = "peci_cpu.cputemp.icxd", |
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.driver_data = (kernel_ulong_t)&cpu_icx, |
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}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids); |
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static struct auxiliary_driver peci_cputemp_driver = { |
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.probe = peci_cputemp_probe, |
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.id_table = peci_cputemp_ids, |
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}; |
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module_auxiliary_driver(peci_cputemp_driver); |
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MODULE_AUTHOR("Jae Hyun Yoo <[email protected]>"); |
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MODULE_AUTHOR("Iwona Winiarska <[email protected]>"); |
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MODULE_DESCRIPTION("PECI cputemp driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_IMPORT_NS(PECI_CPU);
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