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287 lines
9.1 KiB
287 lines
9.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel 8255 Programmable Peripheral Interface |
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* Copyright (C) 2022 William Breathitt Gray |
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*/ |
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#include <linux/bitmap.h> |
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#include <linux/err.h> |
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#include <linux/export.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include "gpio-i8255.h" |
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#define I8255_CONTROL_PORTC_LOWER_DIRECTION BIT(0) |
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#define I8255_CONTROL_PORTB_DIRECTION BIT(1) |
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#define I8255_CONTROL_PORTC_UPPER_DIRECTION BIT(3) |
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#define I8255_CONTROL_PORTA_DIRECTION BIT(4) |
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#define I8255_CONTROL_MODE_SET BIT(7) |
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#define I8255_PORTA 0 |
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#define I8255_PORTB 1 |
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#define I8255_PORTC 2 |
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static int i8255_get_port(struct i8255 __iomem *const ppi, |
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const unsigned long io_port, const unsigned long mask) |
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{ |
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const unsigned long bank = io_port / 3; |
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const unsigned long ppi_port = io_port % 3; |
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return ioread8(&ppi[bank].port[ppi_port]) & mask; |
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} |
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static u8 i8255_direction_mask(const unsigned long offset) |
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{ |
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const unsigned long port_offset = offset % 8; |
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const unsigned long io_port = offset / 8; |
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const unsigned long ppi_port = io_port % 3; |
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switch (ppi_port) { |
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case I8255_PORTA: |
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return I8255_CONTROL_PORTA_DIRECTION; |
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case I8255_PORTB: |
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return I8255_CONTROL_PORTB_DIRECTION; |
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case I8255_PORTC: |
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/* Port C can be configured by nibble */ |
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if (port_offset >= 4) |
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return I8255_CONTROL_PORTC_UPPER_DIRECTION; |
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return I8255_CONTROL_PORTC_LOWER_DIRECTION; |
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default: |
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/* Should never reach this path */ |
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return 0; |
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} |
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} |
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static void i8255_set_port(struct i8255 __iomem *const ppi, |
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struct i8255_state *const state, |
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const unsigned long io_port, |
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const unsigned long mask, const unsigned long bits) |
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{ |
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const unsigned long bank = io_port / 3; |
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const unsigned long ppi_port = io_port % 3; |
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unsigned long flags; |
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unsigned long out_state; |
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spin_lock_irqsave(&state[bank].lock, flags); |
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out_state = ioread8(&ppi[bank].port[ppi_port]); |
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out_state = (out_state & ~mask) | (bits & mask); |
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iowrite8(out_state, &ppi[bank].port[ppi_port]); |
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spin_unlock_irqrestore(&state[bank].lock, flags); |
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} |
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/** |
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* i8255_direction_input - configure signal offset as input |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @state: devices states of the respective PPI banks |
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* @offset: signal offset to configure as input |
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* |
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* Configures a signal @offset as input for the respective Intel 8255 |
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* Programmable Peripheral Interface (@ppi) banks. The @state control_state |
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* values are updated to reflect the new configuration. |
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*/ |
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void i8255_direction_input(struct i8255 __iomem *const ppi, |
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struct i8255_state *const state, |
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const unsigned long offset) |
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{ |
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const unsigned long io_port = offset / 8; |
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const unsigned long bank = io_port / 3; |
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unsigned long flags; |
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spin_lock_irqsave(&state[bank].lock, flags); |
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state[bank].control_state |= I8255_CONTROL_MODE_SET; |
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state[bank].control_state |= i8255_direction_mask(offset); |
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iowrite8(state[bank].control_state, &ppi[bank].control); |
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spin_unlock_irqrestore(&state[bank].lock, flags); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_direction_input, I8255); |
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/** |
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* i8255_direction_output - configure signal offset as output |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @state: devices states of the respective PPI banks |
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* @offset: signal offset to configure as output |
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* @value: signal value to output |
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* |
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* Configures a signal @offset as output for the respective Intel 8255 |
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* Programmable Peripheral Interface (@ppi) banks and sets the respective signal |
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* output to the desired @value. The @state control_state values are updated to |
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* reflect the new configuration. |
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*/ |
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void i8255_direction_output(struct i8255 __iomem *const ppi, |
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struct i8255_state *const state, |
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const unsigned long offset, |
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const unsigned long value) |
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{ |
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const unsigned long io_port = offset / 8; |
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const unsigned long bank = io_port / 3; |
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unsigned long flags; |
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spin_lock_irqsave(&state[bank].lock, flags); |
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state[bank].control_state |= I8255_CONTROL_MODE_SET; |
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state[bank].control_state &= ~i8255_direction_mask(offset); |
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iowrite8(state[bank].control_state, &ppi[bank].control); |
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spin_unlock_irqrestore(&state[bank].lock, flags); |
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i8255_set(ppi, state, offset, value); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_direction_output, I8255); |
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/** |
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* i8255_get - get signal value at signal offset |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @offset: offset of signal to get |
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* |
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* Returns the signal value (0=low, 1=high) for the signal at @offset for the |
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* respective Intel 8255 Programmable Peripheral Interface (@ppi) banks. |
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*/ |
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int i8255_get(struct i8255 __iomem *const ppi, const unsigned long offset) |
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{ |
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const unsigned long io_port = offset / 8; |
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const unsigned long offset_mask = BIT(offset % 8); |
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return !!i8255_get_port(ppi, io_port, offset_mask); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_get, I8255); |
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/** |
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* i8255_get_direction - get the I/O direction for a signal offset |
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* @state: devices states of the respective PPI banks |
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* @offset: offset of signal to get direction |
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* |
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* Returns the signal direction (0=output, 1=input) for the signal at @offset. |
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*/ |
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int i8255_get_direction(const struct i8255_state *const state, |
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const unsigned long offset) |
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{ |
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const unsigned long io_port = offset / 8; |
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const unsigned long bank = io_port / 3; |
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return !!(state[bank].control_state & i8255_direction_mask(offset)); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_get_direction, I8255); |
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/** |
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* i8255_get_multiple - get multiple signal values at multiple signal offsets |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @mask: mask of signals to get |
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* @bits: bitmap to store signal values |
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* @ngpio: number of GPIO signals of the respective PPI banks |
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* |
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* Stores in @bits the values (0=low, 1=high) for the signals defined by @mask |
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* for the respective Intel 8255 Programmable Peripheral Interface (@ppi) banks. |
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*/ |
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void i8255_get_multiple(struct i8255 __iomem *const ppi, |
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const unsigned long *const mask, |
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unsigned long *const bits, const unsigned long ngpio) |
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{ |
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unsigned long offset; |
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unsigned long port_mask; |
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unsigned long io_port; |
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unsigned long port_state; |
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bitmap_zero(bits, ngpio); |
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for_each_set_clump8(offset, port_mask, mask, ngpio) { |
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io_port = offset / 8; |
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port_state = i8255_get_port(ppi, io_port, port_mask); |
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bitmap_set_value8(bits, port_state, offset); |
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} |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_get_multiple, I8255); |
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/** |
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* i8255_mode0_output - configure all PPI ports to MODE 0 output mode |
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* @ppi: Intel 8255 Programmable Peripheral Interface bank |
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* |
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* Configures all Intel 8255 Programmable Peripheral Interface (@ppi) ports to |
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* MODE 0 (Basic Input/Output) output mode. |
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*/ |
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void i8255_mode0_output(struct i8255 __iomem *const ppi) |
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{ |
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iowrite8(I8255_CONTROL_MODE_SET, &ppi->control); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_mode0_output, I8255); |
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/** |
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* i8255_set - set signal value at signal offset |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @state: devices states of the respective PPI banks |
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* @offset: offset of signal to set |
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* @value: value of signal to set |
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* |
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* Assigns output @value for the signal at @offset for the respective Intel 8255 |
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* Programmable Peripheral Interface (@ppi) banks. |
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*/ |
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void i8255_set(struct i8255 __iomem *const ppi, struct i8255_state *const state, |
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const unsigned long offset, const unsigned long value) |
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{ |
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const unsigned long io_port = offset / 8; |
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const unsigned long port_offset = offset % 8; |
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const unsigned long mask = BIT(port_offset); |
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const unsigned long bits = value << port_offset; |
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i8255_set_port(ppi, state, io_port, mask, bits); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_set, I8255); |
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/** |
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* i8255_set_multiple - set signal values at multiple signal offsets |
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* @ppi: Intel 8255 Programmable Peripheral Interface banks |
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* @state: devices states of the respective PPI banks |
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* @mask: mask of signals to set |
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* @bits: bitmap of signal output values |
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* @ngpio: number of GPIO signals of the respective PPI banks |
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* |
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* Assigns output values defined by @bits for the signals defined by @mask for |
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* the respective Intel 8255 Programmable Peripheral Interface (@ppi) banks. |
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*/ |
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void i8255_set_multiple(struct i8255 __iomem *const ppi, |
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struct i8255_state *const state, |
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const unsigned long *const mask, |
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const unsigned long *const bits, |
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const unsigned long ngpio) |
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{ |
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unsigned long offset; |
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unsigned long port_mask; |
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unsigned long io_port; |
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unsigned long value; |
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for_each_set_clump8(offset, port_mask, mask, ngpio) { |
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io_port = offset / 8; |
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value = bitmap_get_value8(bits, offset); |
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i8255_set_port(ppi, state, io_port, port_mask, value); |
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} |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_set_multiple, I8255); |
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/** |
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* i8255_state_init - initialize i8255_state structure |
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* @state: devices states of the respective PPI banks |
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* @nbanks: number of Intel 8255 Programmable Peripheral Interface banks |
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* |
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* Initializes the @state of each Intel 8255 Programmable Peripheral Interface |
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* bank for use in i8255 library functions. |
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*/ |
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void i8255_state_init(struct i8255_state *const state, |
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const unsigned long nbanks) |
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{ |
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unsigned long bank; |
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for (bank = 0; bank < nbanks; bank++) |
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spin_lock_init(&state[bank].lock); |
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} |
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EXPORT_SYMBOL_NS_GPL(i8255_state_init, I8255); |
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MODULE_AUTHOR("William Breathitt Gray"); |
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MODULE_DESCRIPTION("Intel 8255 Programmable Peripheral Interface"); |
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MODULE_LICENSE("GPL");
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