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268 lines
8.7 KiB
268 lines
8.7 KiB
# SPDX-License-Identifier: GPL-2.0-only |
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# |
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# FPGA framework configuration |
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# |
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menuconfig FPGA |
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tristate "FPGA Configuration Framework" |
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help |
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Say Y here if you want support for configuring FPGAs from the |
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kernel. The FPGA framework adds an FPGA manager class and FPGA |
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manager drivers. |
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if FPGA |
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config FPGA_MGR_SOCFPGA |
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tristate "Altera SOCFPGA FPGA Manager" |
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depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST |
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help |
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FPGA manager driver support for Altera SOCFPGA. |
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config FPGA_MGR_SOCFPGA_A10 |
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tristate "Altera SoCFPGA Arria10" |
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depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST |
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select REGMAP_MMIO |
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help |
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FPGA manager driver support for Altera Arria10 SoCFPGA. |
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config ALTERA_PR_IP_CORE |
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tristate "Altera Partial Reconfiguration IP Core" |
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help |
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Core driver support for Altera Partial Reconfiguration IP component |
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config ALTERA_PR_IP_CORE_PLAT |
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tristate "Platform support of Altera Partial Reconfiguration IP Core" |
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depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM |
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help |
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Platform driver support for Altera Partial Reconfiguration IP |
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component |
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config FPGA_MGR_ALTERA_PS_SPI |
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tristate "Altera FPGA Passive Serial over SPI" |
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depends on SPI |
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select BITREVERSE |
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help |
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FPGA manager driver support for Altera Arria/Cyclone/Stratix |
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using the passive serial interface over SPI. |
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config FPGA_MGR_ALTERA_CVP |
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tristate "Altera CvP FPGA Manager" |
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depends on PCI |
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help |
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FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, |
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Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. |
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config FPGA_MGR_ZYNQ_FPGA |
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tristate "Xilinx Zynq FPGA" |
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depends on ARCH_ZYNQ || COMPILE_TEST |
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help |
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FPGA manager driver support for Xilinx Zynq FPGAs. |
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config FPGA_MGR_STRATIX10_SOC |
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tristate "Intel Stratix10 SoC FPGA Manager" |
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depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE) |
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help |
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FPGA manager driver support for the Intel Stratix10 SoC. |
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config FPGA_MGR_XILINX_SPI |
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tristate "Xilinx Configuration over Slave Serial (SPI)" |
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depends on SPI |
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help |
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FPGA manager driver support for Xilinx FPGA configuration |
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over slave serial interface. |
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config FPGA_MGR_ICE40_SPI |
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tristate "Lattice iCE40 SPI" |
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depends on OF && SPI |
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help |
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FPGA manager driver support for Lattice iCE40 FPGAs over SPI. |
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config FPGA_MGR_MACHXO2_SPI |
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tristate "Lattice MachXO2 SPI" |
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depends on SPI |
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help |
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FPGA manager driver support for Lattice MachXO2 configuration |
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over slave SPI interface. |
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config FPGA_MGR_TS73XX |
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tristate "Technologic Systems TS-73xx SBC FPGA Manager" |
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depends on ARCH_EP93XX && MACH_TS72XX |
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help |
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FPGA manager driver support for the Altera Cyclone II FPGA |
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present on the TS-73xx SBC boards. |
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config FPGA_BRIDGE |
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tristate "FPGA Bridge Framework" |
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help |
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Say Y here if you want to support bridges connected between host |
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processors and FPGAs or between FPGAs. |
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config SOCFPGA_FPGA_BRIDGE |
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tristate "Altera SoCFPGA FPGA Bridges" |
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depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE |
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help |
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Say Y to enable drivers for FPGA bridges for Altera SOCFPGA |
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devices. |
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config ALTERA_FREEZE_BRIDGE |
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tristate "Altera FPGA Freeze Bridge" |
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depends on FPGA_BRIDGE && HAS_IOMEM |
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help |
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Say Y to enable drivers for Altera FPGA Freeze bridges. A |
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freeze bridge is a bridge that exists in the FPGA fabric to |
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isolate one region of the FPGA from the busses while that |
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region is being reprogrammed. |
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config XILINX_PR_DECOUPLER |
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tristate "Xilinx LogiCORE PR Decoupler" |
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depends on FPGA_BRIDGE |
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depends on HAS_IOMEM |
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help |
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Say Y to enable drivers for Xilinx LogiCORE PR Decoupler |
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or Xilinx Dynamic Function eXchange AIX Shutdown Manager. |
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The PR Decoupler exists in the FPGA fabric to isolate one |
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region of the FPGA from the busses while that region is |
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being reprogrammed during partial reconfig. |
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The Dynamic Function eXchange AXI shutdown manager prevents |
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AXI traffic from passing through the bridge. The controller |
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safely handles AXI4MM and AXI4-Lite interfaces on a |
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Reconfigurable Partition when it is undergoing dynamic |
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reconfiguration, preventing the system deadlock that can |
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occur if AXI transactions are interrupted by DFX. |
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config FPGA_REGION |
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tristate "FPGA Region" |
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depends on FPGA_BRIDGE |
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help |
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FPGA Region common code. An FPGA Region controls an FPGA Manager |
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and the FPGA Bridges associated with either a reconfigurable |
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region of an FPGA or a whole FPGA. |
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config OF_FPGA_REGION |
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tristate "FPGA Region Device Tree Overlay Support" |
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depends on OF && FPGA_REGION |
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help |
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Support for loading FPGA images by applying a Device Tree |
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overlay. |
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config FPGA_DFL |
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tristate "FPGA Device Feature List (DFL) support" |
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select FPGA_BRIDGE |
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select FPGA_REGION |
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depends on HAS_IOMEM |
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help |
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Device Feature List (DFL) defines a feature list structure that |
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creates a linked list of feature headers within the MMIO space |
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to provide an extensible way of adding features for FPGA. |
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Driver can walk through the feature headers to enumerate feature |
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devices (e.g. FPGA Management Engine, Port and Accelerator |
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Function Unit) and their private features for target FPGA devices. |
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Select this option to enable common support for Field-Programmable |
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Gate Array (FPGA) solutions which implement Device Feature List. |
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It provides enumeration APIs and feature device infrastructure. |
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config FPGA_DFL_FME |
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tristate "FPGA DFL FME Driver" |
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depends on FPGA_DFL && HWMON && PERF_EVENTS |
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help |
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The FPGA Management Engine (FME) is a feature device implemented |
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under Device Feature List (DFL) framework. Select this option to |
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enable the platform device driver for FME which implements all |
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FPGA platform level management features. There shall be one FME |
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per DFL based FPGA device. |
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config FPGA_DFL_FME_MGR |
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tristate "FPGA DFL FME Manager Driver" |
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depends on FPGA_DFL_FME && HAS_IOMEM |
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help |
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Say Y to enable FPGA Manager driver for FPGA Management Engine. |
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config FPGA_DFL_FME_BRIDGE |
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tristate "FPGA DFL FME Bridge Driver" |
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depends on FPGA_DFL_FME && HAS_IOMEM |
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help |
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Say Y to enable FPGA Bridge driver for FPGA Management Engine. |
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config FPGA_DFL_FME_REGION |
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tristate "FPGA DFL FME Region Driver" |
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depends on FPGA_DFL_FME && HAS_IOMEM |
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help |
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Say Y to enable FPGA Region driver for FPGA Management Engine. |
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config FPGA_DFL_AFU |
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tristate "FPGA DFL AFU Driver" |
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depends on FPGA_DFL |
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help |
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This is the driver for FPGA Accelerated Function Unit (AFU) which |
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implements AFU and Port management features. A User AFU connects |
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to the FPGA infrastructure via a Port. There may be more than one |
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Port/AFU per DFL based FPGA device. |
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config FPGA_DFL_NIOS_INTEL_PAC_N3000 |
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tristate "FPGA DFL NIOS Driver for Intel PAC N3000" |
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depends on FPGA_DFL |
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select REGMAP |
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help |
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This is the driver for the N3000 Nios private feature on Intel |
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PAC (Programmable Acceleration Card) N3000. It communicates |
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with the embedded Nios processor to configure the retimers on |
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the card. It also instantiates the SPI master (spi-altera) for |
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the card's BMC (Board Management Controller). |
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config FPGA_DFL_PCI |
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tristate "FPGA DFL PCIe Device Driver" |
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depends on PCI && FPGA_DFL |
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help |
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Select this option to enable PCIe driver for PCIe-based |
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Field-Programmable Gate Array (FPGA) solutions which implement |
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the Device Feature List (DFL). This driver provides interfaces |
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for userspace applications to configure, enumerate, open and access |
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FPGA accelerators on the FPGA DFL devices, enables system level |
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management functions such as FPGA partial reconfiguration, power |
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management and virtualization with DFL framework and DFL feature |
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device drivers. |
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To compile this as a module, choose M here. |
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config FPGA_MGR_ZYNQMP_FPGA |
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tristate "Xilinx ZynqMP FPGA" |
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depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) |
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help |
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FPGA manager driver support for Xilinx ZynqMP FPGAs. |
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This driver uses the processor configuration port(PCAP) |
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to configure the programmable logic(PL) through PS |
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on ZynqMP SoC. |
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config FPGA_MGR_VERSAL_FPGA |
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tristate "Xilinx Versal FPGA" |
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depends on ARCH_ZYNQMP || COMPILE_TEST |
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help |
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Select this option to enable FPGA manager driver support for |
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Xilinx Versal SoC. This driver uses the firmware interface to |
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configure the programmable logic(PL). |
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To compile this as a module, choose M here. |
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config FPGA_M10_BMC_SEC_UPDATE |
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tristate "Intel MAX10 BMC Secure Update driver" |
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depends on MFD_INTEL_M10_BMC |
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select FW_LOADER |
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select FW_UPLOAD |
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help |
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Secure update support for the Intel MAX10 board management |
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controller. |
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This is a subdriver of the Intel MAX10 board management controller |
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(BMC) and provides support for secure updates for the BMC image, |
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the FPGA image, the Root Entry Hashes, etc. |
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config FPGA_MGR_MICROCHIP_SPI |
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tristate "Microchip Polarfire SPI FPGA manager" |
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depends on SPI |
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help |
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FPGA manager driver support for Microchip Polarfire FPGAs |
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programming over slave SPI interface with .dat formatted |
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bitstream image. |
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endif # FPGA
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