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639 lines
17 KiB
639 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Xilinx 'Clocking Wizard' driver |
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* |
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* Copyright (C) 2013 - 2021 Xilinx |
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* |
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* Sören Brinkmann <[email protected]> |
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* |
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*/ |
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|
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/module.h> |
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#include <linux/err.h> |
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#include <linux/iopoll.h> |
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#define WZRD_NUM_OUTPUTS 7 |
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#define WZRD_ACLK_MAX_FREQ 250000000UL |
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#define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n)) |
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#define WZRD_CLKOUT0_FRAC_EN BIT(18) |
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#define WZRD_CLKFBOUT_FRAC_EN BIT(26) |
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#define WZRD_CLKFBOUT_MULT_SHIFT 8 |
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#define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT) |
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#define WZRD_CLKFBOUT_FRAC_SHIFT 16 |
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#define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT) |
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#define WZRD_DIVCLK_DIVIDE_SHIFT 0 |
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#define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) |
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#define WZRD_CLKOUT_DIVIDE_SHIFT 0 |
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#define WZRD_CLKOUT_DIVIDE_WIDTH 8 |
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#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) |
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#define WZRD_CLKOUT_FRAC_SHIFT 8 |
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#define WZRD_CLKOUT_FRAC_MASK 0x3ff |
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#define WZRD_DR_MAX_INT_DIV_VALUE 255 |
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#define WZRD_DR_STATUS_REG_OFFSET 0x04 |
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#define WZRD_DR_LOCK_BIT_MASK 0x00000001 |
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#define WZRD_DR_INIT_REG_OFFSET 0x25C |
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#define WZRD_DR_DIV_TO_PHASE_OFFSET 4 |
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#define WZRD_DR_BEGIN_DYNA_RECONF 0x03 |
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#define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07 |
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#define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02 |
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#define WZRD_USEC_POLL 10 |
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#define WZRD_TIMEOUT_POLL 1000 |
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/* Get the mask from width */ |
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#define div_mask(width) ((1 << (width)) - 1) |
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/* Extract divider instance from clock hardware instance */ |
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#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw) |
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enum clk_wzrd_int_clks { |
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wzrd_clk_mul, |
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wzrd_clk_mul_div, |
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wzrd_clk_mul_frac, |
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wzrd_clk_int_max |
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}; |
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/** |
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* struct clk_wzrd - Clock wizard private data structure |
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* |
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* @clk_data: Clock data |
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* @nb: Notifier block |
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* @base: Memory base |
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* @clk_in1: Handle to input clock 'clk_in1' |
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* @axi_clk: Handle to input clock 's_axi_aclk' |
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* @clks_internal: Internal clocks |
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* @clkout: Output clocks |
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* @speed_grade: Speed grade of the device |
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* @suspended: Flag indicating power state of the device |
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*/ |
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struct clk_wzrd { |
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struct clk_onecell_data clk_data; |
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struct notifier_block nb; |
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void __iomem *base; |
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struct clk *clk_in1; |
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struct clk *axi_clk; |
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struct clk *clks_internal[wzrd_clk_int_max]; |
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struct clk *clkout[WZRD_NUM_OUTPUTS]; |
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unsigned int speed_grade; |
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bool suspended; |
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}; |
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/** |
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* struct clk_wzrd_divider - clock divider specific to clk_wzrd |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @base: base address of register containing the divider |
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* @offset: offset address of register containing the divider |
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* @shift: shift to the divider bit field |
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* @width: width of the divider bit field |
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* @flags: clk_wzrd divider flags |
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* @table: array of value/divider pairs, last entry should have div = 0 |
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* @lock: register lock |
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*/ |
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struct clk_wzrd_divider { |
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struct clk_hw hw; |
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void __iomem *base; |
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u16 offset; |
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u8 shift; |
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u8 width; |
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u8 flags; |
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const struct clk_div_table *table; |
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spinlock_t *lock; /* divider lock */ |
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}; |
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#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) |
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/* maximum frequencies for input/output clocks per speed grade */ |
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static const unsigned long clk_wzrd_max_freq[] = { |
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800000000UL, |
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933000000UL, |
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1066000000UL |
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}; |
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/* spin lock variable for clk_wzrd */ |
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static DEFINE_SPINLOCK(clkwzrd_lock); |
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static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); |
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void __iomem *div_addr = divider->base + divider->offset; |
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unsigned int val; |
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val = readl(div_addr) >> divider->shift; |
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val &= div_mask(divider->width); |
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return divider_recalc_rate(hw, parent_rate, val, divider->table, |
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divider->flags, divider->width); |
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} |
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static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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int err; |
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u32 value; |
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unsigned long flags = 0; |
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); |
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void __iomem *div_addr = divider->base + divider->offset; |
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if (divider->lock) |
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spin_lock_irqsave(divider->lock, flags); |
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else |
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__acquire(divider->lock); |
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value = DIV_ROUND_CLOSEST(parent_rate, rate); |
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/* Cap the value to max */ |
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min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); |
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/* Set divisor and clear phase offset */ |
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writel(value, div_addr); |
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writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); |
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/* Check status register */ |
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err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, |
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value, value & WZRD_DR_LOCK_BIT_MASK, |
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); |
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if (err) |
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goto err_reconfig; |
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/* Initiate reconfiguration */ |
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writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, |
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divider->base + WZRD_DR_INIT_REG_OFFSET); |
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writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, |
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divider->base + WZRD_DR_INIT_REG_OFFSET); |
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/* Check status register */ |
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err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, |
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value, value & WZRD_DR_LOCK_BIT_MASK, |
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); |
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err_reconfig: |
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if (divider->lock) |
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spin_unlock_irqrestore(divider->lock, flags); |
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else |
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__release(divider->lock); |
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return err; |
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} |
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static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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u8 div; |
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/* |
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* since we don't change parent rate we just round rate to closest |
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* achievable |
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*/ |
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div = DIV_ROUND_CLOSEST(*prate, rate); |
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return *prate / div; |
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} |
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static const struct clk_ops clk_wzrd_clk_divider_ops = { |
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.round_rate = clk_wzrd_round_rate, |
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.set_rate = clk_wzrd_dynamic_reconfig, |
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.recalc_rate = clk_wzrd_recalc_rate, |
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}; |
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static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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unsigned int val; |
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u32 div, frac; |
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); |
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void __iomem *div_addr = divider->base + divider->offset; |
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val = readl(div_addr); |
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div = val & div_mask(divider->width); |
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frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK; |
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return mult_frac(parent_rate, 1000, (div * 1000) + frac); |
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} |
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static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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int err; |
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u32 value, pre; |
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unsigned long rate_div, f, clockout0_div; |
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); |
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void __iomem *div_addr = divider->base + divider->offset; |
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rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); |
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clockout0_div = rate_div / 1000; |
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pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); |
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f = (u32)(pre - (clockout0_div * 1000)); |
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f = f & WZRD_CLKOUT_FRAC_MASK; |
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f = f << WZRD_CLKOUT_DIVIDE_WIDTH; |
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value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK)); |
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/* Set divisor and clear phase offset */ |
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writel(value, div_addr); |
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writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); |
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/* Check status register */ |
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err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, |
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value & WZRD_DR_LOCK_BIT_MASK, |
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); |
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if (err) |
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return err; |
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/* Initiate reconfiguration */ |
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writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, |
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divider->base + WZRD_DR_INIT_REG_OFFSET); |
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writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, |
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divider->base + WZRD_DR_INIT_REG_OFFSET); |
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/* Check status register */ |
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return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, |
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value & WZRD_DR_LOCK_BIT_MASK, |
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); |
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} |
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static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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return rate; |
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} |
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static const struct clk_ops clk_wzrd_clk_divider_ops_f = { |
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.round_rate = clk_wzrd_round_rate_f, |
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.set_rate = clk_wzrd_dynamic_reconfig_f, |
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.recalc_rate = clk_wzrd_recalc_ratef, |
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}; |
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static struct clk *clk_wzrd_register_divf(struct device *dev, |
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const char *name, |
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const char *parent_name, |
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unsigned long flags, |
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void __iomem *base, u16 offset, |
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u8 shift, u8 width, |
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u8 clk_divider_flags, |
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const struct clk_div_table *table, |
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spinlock_t *lock) |
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{ |
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struct clk_wzrd_divider *div; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clk_wzrd_clk_divider_ops_f; |
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init.flags = flags; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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div->base = base; |
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div->offset = offset; |
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div->shift = shift; |
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div->width = width; |
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div->flags = clk_divider_flags; |
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div->lock = lock; |
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div->hw.init = &init; |
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div->table = table; |
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hw = &div->hw; |
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ret = devm_clk_hw_register(dev, hw); |
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if (ret) |
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return ERR_PTR(ret); |
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return hw->clk; |
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} |
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static struct clk *clk_wzrd_register_divider(struct device *dev, |
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const char *name, |
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const char *parent_name, |
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unsigned long flags, |
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void __iomem *base, u16 offset, |
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u8 shift, u8 width, |
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u8 clk_divider_flags, |
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const struct clk_div_table *table, |
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spinlock_t *lock) |
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{ |
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struct clk_wzrd_divider *div; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clk_wzrd_clk_divider_ops; |
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init.flags = flags; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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div->base = base; |
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div->offset = offset; |
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div->shift = shift; |
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div->width = width; |
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div->flags = clk_divider_flags; |
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div->lock = lock; |
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div->hw.init = &init; |
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div->table = table; |
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hw = &div->hw; |
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ret = devm_clk_hw_register(dev, hw); |
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if (ret) |
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hw = ERR_PTR(ret); |
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return hw->clk; |
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} |
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static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, |
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void *data) |
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{ |
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unsigned long max; |
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struct clk_notifier_data *ndata = data; |
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struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb); |
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if (clk_wzrd->suspended) |
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return NOTIFY_OK; |
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if (ndata->clk == clk_wzrd->clk_in1) |
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max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; |
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else if (ndata->clk == clk_wzrd->axi_clk) |
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max = WZRD_ACLK_MAX_FREQ; |
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else |
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return NOTIFY_DONE; /* should never happen */ |
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switch (event) { |
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case PRE_RATE_CHANGE: |
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if (ndata->new_rate > max) |
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return NOTIFY_BAD; |
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return NOTIFY_OK; |
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case POST_RATE_CHANGE: |
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case ABORT_RATE_CHANGE: |
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default: |
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return NOTIFY_DONE; |
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} |
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} |
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static int __maybe_unused clk_wzrd_suspend(struct device *dev) |
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{ |
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struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); |
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clk_disable_unprepare(clk_wzrd->axi_clk); |
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clk_wzrd->suspended = true; |
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return 0; |
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} |
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static int __maybe_unused clk_wzrd_resume(struct device *dev) |
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{ |
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int ret; |
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struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); |
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ret = clk_prepare_enable(clk_wzrd->axi_clk); |
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if (ret) { |
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dev_err(dev, "unable to enable s_axi_aclk\n"); |
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return ret; |
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} |
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clk_wzrd->suspended = false; |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, |
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clk_wzrd_resume); |
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static int clk_wzrd_probe(struct platform_device *pdev) |
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{ |
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int i, ret; |
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u32 reg, reg_f, mult; |
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unsigned long rate; |
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const char *clk_name; |
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void __iomem *ctrl_reg; |
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struct clk_wzrd *clk_wzrd; |
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struct device_node *np = pdev->dev.of_node; |
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int nr_outputs; |
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unsigned long flags = 0; |
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clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); |
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if (!clk_wzrd) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, clk_wzrd); |
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clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(clk_wzrd->base)) |
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return PTR_ERR(clk_wzrd->base); |
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ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); |
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if (!ret) { |
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if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { |
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dev_warn(&pdev->dev, "invalid speed grade '%d'\n", |
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clk_wzrd->speed_grade); |
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clk_wzrd->speed_grade = 0; |
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} |
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} |
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clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); |
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if (IS_ERR(clk_wzrd->clk_in1)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), |
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"clk_in1 not found\n"); |
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clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); |
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if (IS_ERR(clk_wzrd->axi_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), |
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"s_axi_aclk not found\n"); |
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ret = clk_prepare_enable(clk_wzrd->axi_clk); |
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if (ret) { |
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dev_err(&pdev->dev, "enabling s_axi_aclk failed\n"); |
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return ret; |
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} |
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rate = clk_get_rate(clk_wzrd->axi_clk); |
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if (rate > WZRD_ACLK_MAX_FREQ) { |
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dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", |
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rate); |
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ret = -EINVAL; |
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goto err_disable_clk; |
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} |
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reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)); |
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reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK; |
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reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT; |
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reg = reg & WZRD_CLKFBOUT_MULT_MASK; |
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reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT; |
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mult = (reg * 1000) + reg_f; |
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clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); |
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if (!clk_name) { |
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ret = -ENOMEM; |
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goto err_disable_clk; |
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} |
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ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); |
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if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { |
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ret = -EINVAL; |
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goto err_disable_clk; |
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} |
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if (nr_outputs == 1) |
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flags = CLK_SET_RATE_PARENT; |
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clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor |
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(&pdev->dev, clk_name, |
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__clk_get_name(clk_wzrd->clk_in1), |
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0, mult, 1000); |
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if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { |
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dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); |
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ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); |
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goto err_disable_clk; |
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} |
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clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); |
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if (!clk_name) { |
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ret = -ENOMEM; |
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goto err_rm_int_clk; |
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} |
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ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0); |
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/* register div */ |
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clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider |
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(&pdev->dev, clk_name, |
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__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), |
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flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); |
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if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { |
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dev_err(&pdev->dev, "unable to register divider clock\n"); |
|
ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); |
|
goto err_rm_int_clk; |
|
} |
|
|
|
/* register div per output */ |
|
for (i = nr_outputs - 1; i >= 0 ; i--) { |
|
const char *clkout_name; |
|
|
|
clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i); |
|
if (!clkout_name) { |
|
ret = -ENOMEM; |
|
goto err_rm_int_clk; |
|
} |
|
|
|
if (!i) |
|
clk_wzrd->clkout[i] = clk_wzrd_register_divf |
|
(&pdev->dev, clkout_name, |
|
clk_name, flags, |
|
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), |
|
WZRD_CLKOUT_DIVIDE_SHIFT, |
|
WZRD_CLKOUT_DIVIDE_WIDTH, |
|
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
|
NULL, &clkwzrd_lock); |
|
else |
|
clk_wzrd->clkout[i] = clk_wzrd_register_divider |
|
(&pdev->dev, clkout_name, |
|
clk_name, 0, |
|
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), |
|
WZRD_CLKOUT_DIVIDE_SHIFT, |
|
WZRD_CLKOUT_DIVIDE_WIDTH, |
|
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
|
NULL, &clkwzrd_lock); |
|
if (IS_ERR(clk_wzrd->clkout[i])) { |
|
int j; |
|
|
|
for (j = i + 1; j < nr_outputs; j++) |
|
clk_unregister(clk_wzrd->clkout[j]); |
|
dev_err(&pdev->dev, |
|
"unable to register divider clock\n"); |
|
ret = PTR_ERR(clk_wzrd->clkout[i]); |
|
goto err_rm_int_clks; |
|
} |
|
} |
|
|
|
kfree(clk_name); |
|
|
|
clk_wzrd->clk_data.clks = clk_wzrd->clkout; |
|
clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); |
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data); |
|
|
|
if (clk_wzrd->speed_grade) { |
|
clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; |
|
|
|
ret = clk_notifier_register(clk_wzrd->clk_in1, |
|
&clk_wzrd->nb); |
|
if (ret) |
|
dev_warn(&pdev->dev, |
|
"unable to register clock notifier\n"); |
|
|
|
ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb); |
|
if (ret) |
|
dev_warn(&pdev->dev, |
|
"unable to register clock notifier\n"); |
|
} |
|
|
|
return 0; |
|
|
|
err_rm_int_clks: |
|
clk_unregister(clk_wzrd->clks_internal[1]); |
|
err_rm_int_clk: |
|
kfree(clk_name); |
|
clk_unregister(clk_wzrd->clks_internal[0]); |
|
err_disable_clk: |
|
clk_disable_unprepare(clk_wzrd->axi_clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int clk_wzrd_remove(struct platform_device *pdev) |
|
{ |
|
int i; |
|
struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); |
|
|
|
of_clk_del_provider(pdev->dev.of_node); |
|
|
|
for (i = 0; i < WZRD_NUM_OUTPUTS; i++) |
|
clk_unregister(clk_wzrd->clkout[i]); |
|
for (i = 0; i < wzrd_clk_int_max; i++) |
|
clk_unregister(clk_wzrd->clks_internal[i]); |
|
|
|
if (clk_wzrd->speed_grade) { |
|
clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb); |
|
clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb); |
|
} |
|
|
|
clk_disable_unprepare(clk_wzrd->axi_clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id clk_wzrd_ids[] = { |
|
{ .compatible = "xlnx,clocking-wizard" }, |
|
{ .compatible = "xlnx,clocking-wizard-v5.2" }, |
|
{ .compatible = "xlnx,clocking-wizard-v6.0" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, clk_wzrd_ids); |
|
|
|
static struct platform_driver clk_wzrd_driver = { |
|
.driver = { |
|
.name = "clk-wizard", |
|
.of_match_table = clk_wzrd_ids, |
|
.pm = &clk_wzrd_dev_pm_ops, |
|
}, |
|
.probe = clk_wzrd_probe, |
|
.remove = clk_wzrd_remove, |
|
}; |
|
module_platform_driver(clk_wzrd_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Soeren Brinkmann <[email protected]"); |
|
MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core");
|
|
|