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453 lines
11 KiB
453 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2015 Endless Mobile, Inc. |
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* Author: Carlo Caione <[email protected]> |
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* |
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* Copyright (c) 2018 Baylibre, SAS. |
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* Author: Jerome Brunet <[email protected]> |
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*/ |
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|
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/* |
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* In the most basic form, a Meson PLL is composed as follows: |
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* |
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* PLL |
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* +--------------------------------+ |
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* | | |
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* | +--+ | |
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* in >>-----[ /N ]--->| | +-----+ | |
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* | | |------| DCO |---->> out |
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* | +--------->| | +--v--+ | |
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* | | +--+ | | |
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* | | | | |
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* | +--[ *(M + (F/Fmax) ]<--+ | |
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* | | |
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* +--------------------------------+ |
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* |
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* out = in * (m + frac / frac_max) / n |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/math64.h> |
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#include <linux/module.h> |
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#include <linux/rational.h> |
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#include "clk-regmap.h" |
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#include "clk-pll.h" |
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static inline struct meson_clk_pll_data * |
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meson_clk_pll_data(struct clk_regmap *clk) |
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{ |
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return (struct meson_clk_pll_data *)clk->data; |
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} |
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static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) |
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{ |
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if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && |
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!MESON_PARM_APPLICABLE(&pll->frac)) |
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return 1; |
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return 0; |
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} |
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static unsigned long __pll_params_to_rate(unsigned long parent_rate, |
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unsigned int m, unsigned int n, |
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unsigned int frac, |
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struct meson_clk_pll_data *pll) |
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{ |
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u64 rate = (u64)parent_rate * m; |
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if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { |
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u64 frac_rate = (u64)parent_rate * frac; |
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rate += DIV_ROUND_UP_ULL(frac_rate, |
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(1 << pll->frac.width)); |
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} |
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return DIV_ROUND_UP_ULL(rate, n); |
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} |
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static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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unsigned int m, n, frac; |
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n = meson_parm_read(clk->map, &pll->n); |
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/* |
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* On some HW, N is set to zero on init. This value is invalid as |
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* it would result in a division by zero. The rate can't be |
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* calculated in this case |
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*/ |
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if (n == 0) |
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return 0; |
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m = meson_parm_read(clk->map, &pll->m); |
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frac = MESON_PARM_APPLICABLE(&pll->frac) ? |
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meson_parm_read(clk->map, &pll->frac) : |
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0; |
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return __pll_params_to_rate(parent_rate, m, n, frac, pll); |
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} |
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static unsigned int __pll_params_with_frac(unsigned long rate, |
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unsigned long parent_rate, |
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unsigned int m, |
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unsigned int n, |
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struct meson_clk_pll_data *pll) |
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{ |
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unsigned int frac_max = (1 << pll->frac.width); |
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u64 val = (u64)rate * n; |
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/* Bail out if we are already over the requested rate */ |
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if (rate < parent_rate * m / n) |
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return 0; |
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if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) |
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val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); |
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else |
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val = div_u64(val * frac_max, parent_rate); |
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val -= m * frac_max; |
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return min((unsigned int)val, (frac_max - 1)); |
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} |
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static bool meson_clk_pll_is_better(unsigned long rate, |
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unsigned long best, |
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unsigned long now, |
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struct meson_clk_pll_data *pll) |
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{ |
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if (__pll_round_closest_mult(pll)) { |
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/* Round Closest */ |
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if (abs(now - rate) < abs(best - rate)) |
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return true; |
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} else { |
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/* Round down */ |
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if (now <= rate && best < now) |
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return true; |
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} |
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return false; |
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} |
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static int meson_clk_get_pll_table_index(unsigned int index, |
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unsigned int *m, |
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unsigned int *n, |
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struct meson_clk_pll_data *pll) |
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{ |
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if (!pll->table[index].n) |
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return -EINVAL; |
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*m = pll->table[index].m; |
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*n = pll->table[index].n; |
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return 0; |
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} |
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static unsigned int meson_clk_get_pll_range_m(unsigned long rate, |
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unsigned long parent_rate, |
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unsigned int n, |
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struct meson_clk_pll_data *pll) |
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{ |
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u64 val = (u64)rate * n; |
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if (__pll_round_closest_mult(pll)) |
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return DIV_ROUND_CLOSEST_ULL(val, parent_rate); |
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return div_u64(val, parent_rate); |
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} |
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static int meson_clk_get_pll_range_index(unsigned long rate, |
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unsigned long parent_rate, |
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unsigned int index, |
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unsigned int *m, |
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unsigned int *n, |
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struct meson_clk_pll_data *pll) |
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{ |
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*n = index + 1; |
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/* Check the predivider range */ |
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if (*n >= (1 << pll->n.width)) |
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return -EINVAL; |
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if (*n == 1) { |
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/* Get the boundaries out the way */ |
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if (rate <= pll->range->min * parent_rate) { |
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*m = pll->range->min; |
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return -ENODATA; |
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} else if (rate >= pll->range->max * parent_rate) { |
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*m = pll->range->max; |
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return -ENODATA; |
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} |
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} |
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*m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); |
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/* the pre-divider gives a multiplier too big - stop */ |
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if (*m >= (1 << pll->m.width)) |
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return -EINVAL; |
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return 0; |
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} |
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static int meson_clk_get_pll_get_index(unsigned long rate, |
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unsigned long parent_rate, |
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unsigned int index, |
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unsigned int *m, |
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unsigned int *n, |
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struct meson_clk_pll_data *pll) |
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{ |
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if (pll->range) |
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return meson_clk_get_pll_range_index(rate, parent_rate, |
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index, m, n, pll); |
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else if (pll->table) |
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return meson_clk_get_pll_table_index(index, m, n, pll); |
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return -EINVAL; |
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} |
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static int meson_clk_get_pll_settings(unsigned long rate, |
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unsigned long parent_rate, |
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unsigned int *best_m, |
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unsigned int *best_n, |
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struct meson_clk_pll_data *pll) |
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{ |
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unsigned long best = 0, now = 0; |
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unsigned int i, m, n; |
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int ret; |
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for (i = 0, ret = 0; !ret; i++) { |
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ret = meson_clk_get_pll_get_index(rate, parent_rate, |
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i, &m, &n, pll); |
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if (ret == -EINVAL) |
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break; |
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now = __pll_params_to_rate(parent_rate, m, n, 0, pll); |
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if (meson_clk_pll_is_better(rate, best, now, pll)) { |
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best = now; |
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*best_m = m; |
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*best_n = n; |
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if (now == rate) |
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break; |
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} |
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} |
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return best ? 0 : -EINVAL; |
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} |
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static int meson_clk_pll_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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unsigned int m, n, frac; |
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unsigned long round; |
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int ret; |
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ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate, |
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&m, &n, pll); |
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if (ret) |
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return ret; |
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round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll); |
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if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) { |
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req->rate = round; |
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return 0; |
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} |
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/* |
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* The rate provided by the setting is not an exact match, let's |
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* try to improve the result using the fractional parameter |
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*/ |
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frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll); |
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req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll); |
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return 0; |
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} |
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static int meson_clk_pll_wait_lock(struct clk_hw *hw) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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int delay = 24000000; |
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do { |
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/* Is the clock locked now ? */ |
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if (meson_parm_read(clk->map, &pll->l)) |
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return 0; |
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delay--; |
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} while (delay > 0); |
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return -ETIMEDOUT; |
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} |
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static int meson_clk_pll_init(struct clk_hw *hw) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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if (pll->init_count) { |
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meson_parm_write(clk->map, &pll->rst, 1); |
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regmap_multi_reg_write(clk->map, pll->init_regs, |
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pll->init_count); |
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meson_parm_write(clk->map, &pll->rst, 0); |
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} |
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return 0; |
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} |
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static int meson_clk_pll_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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if (meson_parm_read(clk->map, &pll->rst) || |
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!meson_parm_read(clk->map, &pll->en) || |
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!meson_parm_read(clk->map, &pll->l)) |
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return 0; |
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return 1; |
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} |
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static int meson_clk_pcie_pll_enable(struct clk_hw *hw) |
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{ |
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meson_clk_pll_init(hw); |
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if (meson_clk_pll_wait_lock(hw)) |
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return -EIO; |
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return 0; |
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} |
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static int meson_clk_pll_enable(struct clk_hw *hw) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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/* do nothing if the PLL is already enabled */ |
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if (clk_hw_is_enabled(hw)) |
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return 0; |
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/* Make sure the pll is in reset */ |
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meson_parm_write(clk->map, &pll->rst, 1); |
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/* Enable the pll */ |
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meson_parm_write(clk->map, &pll->en, 1); |
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/* Take the pll out reset */ |
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meson_parm_write(clk->map, &pll->rst, 0); |
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if (meson_clk_pll_wait_lock(hw)) |
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return -EIO; |
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return 0; |
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} |
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static void meson_clk_pll_disable(struct clk_hw *hw) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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/* Put the pll is in reset */ |
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meson_parm_write(clk->map, &pll->rst, 1); |
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/* Disable the pll */ |
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meson_parm_write(clk->map, &pll->en, 0); |
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} |
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static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); |
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unsigned int enabled, m, n, frac = 0; |
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unsigned long old_rate; |
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int ret; |
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if (parent_rate == 0 || rate == 0) |
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return -EINVAL; |
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old_rate = clk_hw_get_rate(hw); |
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ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll); |
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if (ret) |
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return ret; |
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enabled = meson_parm_read(clk->map, &pll->en); |
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if (enabled) |
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meson_clk_pll_disable(hw); |
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meson_parm_write(clk->map, &pll->n, n); |
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meson_parm_write(clk->map, &pll->m, m); |
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if (MESON_PARM_APPLICABLE(&pll->frac)) { |
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frac = __pll_params_with_frac(rate, parent_rate, m, n, pll); |
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meson_parm_write(clk->map, &pll->frac, frac); |
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} |
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/* If the pll is stopped, bail out now */ |
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if (!enabled) |
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return 0; |
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ret = meson_clk_pll_enable(hw); |
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if (ret) { |
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pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", |
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__func__, old_rate); |
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/* |
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* FIXME: Do we really need/want this HACK ? |
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* It looks unsafe. what happens if the clock gets into a |
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* broken state and we can't lock back on the old_rate ? Looks |
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* like an infinite recursion is possible |
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*/ |
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meson_clk_pll_set_rate(hw, old_rate, parent_rate); |
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} |
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return ret; |
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} |
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/* |
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* The Meson G12A PCIE PLL is fined tuned to deliver a very precise |
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* 100MHz reference clock for the PCIe Analog PHY, and thus requires |
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* a strict register sequence to enable the PLL. |
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* To simplify, re-use the _init() op to enable the PLL and keep |
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* the other ops except set_rate since the rate is fixed. |
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*/ |
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const struct clk_ops meson_clk_pcie_pll_ops = { |
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.recalc_rate = meson_clk_pll_recalc_rate, |
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.determine_rate = meson_clk_pll_determine_rate, |
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.is_enabled = meson_clk_pll_is_enabled, |
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.enable = meson_clk_pcie_pll_enable, |
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.disable = meson_clk_pll_disable |
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}; |
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EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops); |
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const struct clk_ops meson_clk_pll_ops = { |
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.init = meson_clk_pll_init, |
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.recalc_rate = meson_clk_pll_recalc_rate, |
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.determine_rate = meson_clk_pll_determine_rate, |
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.set_rate = meson_clk_pll_set_rate, |
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.is_enabled = meson_clk_pll_is_enabled, |
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.enable = meson_clk_pll_enable, |
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.disable = meson_clk_pll_disable |
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}; |
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EXPORT_SYMBOL_GPL(meson_clk_pll_ops); |
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const struct clk_ops meson_clk_pll_ro_ops = { |
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.recalc_rate = meson_clk_pll_recalc_rate, |
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.is_enabled = meson_clk_pll_is_enabled, |
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}; |
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EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops); |
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MODULE_DESCRIPTION("Amlogic PLL driver"); |
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MODULE_AUTHOR("Carlo Caione <[email protected]>"); |
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MODULE_AUTHOR("Jerome Brunet <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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