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73 lines
2.2 KiB
73 lines
2.2 KiB
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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/* |
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* Copyright (c) 2019 BayLibre, SAS. |
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* Author: Neil Armstrong <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include "clk-regmap.h" |
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#include "clk-cpu-dyndiv.h" |
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static inline struct meson_clk_cpu_dyndiv_data * |
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meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) |
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{ |
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return (struct meson_clk_cpu_dyndiv_data *)clk->data; |
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} |
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static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, |
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unsigned long prate) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); |
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return divider_recalc_rate(hw, prate, |
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meson_parm_read(clk->map, &data->div), |
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NULL, 0, data->div.width); |
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} |
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static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw, |
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unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); |
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return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); |
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} |
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static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_regmap *clk = to_clk_regmap(hw); |
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struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); |
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unsigned int val; |
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int ret; |
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ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0); |
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if (ret < 0) |
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return ret; |
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val = (unsigned int)ret << data->div.shift; |
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/* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */ |
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meson_parm_write(clk->map, &data->dyn, 1); |
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/* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */ |
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return regmap_update_bits(clk->map, data->div.reg_off, |
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SETPMASK(data->div.width, data->div.shift) | |
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SETPMASK(data->dyn.width, data->dyn.shift), |
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val); |
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}; |
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const struct clk_ops meson_clk_cpu_dyndiv_ops = { |
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.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, |
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.round_rate = meson_clk_cpu_dyndiv_round_rate, |
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.set_rate = meson_clk_cpu_dyndiv_set_rate, |
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}; |
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EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops); |
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MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider"); |
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MODULE_AUTHOR("Neil Armstrong <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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