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293 lines
6.5 KiB
293 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Microchip LAN966x SoC Clock driver. |
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* |
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries |
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* |
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* Author: Kavyasree Kotagiri <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/clock/microchip,lan966x.h> |
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#define GCK_ENA BIT(0) |
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#define GCK_SRC_SEL GENMASK(9, 8) |
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#define GCK_PRESCALER GENMASK(23, 16) |
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#define DIV_MAX 255 |
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static const char *clk_names[N_CLOCKS] = { |
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"qspi0", "qspi1", "qspi2", "sdmmc0", |
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"pi", "mcan0", "mcan1", "flexcom0", |
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"flexcom1", "flexcom2", "flexcom3", |
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"flexcom4", "timer1", "usb_refclk", |
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}; |
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struct lan966x_gck { |
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struct clk_hw hw; |
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void __iomem *reg; |
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}; |
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#define to_lan966x_gck(hw) container_of(hw, struct lan966x_gck, hw) |
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static const struct clk_parent_data lan966x_gck_pdata[] = { |
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{ .fw_name = "cpu", }, |
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{ .fw_name = "ddr", }, |
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{ .fw_name = "sys", }, |
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}; |
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static struct clk_init_data init = { |
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.parent_data = lan966x_gck_pdata, |
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.num_parents = ARRAY_SIZE(lan966x_gck_pdata), |
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}; |
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struct clk_gate_soc_desc { |
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const char *name; |
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int bit_idx; |
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}; |
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static const struct clk_gate_soc_desc clk_gate_desc[] = { |
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{ "uhphs", 11 }, |
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{ "udphs", 10 }, |
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{ "mcramc", 9 }, |
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{ "hmatrix", 8 }, |
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{ } |
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}; |
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static DEFINE_SPINLOCK(clk_gate_lock); |
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static void __iomem *base; |
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static int lan966x_gck_enable(struct clk_hw *hw) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 val = readl(gck->reg); |
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val |= GCK_ENA; |
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writel(val, gck->reg); |
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return 0; |
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} |
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static void lan966x_gck_disable(struct clk_hw *hw) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 val = readl(gck->reg); |
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val &= ~GCK_ENA; |
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writel(val, gck->reg); |
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} |
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static int lan966x_gck_set_rate(struct clk_hw *hw, |
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unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 div, val = readl(gck->reg); |
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if (rate == 0 || parent_rate == 0) |
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return -EINVAL; |
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/* Set Prescalar */ |
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div = parent_rate / rate; |
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val &= ~GCK_PRESCALER; |
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val |= FIELD_PREP(GCK_PRESCALER, (div - 1)); |
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writel(val, gck->reg); |
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return 0; |
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} |
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static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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unsigned int div; |
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if (rate == 0 || *parent_rate == 0) |
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return -EINVAL; |
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if (rate >= *parent_rate) |
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return *parent_rate; |
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div = DIV_ROUND_CLOSEST(*parent_rate, rate); |
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return *parent_rate / div; |
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} |
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static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 div, val = readl(gck->reg); |
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div = FIELD_GET(GCK_PRESCALER, val); |
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return parent_rate / (div + 1); |
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} |
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static int lan966x_gck_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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struct clk_hw *parent; |
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int i; |
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for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { |
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parent = clk_hw_get_parent_by_index(hw, i); |
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if (!parent) |
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continue; |
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/* Allowed prescaler divider range is 0-255 */ |
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if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) { |
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req->best_parent_hw = parent; |
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req->best_parent_rate = clk_hw_get_rate(parent); |
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return 0; |
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} |
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} |
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return -EINVAL; |
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} |
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static u8 lan966x_gck_get_parent(struct clk_hw *hw) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 val = readl(gck->reg); |
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return FIELD_GET(GCK_SRC_SEL, val); |
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} |
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static int lan966x_gck_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct lan966x_gck *gck = to_lan966x_gck(hw); |
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u32 val = readl(gck->reg); |
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val &= ~GCK_SRC_SEL; |
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val |= FIELD_PREP(GCK_SRC_SEL, index); |
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writel(val, gck->reg); |
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return 0; |
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} |
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static const struct clk_ops lan966x_gck_ops = { |
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.enable = lan966x_gck_enable, |
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.disable = lan966x_gck_disable, |
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.set_rate = lan966x_gck_set_rate, |
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.round_rate = lan966x_gck_round_rate, |
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.recalc_rate = lan966x_gck_recalc_rate, |
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.determine_rate = lan966x_gck_determine_rate, |
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.set_parent = lan966x_gck_set_parent, |
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.get_parent = lan966x_gck_get_parent, |
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}; |
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static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i) |
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{ |
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struct lan966x_gck *priv; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return ERR_PTR(-ENOMEM); |
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priv->reg = base + (i * 4); |
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priv->hw.init = &init; |
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ret = devm_clk_hw_register(dev, &priv->hw); |
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if (ret) |
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return ERR_PTR(ret); |
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return &priv->hw; |
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}; |
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static int lan966x_gate_clk_register(struct device *dev, |
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struct clk_hw_onecell_data *hw_data, |
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void __iomem *gate_base) |
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{ |
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int i; |
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for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) { |
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int idx = i - GCK_GATE_UHPHS; |
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hw_data->hws[i] = |
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devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, |
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"lan966x", 0, gate_base, |
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clk_gate_desc[idx].bit_idx, |
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0, &clk_gate_lock); |
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if (IS_ERR(hw_data->hws[i])) |
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return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]), |
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"failed to register %s clock\n", |
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clk_gate_desc[idx].name); |
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} |
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return 0; |
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} |
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static int lan966x_clk_probe(struct platform_device *pdev) |
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{ |
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struct clk_hw_onecell_data *hw_data; |
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struct device *dev = &pdev->dev; |
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void __iomem *gate_base; |
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struct resource *res; |
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int i, ret; |
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hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS), |
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GFP_KERNEL); |
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if (!hw_data) |
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return -ENOMEM; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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init.ops = &lan966x_gck_ops; |
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hw_data->num = GCK_GATE_UHPHS; |
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for (i = 0; i < GCK_GATE_UHPHS; i++) { |
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init.name = clk_names[i]; |
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hw_data->hws[i] = lan966x_gck_clk_register(dev, i); |
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if (IS_ERR(hw_data->hws[i])) { |
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dev_err(dev, "failed to register %s clock\n", |
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init.name); |
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return PTR_ERR(hw_data->hws[i]); |
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} |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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if (res) { |
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gate_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(gate_base)) |
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return PTR_ERR(gate_base); |
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hw_data->num = N_CLOCKS; |
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ret = lan966x_gate_clk_register(dev, hw_data, gate_base); |
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if (ret) |
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return ret; |
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} |
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); |
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} |
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static const struct of_device_id lan966x_clk_dt_ids[] = { |
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{ .compatible = "microchip,lan966x-gck", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); |
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static struct platform_driver lan966x_clk_driver = { |
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.probe = lan966x_clk_probe, |
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.driver = { |
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.name = "lan966x-clk", |
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.of_match_table = lan966x_clk_dt_ids, |
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}, |
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}; |
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module_platform_driver(lan966x_clk_driver); |
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MODULE_AUTHOR("Kavyasree Kotagiri <[email protected]>"); |
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MODULE_DESCRIPTION("LAN966X clock driver"); |
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MODULE_LICENSE("GPL v2");
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