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351 lines
7.9 KiB
351 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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#include <linux/delay.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/clock/en7523-clk.h> |
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#define REG_PCI_CONTROL 0x88 |
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#define REG_PCI_CONTROL_PERSTOUT BIT(29) |
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#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) |
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#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) |
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#define REG_GSW_CLK_DIV_SEL 0x1b4 |
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#define REG_EMI_CLK_DIV_SEL 0x1b8 |
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#define REG_BUS_CLK_DIV_SEL 0x1bc |
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#define REG_SPI_CLK_DIV_SEL 0x1c4 |
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#define REG_SPI_CLK_FREQ_SEL 0x1c8 |
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#define REG_NPU_CLK_DIV_SEL 0x1fc |
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#define REG_CRYPTO_CLKSRC 0x200 |
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#define REG_RESET_CONTROL 0x834 |
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#define REG_RESET_CONTROL_PCIEHB BIT(29) |
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#define REG_RESET_CONTROL_PCIE1 BIT(27) |
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#define REG_RESET_CONTROL_PCIE2 BIT(26) |
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struct en_clk_desc { |
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int id; |
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const char *name; |
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u32 base_reg; |
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u8 base_bits; |
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u8 base_shift; |
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union { |
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const unsigned int *base_values; |
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unsigned int base_value; |
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}; |
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size_t n_base_values; |
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u16 div_reg; |
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u8 div_bits; |
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u8 div_shift; |
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u16 div_val0; |
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u8 div_step; |
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}; |
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struct en_clk_gate { |
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void __iomem *base; |
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struct clk_hw hw; |
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}; |
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static const u32 gsw_base[] = { 400000000, 500000000 }; |
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static const u32 emi_base[] = { 333000000, 400000000 }; |
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static const u32 bus_base[] = { 500000000, 540000000 }; |
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static const u32 slic_base[] = { 100000000, 3125000 }; |
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static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; |
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static const struct en_clk_desc en7523_base_clks[] = { |
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{ |
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.id = EN7523_CLK_GSW, |
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.name = "gsw", |
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.base_reg = REG_GSW_CLK_DIV_SEL, |
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.base_bits = 1, |
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.base_shift = 8, |
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.base_values = gsw_base, |
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.n_base_values = ARRAY_SIZE(gsw_base), |
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.div_bits = 3, |
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.div_shift = 0, |
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.div_step = 1, |
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}, { |
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.id = EN7523_CLK_EMI, |
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.name = "emi", |
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.base_reg = REG_EMI_CLK_DIV_SEL, |
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.base_bits = 1, |
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.base_shift = 8, |
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.base_values = emi_base, |
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.n_base_values = ARRAY_SIZE(emi_base), |
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.div_bits = 3, |
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.div_shift = 0, |
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.div_step = 1, |
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}, { |
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.id = EN7523_CLK_BUS, |
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.name = "bus", |
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.base_reg = REG_BUS_CLK_DIV_SEL, |
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.base_bits = 1, |
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.base_shift = 8, |
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.base_values = bus_base, |
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.n_base_values = ARRAY_SIZE(bus_base), |
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.div_bits = 3, |
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.div_shift = 0, |
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.div_step = 1, |
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}, { |
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.id = EN7523_CLK_SLIC, |
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.name = "slic", |
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.base_reg = REG_SPI_CLK_FREQ_SEL, |
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.base_bits = 1, |
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.base_shift = 0, |
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.base_values = slic_base, |
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.n_base_values = ARRAY_SIZE(slic_base), |
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.div_reg = REG_SPI_CLK_DIV_SEL, |
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.div_bits = 5, |
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.div_shift = 24, |
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.div_val0 = 20, |
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.div_step = 2, |
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}, { |
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.id = EN7523_CLK_SPI, |
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.name = "spi", |
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.base_reg = REG_SPI_CLK_DIV_SEL, |
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.base_value = 400000000, |
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.div_bits = 5, |
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.div_shift = 8, |
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.div_val0 = 40, |
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.div_step = 2, |
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}, { |
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.id = EN7523_CLK_NPU, |
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.name = "npu", |
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.base_reg = REG_NPU_CLK_DIV_SEL, |
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.base_bits = 2, |
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.base_shift = 8, |
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.base_values = npu_base, |
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.n_base_values = ARRAY_SIZE(npu_base), |
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.div_bits = 3, |
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.div_shift = 0, |
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.div_step = 1, |
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}, { |
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.id = EN7523_CLK_CRYPTO, |
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.name = "crypto", |
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.base_reg = REG_CRYPTO_CLKSRC, |
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.base_bits = 1, |
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.base_shift = 8, |
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.base_values = emi_base, |
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.n_base_values = ARRAY_SIZE(emi_base), |
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} |
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}; |
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static const struct of_device_id of_match_clk_en7523[] = { |
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{ .compatible = "airoha,en7523-scu", }, |
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{ /* sentinel */ } |
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}; |
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static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) |
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{ |
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const struct en_clk_desc *desc = &en7523_base_clks[i]; |
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u32 val; |
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if (!desc->base_bits) |
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return desc->base_value; |
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val = readl(base + desc->base_reg); |
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val >>= desc->base_shift; |
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val &= (1 << desc->base_bits) - 1; |
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if (val >= desc->n_base_values) |
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return 0; |
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return desc->base_values[val]; |
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} |
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static u32 en7523_get_div(void __iomem *base, int i) |
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{ |
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const struct en_clk_desc *desc = &en7523_base_clks[i]; |
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u32 reg, val; |
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if (!desc->div_bits) |
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return 1; |
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reg = desc->div_reg ? desc->div_reg : desc->base_reg; |
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val = readl(base + reg); |
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val >>= desc->div_shift; |
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val &= (1 << desc->div_bits) - 1; |
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if (!val && desc->div_val0) |
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return desc->div_val0; |
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return (val + 1) * desc->div_step; |
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} |
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static int en7523_pci_is_enabled(struct clk_hw *hw) |
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{ |
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); |
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return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); |
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} |
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static int en7523_pci_prepare(struct clk_hw *hw) |
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{ |
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); |
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void __iomem *np_base = cg->base; |
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u32 val, mask; |
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/* Need to pull device low before reset */ |
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val = readl(np_base + REG_PCI_CONTROL); |
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val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); |
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writel(val, np_base + REG_PCI_CONTROL); |
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usleep_range(1000, 2000); |
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/* Enable PCIe port 1 */ |
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val |= REG_PCI_CONTROL_REFCLK_EN1; |
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writel(val, np_base + REG_PCI_CONTROL); |
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usleep_range(1000, 2000); |
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/* Reset to default */ |
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val = readl(np_base + REG_RESET_CONTROL); |
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mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | |
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REG_RESET_CONTROL_PCIEHB; |
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writel(val & ~mask, np_base + REG_RESET_CONTROL); |
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usleep_range(1000, 2000); |
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writel(val | mask, np_base + REG_RESET_CONTROL); |
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msleep(100); |
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writel(val & ~mask, np_base + REG_RESET_CONTROL); |
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usleep_range(5000, 10000); |
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/* Release device */ |
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mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; |
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val = readl(np_base + REG_PCI_CONTROL); |
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writel(val & ~mask, np_base + REG_PCI_CONTROL); |
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usleep_range(1000, 2000); |
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writel(val | mask, np_base + REG_PCI_CONTROL); |
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msleep(250); |
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return 0; |
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} |
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static void en7523_pci_unprepare(struct clk_hw *hw) |
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{ |
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struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); |
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void __iomem *np_base = cg->base; |
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u32 val; |
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val = readl(np_base + REG_PCI_CONTROL); |
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val &= ~REG_PCI_CONTROL_REFCLK_EN1; |
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writel(val, np_base + REG_PCI_CONTROL); |
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} |
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static struct clk_hw *en7523_register_pcie_clk(struct device *dev, |
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void __iomem *np_base) |
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{ |
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static const struct clk_ops pcie_gate_ops = { |
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.is_enabled = en7523_pci_is_enabled, |
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.prepare = en7523_pci_prepare, |
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.unprepare = en7523_pci_unprepare, |
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}; |
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struct clk_init_data init = { |
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.name = "pcie", |
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.ops = &pcie_gate_ops, |
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}; |
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struct en_clk_gate *cg; |
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cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); |
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if (!cg) |
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return NULL; |
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cg->base = np_base; |
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cg->hw.init = &init; |
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en7523_pci_unprepare(&cg->hw); |
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if (clk_hw_register(dev, &cg->hw)) |
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return NULL; |
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return &cg->hw; |
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} |
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static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, |
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void __iomem *base, void __iomem *np_base) |
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{ |
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struct clk_hw *hw; |
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u32 rate; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { |
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const struct en_clk_desc *desc = &en7523_base_clks[i]; |
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rate = en7523_get_base_rate(base, i); |
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rate /= en7523_get_div(base, i); |
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hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); |
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if (IS_ERR(hw)) { |
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pr_err("Failed to register clk %s: %ld\n", |
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desc->name, PTR_ERR(hw)); |
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continue; |
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} |
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clk_data->hws[desc->id] = hw; |
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} |
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hw = en7523_register_pcie_clk(dev, np_base); |
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clk_data->hws[EN7523_CLK_PCIE] = hw; |
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clk_data->num = EN7523_NUM_CLOCKS; |
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} |
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static int en7523_clk_probe(struct platform_device *pdev) |
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{ |
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struct device_node *node = pdev->dev.of_node; |
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struct clk_hw_onecell_data *clk_data; |
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void __iomem *base, *np_base; |
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int r; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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np_base = devm_platform_ioremap_resource(pdev, 1); |
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if (IS_ERR(np_base)) |
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return PTR_ERR(np_base); |
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clk_data = devm_kzalloc(&pdev->dev, |
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struct_size(clk_data, hws, EN7523_NUM_CLOCKS), |
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GFP_KERNEL); |
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if (!clk_data) |
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return -ENOMEM; |
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en7523_register_clocks(&pdev->dev, clk_data, base, np_base); |
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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return r; |
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} |
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static struct platform_driver clk_en7523_drv = { |
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.probe = en7523_clk_probe, |
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.driver = { |
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.name = "clk-en7523", |
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.of_match_table = of_match_clk_en7523, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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static int __init clk_en7523_init(void) |
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{ |
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return platform_driver_register(&clk_en7523_drv); |
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} |
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arch_initcall(clk_en7523_init);
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