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216 lines
5.4 KiB
216 lines
5.4 KiB
/* |
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* TX4939 irq routines |
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* Based on linux/arch/mips/kernel/irq_txx9.c, |
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* and RBTX49xx patch from CELF patch archive. |
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* |
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* Copyright 2001, 2003-2005 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. |
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* [email protected] |
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* [email protected] |
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* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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*/ |
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/* |
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* TX4939 defines 64 IRQs. |
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* Similer to irq_txx9.c but different register layouts. |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/types.h> |
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#include <asm/irq_cpu.h> |
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#include <asm/txx9irq.h> |
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#include <asm/txx9/tx4939.h> |
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/* IRCER : Int. Control Enable */ |
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#define TXx9_IRCER_ICE 0x00000001 |
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/* IRCR : Int. Control */ |
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#define TXx9_IRCR_LOW 0x00000000 |
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#define TXx9_IRCR_HIGH 0x00000001 |
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#define TXx9_IRCR_DOWN 0x00000002 |
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#define TXx9_IRCR_UP 0x00000003 |
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#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002) |
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/* IRSCR : Int. Status Control */ |
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#define TXx9_IRSCR_EIClrE 0x00000100 |
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#define TXx9_IRSCR_EIClr_MASK 0x0000000f |
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/* IRCSR : Int. Current Status */ |
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#define TXx9_IRCSR_IF 0x00010000 |
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#define irc_dlevel 0 |
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#define irc_elevel 1 |
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static struct { |
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unsigned char level; |
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unsigned char mode; |
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} tx4939irq[TX4939_NUM_IR] __read_mostly; |
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static void tx4939_irq_unmask(struct irq_data *d) |
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{ |
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unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; |
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u32 __iomem *lvlp; |
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int ofs; |
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if (irq_nr < 32) { |
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irq_nr--; |
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lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r; |
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} else { |
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irq_nr -= 32; |
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lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r; |
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} |
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ofs = (irq_nr & 16) + (irq_nr & 1) * 8; |
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__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) |
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| (tx4939irq[irq_nr].level << ofs), |
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lvlp); |
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} |
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static inline void tx4939_irq_mask(struct irq_data *d) |
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{ |
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unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; |
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u32 __iomem *lvlp; |
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int ofs; |
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if (irq_nr < 32) { |
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irq_nr--; |
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lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r; |
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} else { |
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irq_nr -= 32; |
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lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r; |
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} |
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ofs = (irq_nr & 16) + (irq_nr & 1) * 8; |
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__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) |
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| (irc_dlevel << ofs), |
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lvlp); |
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mmiowb(); |
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} |
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static void tx4939_irq_mask_ack(struct irq_data *d) |
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{ |
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unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; |
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tx4939_irq_mask(d); |
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if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) { |
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irq_nr--; |
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/* clear edge detection */ |
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__raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf)) |
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<< (irq_nr & 0x10), |
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&tx4939_ircptr->edc.r); |
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} |
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} |
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static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; |
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u32 cr; |
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u32 __iomem *crp; |
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int ofs; |
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int mode; |
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if (flow_type & IRQF_TRIGGER_PROBE) |
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return 0; |
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switch (flow_type & IRQF_TRIGGER_MASK) { |
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case IRQF_TRIGGER_RISING: |
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mode = TXx9_IRCR_UP; |
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break; |
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case IRQF_TRIGGER_FALLING: |
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mode = TXx9_IRCR_DOWN; |
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break; |
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case IRQF_TRIGGER_HIGH: |
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mode = TXx9_IRCR_HIGH; |
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break; |
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case IRQF_TRIGGER_LOW: |
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mode = TXx9_IRCR_LOW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (irq_nr < 32) { |
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irq_nr--; |
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crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r; |
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} else { |
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irq_nr -= 32; |
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crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r; |
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} |
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ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2; |
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cr = __raw_readl(crp); |
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cr &= ~(0x3 << ofs); |
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cr |= (mode & 0x3) << ofs; |
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__raw_writel(cr, crp); |
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tx4939irq[irq_nr].mode = mode; |
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return 0; |
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} |
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static struct irq_chip tx4939_irq_chip = { |
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.name = "TX4939", |
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.irq_ack = tx4939_irq_mask_ack, |
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.irq_mask = tx4939_irq_mask, |
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.irq_mask_ack = tx4939_irq_mask_ack, |
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.irq_unmask = tx4939_irq_unmask, |
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.irq_set_type = tx4939_irq_set_type, |
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}; |
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static int tx4939_irq_set_pri(int irc_irq, int new_pri) |
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{ |
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int old_pri; |
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if ((unsigned int)irc_irq >= TX4939_NUM_IR) |
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return 0; |
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old_pri = tx4939irq[irc_irq].level; |
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tx4939irq[irc_irq].level = new_pri; |
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return old_pri; |
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} |
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void __init tx4939_irq_init(void) |
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{ |
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int i; |
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mips_cpu_irq_init(); |
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/* disable interrupt control */ |
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__raw_writel(0, &tx4939_ircptr->den.r); |
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__raw_writel(0, &tx4939_ircptr->maskint.r); |
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__raw_writel(0, &tx4939_ircptr->maskext.r); |
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/* irq_base + 0 is not used */ |
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for (i = 1; i < TX4939_NUM_IR; i++) { |
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tx4939irq[i].level = 4; /* middle level */ |
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tx4939irq[i].mode = TXx9_IRCR_LOW; |
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irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, |
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handle_level_irq); |
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} |
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/* mask all IRC interrupts */ |
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__raw_writel(0, &tx4939_ircptr->msk.r); |
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for (i = 0; i < 16; i++) |
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__raw_writel(0, &tx4939_ircptr->lvl[i].r); |
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/* setup IRC interrupt mode (Low Active) */ |
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for (i = 0; i < 2; i++) |
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__raw_writel(0, &tx4939_ircptr->dm[i].r); |
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for (i = 0; i < 2; i++) |
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__raw_writel(0, &tx4939_ircptr->dm2[i].r); |
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/* enable interrupt control */ |
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__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); |
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__raw_writel(irc_elevel, &tx4939_ircptr->msk.r); |
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, |
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handle_simple_irq); |
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/* raise priority for errors, timers, sio */ |
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tx4939_irq_set_pri(TX4939_IR_WTOERR, 7); |
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tx4939_irq_set_pri(TX4939_IR_PCIERR, 7); |
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tx4939_irq_set_pri(TX4939_IR_PCIPME, 7); |
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for (i = 0; i < TX4939_NUM_IR_TMR; i++) |
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tx4939_irq_set_pri(TX4939_IR_TMR(i), 6); |
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for (i = 0; i < TX4939_NUM_IR_SIO; i++) |
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tx4939_irq_set_pri(TX4939_IR_SIO(i), 5); |
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} |
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int tx4939_irq(void) |
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{ |
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u32 csr = __raw_readl(&tx4939_ircptr->cs.r); |
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if (likely(!(csr & TXx9_IRCSR_IF))) |
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return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1)); |
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return -1; |
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}
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