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201 lines
5.1 KiB
201 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* |
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* Parts of this file are based on Ralink's 2.6.21 BSP |
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* |
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* Copyright (C) 2008-2011 Gabor Juhos <[email protected]> |
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* Copyright (C) 2008 Imre Kaloz <[email protected]> |
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* Copyright (C) 2013 John Crispin <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/bug.h> |
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#include <asm/io.h> |
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#include <asm/mipsregs.h> |
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#include <asm/mach-ralink/ralink_regs.h> |
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#include <asm/mach-ralink/rt305x.h> |
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#include "common.h" |
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static unsigned long rt5350_get_mem_size(void) |
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{ |
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); |
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unsigned long ret; |
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u32 t; |
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t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); |
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t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & |
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RT5350_SYSCFG0_DRAM_SIZE_MASK; |
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switch (t) { |
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case RT5350_SYSCFG0_DRAM_SIZE_2M: |
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ret = 2; |
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break; |
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case RT5350_SYSCFG0_DRAM_SIZE_8M: |
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ret = 8; |
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break; |
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case RT5350_SYSCFG0_DRAM_SIZE_16M: |
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ret = 16; |
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break; |
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case RT5350_SYSCFG0_DRAM_SIZE_32M: |
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ret = 32; |
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break; |
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case RT5350_SYSCFG0_DRAM_SIZE_64M: |
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ret = 64; |
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break; |
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default: |
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panic("rt5350: invalid DRAM size: %u", t); |
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break; |
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} |
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return ret; |
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} |
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void __init ralink_clk_init(void) |
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{ |
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; |
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unsigned long wmac_rate = 40000000; |
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); |
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if (soc_is_rt305x() || soc_is_rt3350()) { |
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t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & |
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RT305X_SYSCFG_CPUCLK_MASK; |
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switch (t) { |
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case RT305X_SYSCFG_CPUCLK_LOW: |
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cpu_rate = 320000000; |
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break; |
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case RT305X_SYSCFG_CPUCLK_HIGH: |
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cpu_rate = 384000000; |
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break; |
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} |
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sys_rate = uart_rate = wdt_rate = cpu_rate / 3; |
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} else if (soc_is_rt3352()) { |
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t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & |
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RT3352_SYSCFG0_CPUCLK_MASK; |
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switch (t) { |
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case RT3352_SYSCFG0_CPUCLK_LOW: |
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cpu_rate = 384000000; |
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break; |
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case RT3352_SYSCFG0_CPUCLK_HIGH: |
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cpu_rate = 400000000; |
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break; |
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} |
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sys_rate = wdt_rate = cpu_rate / 3; |
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uart_rate = 40000000; |
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} else if (soc_is_rt5350()) { |
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t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & |
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RT5350_SYSCFG0_CPUCLK_MASK; |
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switch (t) { |
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case RT5350_SYSCFG0_CPUCLK_360: |
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cpu_rate = 360000000; |
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sys_rate = cpu_rate / 3; |
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break; |
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case RT5350_SYSCFG0_CPUCLK_320: |
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cpu_rate = 320000000; |
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sys_rate = cpu_rate / 4; |
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break; |
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case RT5350_SYSCFG0_CPUCLK_300: |
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cpu_rate = 300000000; |
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sys_rate = cpu_rate / 3; |
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break; |
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default: |
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BUG(); |
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} |
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uart_rate = 40000000; |
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wdt_rate = sys_rate; |
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} else { |
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BUG(); |
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} |
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if (soc_is_rt3352() || soc_is_rt5350()) { |
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u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); |
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if (!(val & RT3352_CLKCFG0_XTAL_SEL)) |
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wmac_rate = 20000000; |
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} |
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ralink_clk_add("cpu", cpu_rate); |
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ralink_clk_add("sys", sys_rate); |
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ralink_clk_add("10000900.i2c", uart_rate); |
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ralink_clk_add("10000a00.i2s", uart_rate); |
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ralink_clk_add("10000b00.spi", sys_rate); |
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ralink_clk_add("10000b40.spi", sys_rate); |
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ralink_clk_add("10000100.timer", wdt_rate); |
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ralink_clk_add("10000120.watchdog", wdt_rate); |
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ralink_clk_add("10000500.uart", uart_rate); |
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ralink_clk_add("10000c00.uartlite", uart_rate); |
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ralink_clk_add("10100000.ethernet", sys_rate); |
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ralink_clk_add("10180000.wmac", wmac_rate); |
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} |
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void __init ralink_of_remap(void) |
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{ |
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rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); |
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rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); |
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if (!rt_sysc_membase || !rt_memc_membase) |
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panic("Failed to remap core resources"); |
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} |
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void __init prom_soc_init(struct ralink_soc_info *soc_info) |
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{ |
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); |
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unsigned char *name; |
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u32 n0; |
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u32 n1; |
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u32 id; |
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); |
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); |
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if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { |
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unsigned long icache_sets; |
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icache_sets = (read_c0_config1() >> 22) & 7; |
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if (icache_sets == 1) { |
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ralink_soc = RT305X_SOC_RT3050; |
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name = "RT3050"; |
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soc_info->compatible = "ralink,rt3050-soc"; |
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} else { |
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ralink_soc = RT305X_SOC_RT3052; |
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name = "RT3052"; |
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soc_info->compatible = "ralink,rt3052-soc"; |
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} |
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} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { |
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ralink_soc = RT305X_SOC_RT3350; |
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name = "RT3350"; |
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soc_info->compatible = "ralink,rt3350-soc"; |
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} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { |
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ralink_soc = RT305X_SOC_RT3352; |
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name = "RT3352"; |
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soc_info->compatible = "ralink,rt3352-soc"; |
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} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { |
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ralink_soc = RT305X_SOC_RT5350; |
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name = "RT5350"; |
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soc_info->compatible = "ralink,rt5350-soc"; |
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} else { |
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panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); |
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} |
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id = __raw_readl(sysc + SYSC_REG_CHIP_ID); |
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, |
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"Ralink %s id:%u rev:%u", |
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name, |
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, |
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(id & CHIP_ID_REV_MASK)); |
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soc_info->mem_base = RT305X_SDRAM_BASE; |
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if (soc_is_rt5350()) { |
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soc_info->mem_size = rt5350_get_mem_size(); |
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} else if (soc_is_rt305x() || soc_is_rt3350()) { |
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soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; |
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soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; |
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} else if (soc_is_rt3352()) { |
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soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; |
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soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; |
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} |
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}
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