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118 lines
3.0 KiB
118 lines
3.0 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) |
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maintainers: |
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- Andy Gross <[email protected]> |
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- Bjorn Andersson <[email protected]> |
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- Krzysztof Kozlowski <[email protected]> |
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description: |
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The QUP v3 core is a GENI based AHB slave that provides a common data path |
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(an output FIFO and an input FIFO) for serial peripheral interface (SPI) |
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mini-core. |
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SPI in master mode supports up to 50MHz, up to four chip selects, |
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programmable data path from 4 bits to 32 bits and numerous protocol variants. |
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SPI Controller nodes must be child of GENI based Qualcomm Universal |
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Peripharal. Please refer GENI based QUP wrapper controller node bindings |
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described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. |
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allOf: |
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- $ref: /schemas/spi/spi-controller.yaml# |
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properties: |
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compatible: |
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const: qcom,geni-spi |
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clocks: |
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maxItems: 1 |
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clock-names: |
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const: se |
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dmas: |
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maxItems: 2 |
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dma-names: |
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items: |
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- const: tx |
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- const: rx |
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interconnects: |
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minItems: 2 |
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maxItems: 3 |
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interconnect-names: |
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minItems: 2 |
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items: |
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- const: qup-core |
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- const: qup-config |
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- const: qup-memory |
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interrupts: |
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maxItems: 1 |
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operating-points-v2: true |
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power-domains: |
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maxItems: 1 |
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reg: |
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maxItems: 1 |
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required: |
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- compatible |
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- clocks |
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- clock-names |
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- interrupts |
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- reg |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/qcom,gcc-sc7180.h> |
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#include <dt-bindings/interconnect/qcom,sc7180.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/qcom-rpmpd.h> |
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spi@880000 { |
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compatible = "qcom,geni-spi"; |
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reg = <0x00880000 0x4000>; |
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clock-names = "se"; |
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&qup_spi0_default>; |
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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power-domains = <&rpmhpd SC7180_CX>; |
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operating-points-v2 = <&qup_opp_table>; |
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, |
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; |
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interconnect-names = "qup-core", "qup-config"; |
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}; |
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- | |
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#include <dt-bindings/dma/qcom-gpi.h> |
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spi@884000 { |
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compatible = "qcom,geni-spi"; |
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reg = <0x00884000 0x4000>; |
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clock-names = "se"; |
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
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dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, |
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<&gpi_dma0 1 1 QCOM_GPI_SPI>; |
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dma-names = "tx", "rx"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&qup_spi1_default>; |
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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};
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