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105 lines
2.4 KiB
105 lines
2.4 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings |
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maintainers: |
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- Laurent Pinchart <[email protected]> |
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description: | |
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This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The |
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GTR provides four lanes and is used by USB, SATA, PCIE, Display port and |
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Ethernet SGMII controllers. |
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properties: |
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"#phy-cells": |
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const: 4 |
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description: | |
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The cells contain the following arguments. |
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- description: The GTR lane |
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minimum: 0 |
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maximum: 3 |
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- description: The PHY type |
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enum: |
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- PHY_TYPE_DP |
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- PHY_TYPE_PCIE |
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- PHY_TYPE_SATA |
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- PHY_TYPE_SGMII |
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- PHY_TYPE_USB3 |
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- description: The PHY instance |
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minimum: 0 |
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maximum: 1 # for DP, SATA or USB |
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maximum: 3 # for PCIE or SGMII |
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- description: The reference clock number |
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minimum: 0 |
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maximum: 3 |
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compatible: |
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enum: |
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- xlnx,zynqmp-psgtr-v1.1 |
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- xlnx,zynqmp-psgtr |
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clocks: |
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minItems: 1 |
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maxItems: 4 |
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description: | |
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Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected |
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inputs shall not have an entry. |
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clock-names: |
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minItems: 1 |
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maxItems: 4 |
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items: |
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pattern: "^ref[0-3]$" |
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reg: |
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items: |
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- description: SERDES registers block |
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- description: SIOU registers block |
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reg-names: |
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items: |
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- const: serdes |
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- const: siou |
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xlnx,tx-termination-fix: |
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description: | |
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Include this for fixing functional issue with the TX termination |
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resistance in GT, which can be out of spec for the XCZU9EG silicon |
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version. |
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type: boolean |
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required: |
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- "#phy-cells" |
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- compatible |
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- reg |
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- reg-names |
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if: |
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properties: |
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compatible: |
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const: xlnx,zynqmp-psgtr-v1.1 |
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then: |
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properties: |
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xlnx,tx-termination-fix: false |
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additionalProperties: false |
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examples: |
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- | |
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phy: phy@fd400000 { |
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compatible = "xlnx,zynqmp-psgtr-v1.1"; |
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reg = <0xfd400000 0x40000>, |
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<0xfd3d0000 0x1000>; |
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reg-names = "serdes", "siou"; |
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clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>; |
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clock-names = "ref1", "ref2", "ref3"; |
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#phy-cells = <4>; |
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}; |
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...
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