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104 lines
3.2 KiB
104 lines
3.2 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: CPSW Port's Interface Mode Selection PHY Tree Bindings |
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maintainers: |
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- Kishon Vijay Abraham I <[email protected]> |
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description: | |
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TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports |
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two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. |
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The interface mode is selected by configuring the MII mode selection register(s) |
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(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and |
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bit fields placement in SCM are different between SoCs while fields meaning |
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is the same. |
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+--------------+ |
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+-------------------------------+ |SCM | |
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| CPSW | | +---------+ | |
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| +--------------------------------+gmii_sel | | |
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| | | | +---------+ | |
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| +----v---+ +--------+ | +--------------+ |
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| |Port 1..<--+-->GMII/MII<-------> |
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| | | | | | | |
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| +--------+ | +--------+ | |
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| | | |
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| | +--------+ | |
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| | | RMII <-------> |
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| +--> | | |
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| | +--------+ | |
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| | | |
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| | +--------+ | |
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| | | RGMII <-------> |
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| +--> | | |
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| +--------+ | |
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+-------------------------------+ |
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CPSW Port's Interface Mode Selection PHY describes MII interface mode between |
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CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration. |
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CPSW Port's Interface Mode Selection PHY device should defined as child device |
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of SCM node (scm_conf) and can be attached to each CPSW port node using standard |
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PHY bindings. |
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properties: |
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compatible: |
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enum: |
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- ti,am3352-phy-gmii-sel |
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- ti,dra7xx-phy-gmii-sel |
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- ti,am43xx-phy-gmii-sel |
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- ti,dm814-phy-gmii-sel |
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- ti,am654-phy-gmii-sel |
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reg: |
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maxItems: 1 |
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'#phy-cells': true |
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allOf: |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- ti,dra7xx-phy-gmii-sel |
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- ti,dm814-phy-gmii-sel |
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- ti,am654-phy-gmii-sel |
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then: |
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properties: |
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'#phy-cells': |
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const: 1 |
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description: CPSW port number (starting from 1) |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- ti,am3352-phy-gmii-sel |
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- ti,am43xx-phy-gmii-sel |
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then: |
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properties: |
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'#phy-cells': |
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const: 2 |
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description: | |
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- CPSW port number (starting from 1) |
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- RMII refclk mode |
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required: |
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- compatible |
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- reg |
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- '#phy-cells' |
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additionalProperties: false |
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examples: |
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- | |
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phy_gmii_sel: phy-gmii-sel@650 { |
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compatible = "ti,am3352-phy-gmii-sel"; |
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reg = <0x650 0x4>; |
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#phy-cells = <2>; |
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};
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