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42 lines
1.1 KiB
42 lines
1.1 KiB
Qualcomm PCIe2 PHY controller |
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The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm |
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platforms. |
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Required properties: |
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- compatible: compatible list, should be: |
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"qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" |
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- reg: offset and length of the PHY register set. |
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- #phy-cells: must be 0. |
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- clocks: a clock-specifier pair for the "pipe" clock |
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- vdda-vp-supply: phandle to low voltage regulator |
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- vdda-vph-supply: phandle to high voltage regulator |
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- resets: reset-specifier pairs for the "phy" and "pipe" resets |
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- reset-names: list of resets, should contain: |
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"phy" and "pipe" |
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- clock-output-names: name of the outgoing clock signal from the PHY PLL |
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- #clock-cells: must be 0 |
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Example: |
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phy@7786000 { |
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compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; |
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reg = <0x07786000 0xb8>; |
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
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resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, |
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<&gcc GCC_PCIE_0_PIPE_ARES>; |
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reset-names = "phy", "pipe"; |
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vdda-vp-supply = <&vreg_l3_1p05>; |
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vdda-vph-supply = <&vreg_l5_1p8>; |
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clock-output-names = "pcie_0_pipe_clk"; |
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#clock-cells = <0>; |
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#phy-cells = <0>; |
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};
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