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61 lines
1.7 KiB
61 lines
1.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Mixel LVDS PHY for Freescale i.MX8qm SoC |
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maintainers: |
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- Liu Ying <[email protected]> |
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description: | |
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The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC. |
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It converts two groups of four 7/10 bits of CMOS data into two |
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groups of four data lanes of LVDS data streams. A phase-locked |
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transmit clock is transmitted in parallel with each group of |
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data streams over a fifth LVDS link. Every cycle of the transmit |
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clock, 56/80 bits of input data are sampled and transmitted |
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through the two groups of LVDS data streams. Together with the |
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transmit clocks, the two groups of LVDS data streams form two |
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LVDS channels. |
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The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled |
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by Control and Status Registers(CSR) module in the SoC. The CSR |
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module, as a system controller, contains the PHY's registers. |
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properties: |
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compatible: |
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enum: |
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- fsl,imx8qm-lvds-phy |
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- mixel,28fdsoi-lvds-1250-8ch-tx-pll |
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"#phy-cells": |
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const: 1 |
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description: | |
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Cell allows setting the LVDS channel index of the PHY. |
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Index 0 is for LVDS channel0 and index 1 is for LVDS channel1. |
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clocks: |
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maxItems: 1 |
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power-domains: |
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maxItems: 1 |
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required: |
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- compatible |
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- "#phy-cells" |
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- clocks |
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- power-domains |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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phy { |
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compatible = "fsl,imx8qm-lvds-phy"; |
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#phy-cells = <1>; |
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; |
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power-domains = <&pd IMX_SC_R_LVDS_0>; |
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};
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