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234 lines
7.1 KiB
234 lines
7.1 KiB
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Broadcom STB NAND Controller |
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maintainers: |
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- Brian Norris <[email protected]> |
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- Kamal Dasu <[email protected]> |
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description: | |
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The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND |
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flash chips. It has a memory-mapped register interface for both control |
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registers and for its data input/output buffer. On some SoCs, this controller |
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is paired with a custom DMA engine (inventively named "Flash DMA") which |
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supports basic PROGRAM and READ functions, among other features. |
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This controller was originally designed for STB SoCs (BCM7xxx) but is now |
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available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and |
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iProc/Cygnus. Its history includes several similar (but not fully register |
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compatible) versions. |
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|
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-- Additional SoC-specific NAND controller properties -- |
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The NAND controller is integrated differently on the variety of SoCs on which |
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it is found. Part of this integration involves providing status and enable |
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bits with which to control the 8 exposed NAND interrupts, as well as hardware |
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for configuring the endianness of the data bus. On some SoCs, these features |
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are handled via standard, modular components (e.g., their interrupts look like |
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a normal IRQ chip), but on others, they are controlled in unique and |
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interesting ways, sometimes with registers that lump multiple NAND-related |
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functions together. The former case can be described simply by the standard |
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interrupts properties in the main controller node. But for the latter |
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exceptional cases, we define additional 'compatible' properties and associated |
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register resources within the NAND controller node above. |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- brcm,brcmnand-v2.1 |
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- brcm,brcmnand-v2.2 |
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- brcm,brcmnand-v4.0 |
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- brcm,brcmnand-v5.0 |
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- brcm,brcmnand-v6.0 |
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- brcm,brcmnand-v6.1 |
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- brcm,brcmnand-v6.2 |
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- brcm,brcmnand-v7.0 |
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- brcm,brcmnand-v7.1 |
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- brcm,brcmnand-v7.2 |
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- brcm,brcmnand-v7.3 |
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- const: brcm,brcmnand |
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- description: BCM63138 SoC-specific NAND controller |
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items: |
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- const: brcm,nand-bcm63138 |
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- enum: |
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- brcm,brcmnand-v7.0 |
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- brcm,brcmnand-v7.1 |
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- const: brcm,brcmnand |
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- description: iProc SoC-specific NAND controller |
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items: |
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- const: brcm,nand-iproc |
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- const: brcm,brcmnand-v6.1 |
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- const: brcm,brcmnand |
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- description: BCM63168 SoC-specific NAND controller |
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items: |
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- const: brcm,nand-bcm63168 |
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- const: brcm,nand-bcm6368 |
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- const: brcm,brcmnand-v4.0 |
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- const: brcm,brcmnand |
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reg: |
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minItems: 1 |
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maxItems: 6 |
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reg-names: |
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minItems: 1 |
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maxItems: 6 |
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items: |
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enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ] |
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interrupts: |
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minItems: 1 |
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items: |
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- description: NAND CTLRDY interrupt |
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- description: FLASH_DMA_DONE if flash DMA is available |
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- description: FLASH_EDU_DONE if EDU is available |
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interrupt-names: |
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minItems: 1 |
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items: |
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- const: nand_ctlrdy |
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- const: flash_dma_done |
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- const: flash_edu_done |
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clocks: |
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maxItems: 1 |
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description: reference to the clock for the NAND controller |
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clock-names: |
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const: nand |
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brcm,nand-has-wp: |
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description: > |
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Some versions of this IP include a write-protect |
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(WP) control bit. It is always available on >= |
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v7.0. Use this property to describe the rare |
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earlier versions of this core that include WP |
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type: boolean |
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patternProperties: |
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"^nand@[a-f0-9]$": |
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type: object |
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properties: |
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compatible: |
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const: brcm,nandcs |
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nand-ecc-step-size: |
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enum: [ 512, 1024 ] |
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brcm,nand-oob-sector-size: |
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description: | |
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integer, to denote the spare area sector size |
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expected for the ECC layout in use. This size, in |
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addition to the strength and step-size, |
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determines how the hardware BCH engine will lay |
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out the parity bytes it stores on the flash. |
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This property can be automatically determined by |
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the flash geometry (particularly the NAND page |
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and OOB size) in many cases, but when booting |
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from NAND, the boot controller has only a limited |
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number of available options for its default ECC |
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layout. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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allOf: |
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- $ref: nand-controller.yaml# |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: brcm,nand-bcm63138 |
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then: |
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properties: |
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reg-names: |
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items: |
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- const: nand |
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- const: nand-int-base |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: brcm,nand-bcm6368 |
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then: |
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properties: |
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reg-names: |
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items: |
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- const: nand |
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- const: nand-int-base |
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- const: nand-cache |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: brcm,nand-iproc |
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then: |
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properties: |
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reg-names: |
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items: |
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- const: nand |
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- const: iproc-idm |
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- const: iproc-ext |
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unevaluatedProperties: false |
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required: |
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- reg |
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- reg-names |
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- interrupts |
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examples: |
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- | |
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nand-controller@f0442800 { |
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compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; |
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reg = <0xf0442800 0x600>, |
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<0xf0443000 0x100>; |
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reg-names = "nand", "flash-dma"; |
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interrupt-parent = <&hif_intr2_intc>; |
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interrupts = <24>, <4>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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nand@1 { |
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compatible = "brcm,nandcs"; |
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reg = <1>; // Chip select 1 |
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nand-on-flash-bbt; |
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nand-ecc-strength = <12>; |
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nand-ecc-step-size = <512>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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}; |
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- | |
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nand-controller@10000200 { |
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compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", |
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"brcm,brcmnand-v4.0", "brcm,brcmnand"; |
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reg = <0x10000200 0x180>, |
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<0x100000b0 0x10>, |
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<0x10000600 0x200>; |
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reg-names = "nand", "nand-int-base", "nand-cache"; |
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interrupt-parent = <&periph_intc>; |
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interrupts = <50>; |
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clocks = <&periph_clk 20>; |
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clock-names = "nand"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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nand@0 { |
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compatible = "brcm,nandcs"; |
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reg = <0>; |
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nand-on-flash-bbt; |
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nand-ecc-strength = <1>; |
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nand-ecc-step-size = <512>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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};
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