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39 lines
1.4 KiB
39 lines
1.4 KiB
Amlogic SD / eMMC controller for S905/GXBB family SoCs |
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The MMC 5.1 compliant host controller on Amlogic provides the |
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interface for SD, eMMC and SDIO devices. |
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This file documents the properties in addition to those available in |
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the MMC core bindings, documented by mmc.txt. |
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Required properties: |
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- compatible : contains one of: |
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- "amlogic,meson-gx-mmc" |
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- "amlogic,meson-gxbb-mmc" |
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- "amlogic,meson-gxl-mmc" |
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- "amlogic,meson-gxm-mmc" |
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- "amlogic,meson-axg-mmc" |
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- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. |
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- clock-names: Should contain the following: |
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"core" - Main peripheral bus clock |
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"clkin0" - Parent clock of internal mux |
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"clkin1" - Other parent clock of internal mux |
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The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the |
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clock rate requested by the MMC core. |
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- resets : phandle of the internal reset line |
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Optional properties: |
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- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the |
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DRAM memory, like on the G12A dedicated SDIO controller. |
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Example: |
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sd_emmc_a: mmc@70000 { |
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compatible = "amlogic,meson-gxbb-mmc"; |
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reg = <0x0 0x70000 0x0 0x2000>; |
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interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; |
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clock-names = "core", "clkin0", "clkin1"; |
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pinctrl-0 = <&emmc_pins>; |
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resets = <&reset RESET_SD_EMMC_A>; |
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};
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