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52 lines
2.4 KiB
52 lines
2.4 KiB
RISC-V Hart-Level Interrupt Controller (HLIC) |
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RISC-V cores include Control Status Registers (CSRs) which are local to each |
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CPU core (HART in RISC-V terminology) and can be read or written by software. |
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Some of these CSRs are used to control local interrupts connected to the core. |
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Every interrupt is ultimately routed through a hart's HLIC before it |
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interrupts that hart. |
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The RISC-V supervisor ISA manual specifies three interrupt sources that are |
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attached to every HLIC: software interrupts, the timer interrupt, and external |
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interrupts. Software interrupts are used to send IPIs between cores. The |
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timer interrupt comes from an architecturally mandated real-time timer that is |
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controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External |
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interrupts connect all other device interrupts to the HLIC, which are routed |
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via the platform-level interrupt controller (PLIC). |
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All RISC-V systems that conform to the supervisor ISA specification are |
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required to have a HLIC with these three interrupt sources present. Since the |
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interrupt map is defined by the ISA it's not listed in the HLIC's device tree |
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entry, though external interrupt controllers (like the PLIC, for example) will |
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need to define how their interrupts map to the relevant HLICs. This means |
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a PLIC interrupt property will typically list the HLICs for all present HARTs |
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in the system. |
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Required properties: |
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- compatible : "riscv,cpu-intc" |
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- #interrupt-cells : should be <1>. The interrupt sources are defined by the |
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RISC-V supervisor ISA manual, with only the following three interrupts being |
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defined for supervisor mode: |
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- Source 1 is the supervisor software interrupt, which can be sent by an SBI |
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call and is reserved for use by software. |
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- Source 5 is the supervisor timer interrupt, which can be configured by |
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SBI calls and implements a one-shot timer. |
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- Source 9 is the supervisor external interrupt, which chains to all other |
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device interrupts. |
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- interrupt-controller : Identifies the node as an interrupt controller |
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Furthermore, this interrupt-controller MUST be embedded inside the cpu |
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definition of the hart whose CSRs control these local interrupts. |
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An example device tree entry for a HLIC is show below. |
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cpu1: cpu@1 { |
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compatible = "riscv"; |
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... |
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cpu1-intc: interrupt-controller { |
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#interrupt-cells = <1>; |
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compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; |
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interrupt-controller; |
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}; |
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};
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