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58 lines
1.7 KiB
58 lines
1.7 KiB
* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers |
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Required properties: |
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- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". |
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- reg: should contain IC registers location and length. |
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- interrupt-controller: identifies the node as an interrupt controller. |
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- #interrupt-cells: the number of cells to define an interrupt, should be 2. |
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The first cell is the IRQ number, the second cell is used to specify |
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one of the supported IRQ types: |
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IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, |
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IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, |
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IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, |
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IRQ_TYPE_LEVEL_LOW = active low level-sensitive. |
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Reset value is IRQ_TYPE_LEVEL_LOW. |
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Optional properties: |
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- interrupts: empty for MIC interrupt controller, cascaded MIC |
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hardware interrupts for SIC1 and SIC2 |
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Examples: |
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/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ |
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mic: interrupt-controller@40008000 { |
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compatible = "nxp,lpc3220-mic"; |
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reg = <0x40008000 0x4000>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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sic1: interrupt-controller@4000c000 { |
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compatible = "nxp,lpc3220-sic"; |
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reg = <0x4000c000 0x4000>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&mic>; |
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>, |
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<30 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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sic2: interrupt-controller@40010000 { |
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compatible = "nxp,lpc3220-sic"; |
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reg = <0x40010000 0x4000>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&mic>; |
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>, |
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<31 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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/* ADC */ |
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adc@40048000 { |
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compatible = "nxp,lpc3220-adc"; |
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reg = <0x40048000 0x1000>; |
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interrupt-parent = <&sic1>; |
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
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};
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