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243 lines
6.8 KiB
243 lines
6.8 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: ARM Generic Interrupt Controller v1 and v2 |
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maintainers: |
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- Marc Zyngier <[email protected]> |
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description: |+ |
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ARM SMP cores are often associated with a GIC, providing per processor |
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interrupts (PPI), shared processor interrupts (SPI) and software |
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generated interrupts (SGI). |
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Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. |
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Secondary GICs are cascaded into the upward interrupt controller and do not |
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have PPIs or SGIs. |
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allOf: |
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- $ref: /schemas/interrupt-controller.yaml# |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- arm,arm11mp-gic |
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- arm,cortex-a15-gic |
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- arm,cortex-a7-gic |
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- arm,cortex-a5-gic |
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- arm,cortex-a9-gic |
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- arm,eb11mp-gic |
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- arm,gic-400 |
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- arm,pl390 |
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- arm,tc11mp-gic |
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- qcom,msm-8660-qgic |
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- qcom,msm-qgic2 |
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- items: |
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- const: arm,gic-400 |
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- enum: |
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- arm,cortex-a15-gic |
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- arm,cortex-a7-gic |
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- items: |
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- const: arm,arm1176jzf-devchip-gic |
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- const: arm,arm11mp-gic |
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- items: |
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- const: brcm,brahma-b15-gic |
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- const: arm,cortex-a15-gic |
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- oneOf: |
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- const: nvidia,tegra210-agic |
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- items: |
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- enum: |
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- nvidia,tegra186-agic |
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- nvidia,tegra194-agic |
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- nvidia,tegra234-agic |
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- const: nvidia,tegra210-agic |
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interrupt-controller: true |
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"#address-cells": |
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enum: [ 0, 1 ] |
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"#size-cells": |
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const: 1 |
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"#interrupt-cells": |
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const: 3 |
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description: | |
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI |
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interrupts. |
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The 2nd cell contains the interrupt number for the interrupt type. |
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SPI interrupts are in the range [0-987]. PPI interrupts are in the |
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range [0-15]. |
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The 3rd cell is the flags, encoded as follows: |
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bits[3:0] trigger type and level flags. |
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1 = low-to-high edge triggered |
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2 = high-to-low edge triggered (invalid for SPIs) |
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4 = active high level-sensitive |
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8 = active low level-sensitive (invalid for SPIs). |
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bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of |
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the 8 possible cpus attached to the GIC. A bit set to '1' indicated |
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the interrupt is wired to that CPU. Only valid for PPI interrupts. |
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Also note that the configurability of PPI interrupts is IMPLEMENTATION |
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DEFINED and as such not guaranteed to be present (most SoC available |
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in 2014 seem to ignore the setting of this flag and use the hardware |
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default value). |
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reg: |
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description: | |
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Specifies base physical address(s) and size of the GIC registers. The |
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first region is the GIC distributor register base and size. The 2nd region |
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is the GIC cpu interface register base and size. |
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For GICv2 with virtualization extensions, additional regions are |
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required for specifying the base physical address and size of the VGIC |
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registers. The first additional region is the GIC virtual interface |
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control register base and size. The 2nd additional region is the GIC |
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virtual cpu interface register base and size. |
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minItems: 2 |
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maxItems: 4 |
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ranges: true |
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interrupts: |
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description: Interrupt source of the parent interrupt controller on |
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secondary GICs, or VGIC maintenance interrupt on primary GIC (see |
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below). |
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maxItems: 1 |
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cpu-offset: |
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description: per-cpu offset within the distributor and cpu interface |
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regions, used when the GIC doesn't have banked registers. The offset |
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is cpu-offset * cpu-nr. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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clocks: |
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minItems: 1 |
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maxItems: 2 |
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clock-names: |
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description: List of names for the GIC clock input(s). Valid clock names |
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depend on the GIC variant. |
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oneOf: |
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- const: ic_clk # for "arm,arm11mp-gic" |
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- const: PERIPHCLKEN # for "arm,cortex-a15-gic" |
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- items: # for "arm,cortex-a9-gic" |
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- const: PERIPHCLK |
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- const: PERIPHCLKEN |
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- const: clk # for "arm,gic-400" and "nvidia,tegra210" |
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- const: gclk #for "arm,pl390" |
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power-domains: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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required: |
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- compatible |
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- reg |
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patternProperties: |
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"^v2m@[0-9a-f]+$": |
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type: object |
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description: | |
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* GICv2m extension for MSI/MSI-x support (Optional) |
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Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). |
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This is enabled by specifying v2m sub-node(s). |
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properties: |
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compatible: |
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const: arm,gic-v2m-frame |
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msi-controller: true |
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reg: |
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maxItems: 1 |
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description: GICv2m MSI interface register base and size |
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arm,msi-base-spi: |
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description: When the MSI_TYPER register contains an incorrect value, |
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this property should contain the SPI base of the MSI frame, overriding |
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the HW value. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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arm,msi-num-spis: |
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description: When the MSI_TYPER register contains an incorrect value, |
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this property should contain the number of SPIs assigned to the |
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frame, overriding the HW value. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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required: |
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- compatible |
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- msi-controller |
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- reg |
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additionalProperties: false |
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additionalProperties: false |
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examples: |
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- | |
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// GICv1 |
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intc: interrupt-controller@fff11000 { |
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compatible = "arm,cortex-a9-gic"; |
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#interrupt-cells = <3>; |
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#address-cells = <1>; |
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interrupt-controller; |
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reg = <0xfff11000 0x1000>, |
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<0xfff10100 0x100>; |
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}; |
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- | |
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// GICv2 |
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interrupt-controller@2c001000 { |
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compatible = "arm,cortex-a15-gic"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x2c001000 0x1000>, |
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<0x2c002000 0x2000>, |
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<0x2c004000 0x2000>, |
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<0x2c006000 0x2000>; |
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interrupts = <1 9 0xf04>; |
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}; |
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- | |
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// GICv2m extension for MSI/MSI-x support |
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interrupt-controller@e1101000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-controller; |
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interrupts = <1 8 0xf04>; |
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ranges = <0 0xe1100000 0x100000>; |
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reg = <0xe1110000 0x01000>, |
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<0xe112f000 0x02000>, |
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<0xe1140000 0x10000>, |
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<0xe1160000 0x10000>; |
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v2m0: v2m@80000 { |
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compatible = "arm,gic-v2m-frame"; |
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msi-controller; |
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reg = <0x80000 0x1000>; |
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}; |
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//... |
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v2mN: v2m@90000 { |
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compatible = "arm,gic-v2m-frame"; |
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msi-controller; |
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reg = <0x90000 0x1000>; |
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}; |
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}; |
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...
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