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37 lines
1.3 KiB
37 lines
1.3 KiB
TB10x Top Level Interrupt Controller |
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==================================== |
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The Abilis TB10x SOC contains a custom interrupt controller. It performs |
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one-to-one mapping of external interrupt sources to CPU interrupts and |
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provides support for reconfigurable trigger modes. |
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Required properties |
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------------------- |
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- compatible: Should be "abilis,tb10x-ictl" |
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- reg: specifies physical base address and size of register range. |
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- interrupt-congroller: Identifies the node as an interrupt controller. |
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- #interrupt cells: Specifies the number of cells used to encode an interrupt |
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source connected to this controller. The value shall be 2. |
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- interrupts: Specifies the list of interrupt lines which are handled by |
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the interrupt controller in the parent controller's notation. Interrupts |
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are mapped one-to-one to parent interrupts. |
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Example |
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------- |
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intc: interrupt-controller { /* Parent interrupt controller */ |
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interrupt-controller; |
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#interrupt-cells = <1>; /* For example below */ |
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/* ... */ |
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}; |
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tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ |
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compatible = "abilis,tb10x-ictl"; |
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reg = <0x2000 0x20>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&intc>; |
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interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 |
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20 21 22 23 24 25 26 27 28 29 30 31>; |
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};
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