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154 lines
3.9 KiB
154 lines
3.9 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: I2C controller embedded in STMicroelectronics STM32 I2C platform |
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maintainers: |
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- Pierre-Yves MORDRET <[email protected]> |
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allOf: |
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- $ref: /schemas/i2c/i2c-controller.yaml# |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- st,stm32f7-i2c |
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- st,stm32mp13-i2c |
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- st,stm32mp15-i2c |
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then: |
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properties: |
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i2c-scl-rising-time-ns: |
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default: 25 |
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i2c-scl-falling-time-ns: |
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default: 10 |
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else: |
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properties: |
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st,syscfg-fmp: false |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- st,stm32f4-i2c |
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then: |
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properties: |
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clock-frequency: |
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enum: [100000, 400000] |
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properties: |
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compatible: |
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enum: |
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- st,stm32f4-i2c |
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- st,stm32f7-i2c |
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- st,stm32mp13-i2c |
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- st,stm32mp15-i2c |
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reg: |
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maxItems: 1 |
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interrupts: |
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items: |
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- description: interrupt ID for I2C event |
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- description: interrupt ID for I2C error |
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resets: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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dmas: |
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items: |
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- description: RX DMA Channel phandle |
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- description: TX DMA Channel phandle |
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dma-names: |
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items: |
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- const: rx |
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- const: tx |
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clock-frequency: |
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description: Desired I2C bus clock frequency in Hz. If not specified, |
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the default 100 kHz frequency will be used. |
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For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters |
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match, the bus clock frequency can be from 1Hz to 1MHz. |
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default: 100000 |
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minimum: 1 |
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maximum: 1000000 |
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st,syscfg-fmp: |
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description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode |
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Plus speed is selected by slave. |
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$ref: "/schemas/types.yaml#/definitions/phandle-array" |
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items: |
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- items: |
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- description: phandle to syscfg |
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- description: register offset within syscfg |
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- description: register bitmask for FMP bit |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- resets |
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- clocks |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/mfd/stm32f7-rcc.h> |
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#include <dt-bindings/clock/stm32fx-clock.h> |
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//Example 1 (with st,stm32f4-i2c compatible) |
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i2c@40005400 { |
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compatible = "st,stm32f4-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x40005400 0x400>; |
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interrupts = <31>, |
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<32>; |
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resets = <&rcc 277>; |
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clocks = <&rcc 0 149>; |
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}; |
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- | |
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#include <dt-bindings/mfd/stm32f7-rcc.h> |
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#include <dt-bindings/clock/stm32fx-clock.h> |
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//Example 2 (with st,stm32f7-i2c compatible) |
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i2c@40005800 { |
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compatible = "st,stm32f7-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x40005800 0x400>; |
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interrupts = <31>, |
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<32>; |
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>; |
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clocks = <&rcc 1 CLK_I2C1>; |
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}; |
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- | |
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#include <dt-bindings/mfd/stm32f7-rcc.h> |
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#include <dt-bindings/clock/stm32fx-clock.h> |
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//Example 3 (with st,stm32mp15-i2c compatible on stm32mp) |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/stm32mp1-clks.h> |
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#include <dt-bindings/reset/stm32mp1-resets.h> |
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i2c@40013000 { |
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compatible = "st,stm32mp15-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x40013000 0x400>; |
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rcc I2C2_K>; |
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resets = <&rcc I2C2_R>; |
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i2c-scl-rising-time-ns = <185>; |
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i2c-scl-falling-time-ns = <20>; |
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st,syscfg-fmp = <&syscfg 0x4 0x2>; |
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};
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