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191 lines
5.7 KiB
191 lines
5.7 KiB
Atmel system registers |
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Chipid required properties: |
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- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" |
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- reg : Should contain registers location and length |
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PIT Timer required properties: |
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- compatible: Should be "atmel,at91sam9260-pit" |
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- reg: Should contain registers location and length |
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- interrupts: Should contain interrupt for the PIT which is the IRQ line |
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shared across all System Controller members. |
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PIT64B Timer required properties: |
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- compatible: Should be "microchip,sam9x60-pit64b" |
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- reg: Should contain registers location and length |
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- interrupts: Should contain interrupt for PIT64B timer |
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- clocks: Should contain the available clock sources for PIT64B timer. |
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System Timer (ST) required properties: |
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- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" |
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- reg: Should contain registers location and length |
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- interrupts: Should contain interrupt for the ST which is the IRQ line |
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shared across all System Controller members. |
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- clocks: phandle to input clock. |
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Its subnodes can be: |
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- watchdog: compatible should be "atmel,at91rm9200-wdt" |
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RAMC SDRAM/DDR Controller required properties: |
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- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" |
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"atmel,at91sam9260-sdramc", |
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"atmel,at91sam9g45-ddramc", |
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"atmel,sama5d3-ddramc", |
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"microchip,sam9x60-ddramc", |
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"microchip,sama7g5-uddrc" |
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- reg: Should contain registers location and length |
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Examples: |
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ramc0: ramc@ffffe800 { |
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compatible = "atmel,at91sam9g45-ddramc"; |
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reg = <0xffffe800 0x200>; |
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}; |
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RAMC PHY Controller required properties: |
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- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" |
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- reg: Should contain registers location and length |
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Example: |
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ddr3phy: ddr3phy@e3804000 { |
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compatible = "microchip,sama7g5-ddr3phy", "syscon"; |
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reg = <0xe3804000 0x1000>; |
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}; |
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SHDWC Shutdown Controller |
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required properties: |
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- compatible: Should be "atmel,<chip>-shdwc". |
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<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". |
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- reg: Should contain registers location and length |
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- clocks: phandle to input clock. |
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optional properties: |
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- atmel,wakeup-mode: String, operation mode of the wakeup mode. |
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Supported values are: "none", "high", "low", "any". |
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- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). |
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optional at91sam9260 properties: |
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
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optional at91sam9rl properties: |
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- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
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optional at91sam9x5 properties: |
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- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
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Example: |
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shdwc@fffffd10 { |
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compatible = "atmel,at91sam9260-shdwc"; |
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reg = <0xfffffd10 0x10>; |
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clocks = <&clk32k>; |
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}; |
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SHDWC SAMA5D2-Compatible Shutdown Controller |
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1) shdwc node |
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required properties: |
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- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or |
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"microchip,sama7g5-shdwc" |
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- reg: should contain registers location and length |
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- clocks: phandle to input clock. |
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- #address-cells: should be one. The cell is the wake-up input index. |
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- #size-cells: should be zero. |
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optional properties: |
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- debounce-delay-us: minimum wake-up inputs debouncer period in |
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microseconds. It's usually a board-related property. |
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- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. |
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optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: |
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- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
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The node contains child nodes for each wake-up input that the platform uses. |
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2) input nodes |
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Wake-up input nodes are usually described in the "board" part of the Device |
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Tree. Note also that input 0 is linked to the wake-up pin and is frequently |
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used. |
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Required properties: |
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- reg: should contain the wake-up input index [0 - 15]. |
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Optional properties: |
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- atmel,wakeup-active-high: boolean, the corresponding wake-up input described |
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by the child, forces the wake-up of the core power supply on a high level. |
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The default is to be active low. |
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Example: |
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On the SoC side: |
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shdwc@f8048010 { |
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compatible = "atmel,sama5d2-shdwc"; |
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reg = <0xf8048010 0x10>; |
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clocks = <&clk32k>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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atmel,wakeup-rtc-timer; |
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}; |
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On the board side: |
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shdwc@f8048010 { |
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debounce-delay-us = <976>; |
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input@0 { |
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reg = <0>; |
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}; |
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input@1 { |
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reg = <1>; |
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atmel,wakeup-active-high; |
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}; |
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}; |
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Special Function Registers (SFR) |
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Special Function Registers (SFR) manage specific aspects of the integrated |
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memory, bridge implementations, processor and other functionality not controlled |
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elsewhere. |
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required properties: |
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- compatible: Should be "atmel,<chip>-sfr", "syscon" or |
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"atmel,<chip>-sfrbu", "syscon" |
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<chip> can be "sama5d3", "sama5d4" or "sama5d2". |
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It also can be "microchip,sam9x60-sfr", "syscon". |
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- reg: Should contain registers location and length |
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sfr@f0038000 { |
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compatible = "atmel,sama5d3-sfr", "syscon"; |
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reg = <0xf0038000 0x60>; |
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}; |
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Security Module (SECUMOD) |
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The Security Module macrocell provides all necessary secure functions to avoid |
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voltage, temperature, frequency and mechanical attacks on the chip. It also |
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embeds secure memories that can be scrambled. |
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The Security Module also offers the PIOBU pins which can be used as GPIO pins. |
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Note that they maintain their voltage during Backup/Self-refresh. |
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required properties: |
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- compatible: Should be "atmel,<chip>-secumod", "syscon". |
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<chip> can be "sama5d2". |
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- reg: Should contain registers location and length |
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- gpio-controller: Marks the port as GPIO controller. |
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- #gpio-cells: There are 2. The pin number is the |
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first, the second represents additional |
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parameters such as GPIO_ACTIVE_HIGH/LOW. |
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secumod@fc040000 { |
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compatible = "atmel,sama5d2-secumod", "syscon"; |
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reg = <0xfc040000 0x100>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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};
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