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27 lines
834 B
27 lines
834 B
* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) |
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ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores |
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with a shared L3 memory system, control logic and external interfaces to |
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form a multicore cluster. The PMU enables to gather various statistics on |
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the operations of the DSU. The PMU provides independent 32bit counters that |
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can count any of the supported events, along with a 64bit cycle counter. |
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The PMU is accessed via CPU system registers and has no MMIO component. |
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** DSU PMU required properties: |
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- compatible : should be one of : |
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"arm,dsu-pmu" |
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- interrupts : Exactly 1 SPI must be listed. |
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- cpus : List of phandles for the CPUs connected to this DSU instance. |
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** Example: |
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dsu-pmu-0 { |
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compatible = "arm,dsu-pmu"; |
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; |
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cpus = <&cpu_0>, <&cpu_1>; |
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};
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