mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-11 17:55:54 +00:00
more cleanup
This commit is contained in:
Raziel K. Crowe
parent
7dec27f73b
commit
7ae6aaac6f
561
.clang-format
561
.clang-format
@ -1,561 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# clang-format configuration file. Intended for clang-format >= 4.
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#
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# For more information, see:
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#
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# Documentation/process/clang-format.rst
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# https://clang.llvm.org/docs/ClangFormat.html
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# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
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#
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---
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AccessModifierOffset: -4
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AlignAfterOpenBracket: Align
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AlignConsecutiveAssignments: false
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AlignConsecutiveDeclarations: false
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#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
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AlignOperands: true
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AlignTrailingComments: false
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AllowAllParametersOfDeclarationOnNextLine: false
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AllowShortBlocksOnASingleLine: false
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AllowShortCaseLabelsOnASingleLine: false
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AllowShortFunctionsOnASingleLine: None
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AllowShortIfStatementsOnASingleLine: false
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AllowShortLoopsOnASingleLine: false
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AlwaysBreakAfterDefinitionReturnType: None
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AlwaysBreakAfterReturnType: None
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AlwaysBreakBeforeMultilineStrings: false
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AlwaysBreakTemplateDeclarations: false
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BinPackArguments: true
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BinPackParameters: true
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BraceWrapping:
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AfterClass: false
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AfterControlStatement: false
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AfterEnum: false
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AfterFunction: true
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AfterNamespace: true
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AfterObjCDeclaration: false
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AfterStruct: false
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AfterUnion: false
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#AfterExternBlock: false # Unknown to clang-format-5.0
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BeforeCatch: false
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BeforeElse: false
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IndentBraces: false
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#SplitEmptyFunction: true # Unknown to clang-format-4.0
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#SplitEmptyRecord: true # Unknown to clang-format-4.0
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#SplitEmptyNamespace: true # Unknown to clang-format-4.0
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BreakBeforeBinaryOperators: None
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BreakBeforeBraces: Custom
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#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
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BreakBeforeTernaryOperators: false
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BreakConstructorInitializersBeforeComma: false
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#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
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BreakAfterJavaFieldAnnotations: false
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BreakStringLiterals: false
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ColumnLimit: 80
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CommentPragmas: '^ IWYU pragma:'
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#CompactNamespaces: false # Unknown to clang-format-4.0
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ConstructorInitializerAllOnOneLineOrOnePerLine: false
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ConstructorInitializerIndentWidth: 8
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ContinuationIndentWidth: 8
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Cpp11BracedListStyle: false
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DerivePointerAlignment: false
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DisableFormat: false
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ExperimentalAutoDetectBinPacking: false
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#FixNamespaceComments: false # Unknown to clang-format-4.0
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# Taken from:
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# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
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# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
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# | sort | uniq
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ForEachMacros:
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- 'apei_estatus_for_each_section'
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- 'ata_for_each_dev'
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- 'ata_for_each_link'
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- '__ata_qc_for_each'
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- 'ata_qc_for_each'
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- 'ata_qc_for_each_raw'
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- 'ata_qc_for_each_with_internal'
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- 'ax25_for_each'
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- 'ax25_uid_for_each'
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- '__bio_for_each_bvec'
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- 'bio_for_each_bvec'
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- 'bio_for_each_bvec_all'
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- 'bio_for_each_integrity_vec'
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- '__bio_for_each_segment'
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- 'bio_for_each_segment'
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- 'bio_for_each_segment_all'
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- 'bio_list_for_each'
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- 'bip_for_each_vec'
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- 'bitmap_for_each_clear_region'
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- 'bitmap_for_each_set_region'
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- 'blkg_for_each_descendant_post'
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- 'blkg_for_each_descendant_pre'
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- 'blk_queue_for_each_rl'
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- 'bond_for_each_slave'
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- 'bond_for_each_slave_rcu'
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- 'bpf_for_each_spilled_reg'
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- 'btree_for_each_safe128'
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- 'btree_for_each_safe32'
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- 'btree_for_each_safe64'
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- 'btree_for_each_safel'
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- 'card_for_each_dev'
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- 'cgroup_taskset_for_each'
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- 'cgroup_taskset_for_each_leader'
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- 'cpufreq_for_each_entry'
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- 'cpufreq_for_each_entry_idx'
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- 'cpufreq_for_each_valid_entry'
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- 'cpufreq_for_each_valid_entry_idx'
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- 'css_for_each_child'
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- 'css_for_each_descendant_post'
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- 'css_for_each_descendant_pre'
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- 'device_for_each_child_node'
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- 'displayid_iter_for_each'
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- 'dma_fence_chain_for_each'
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- 'do_for_each_ftrace_op'
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- 'drm_atomic_crtc_for_each_plane'
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- 'drm_atomic_crtc_state_for_each_plane'
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- 'drm_atomic_crtc_state_for_each_plane_state'
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- 'drm_atomic_for_each_plane_damage'
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- 'drm_client_for_each_connector_iter'
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- 'drm_client_for_each_modeset'
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- 'drm_connector_for_each_possible_encoder'
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- 'drm_for_each_bridge_in_chain'
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- 'drm_for_each_connector_iter'
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- 'drm_for_each_crtc'
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- 'drm_for_each_crtc_reverse'
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- 'drm_for_each_encoder'
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- 'drm_for_each_encoder_mask'
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- 'drm_for_each_fb'
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- 'drm_for_each_legacy_plane'
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- 'drm_for_each_plane'
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- 'drm_for_each_plane_mask'
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- 'drm_for_each_privobj'
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- 'drm_mm_for_each_hole'
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- 'drm_mm_for_each_node'
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- 'drm_mm_for_each_node_in_range'
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- 'drm_mm_for_each_node_safe'
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- 'flow_action_for_each'
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- 'for_each_acpi_dev_match'
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- 'for_each_active_dev_scope'
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- 'for_each_active_drhd_unit'
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- 'for_each_active_iommu'
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- 'for_each_aggr_pgid'
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- 'for_each_available_child_of_node'
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- 'for_each_bio'
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- 'for_each_board_func_rsrc'
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- 'for_each_bvec'
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- 'for_each_card_auxs'
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- 'for_each_card_auxs_safe'
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- 'for_each_card_components'
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- 'for_each_card_dapms'
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- 'for_each_card_pre_auxs'
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- 'for_each_card_prelinks'
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- 'for_each_card_rtds'
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- 'for_each_card_rtds_safe'
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- 'for_each_card_widgets'
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- 'for_each_card_widgets_safe'
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- 'for_each_cgroup_storage_type'
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- 'for_each_child_of_node'
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- 'for_each_clear_bit'
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- 'for_each_clear_bit_from'
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- 'for_each_cmsghdr'
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- 'for_each_compatible_node'
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- 'for_each_component_dais'
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- 'for_each_component_dais_safe'
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- 'for_each_comp_order'
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- 'for_each_console'
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- 'for_each_cpu'
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- 'for_each_cpu_and'
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- 'for_each_cpu_not'
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- 'for_each_cpu_wrap'
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- 'for_each_dapm_widgets'
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- 'for_each_dev_addr'
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- 'for_each_dev_scope'
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- 'for_each_dma_cap_mask'
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- 'for_each_dpcm_be'
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- 'for_each_dpcm_be_rollback'
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- 'for_each_dpcm_be_safe'
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- 'for_each_dpcm_fe'
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- 'for_each_drhd_unit'
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- 'for_each_dss_dev'
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- 'for_each_dtpm_table'
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- 'for_each_efi_memory_desc'
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- 'for_each_efi_memory_desc_in_map'
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- 'for_each_element'
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- 'for_each_element_extid'
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- 'for_each_element_id'
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- 'for_each_endpoint_of_node'
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- 'for_each_evictable_lru'
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- 'for_each_fib6_node_rt_rcu'
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- 'for_each_fib6_walker_rt'
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- 'for_each_free_mem_pfn_range_in_zone'
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- 'for_each_free_mem_pfn_range_in_zone_from'
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- 'for_each_free_mem_range'
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- 'for_each_free_mem_range_reverse'
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- 'for_each_func_rsrc'
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- 'for_each_hstate'
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- 'for_each_if'
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- 'for_each_iommu'
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- 'for_each_ip_tunnel_rcu'
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- 'for_each_irq_nr'
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- 'for_each_link_codecs'
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- 'for_each_link_cpus'
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- 'for_each_link_platforms'
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- 'for_each_lru'
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- 'for_each_matching_node'
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- 'for_each_matching_node_and_match'
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- 'for_each_member'
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- 'for_each_memcg_cache_index'
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- 'for_each_mem_pfn_range'
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- '__for_each_mem_range'
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- 'for_each_mem_range'
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- '__for_each_mem_range_rev'
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- 'for_each_mem_range_rev'
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- 'for_each_mem_region'
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- 'for_each_migratetype_order'
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- 'for_each_msi_entry'
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- 'for_each_msi_entry_safe'
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- 'for_each_msi_vector'
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- 'for_each_net'
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- 'for_each_net_continue_reverse'
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- 'for_each_netdev'
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- 'for_each_netdev_continue'
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- 'for_each_netdev_continue_rcu'
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- 'for_each_netdev_continue_reverse'
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- 'for_each_netdev_feature'
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- 'for_each_netdev_in_bond_rcu'
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- 'for_each_netdev_rcu'
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- 'for_each_netdev_reverse'
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- 'for_each_netdev_safe'
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- 'for_each_net_rcu'
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- 'for_each_new_connector_in_state'
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- 'for_each_new_crtc_in_state'
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- 'for_each_new_mst_mgr_in_state'
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- 'for_each_new_plane_in_state'
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- 'for_each_new_private_obj_in_state'
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- 'for_each_node'
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- 'for_each_node_by_name'
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- 'for_each_node_by_type'
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- 'for_each_node_mask'
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- 'for_each_node_state'
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- 'for_each_node_with_cpus'
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- 'for_each_node_with_property'
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- 'for_each_nonreserved_multicast_dest_pgid'
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- 'for_each_of_allnodes'
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- 'for_each_of_allnodes_from'
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- 'for_each_of_cpu_node'
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- 'for_each_of_pci_range'
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- 'for_each_old_connector_in_state'
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- 'for_each_old_crtc_in_state'
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- 'for_each_old_mst_mgr_in_state'
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- 'for_each_oldnew_connector_in_state'
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- 'for_each_oldnew_crtc_in_state'
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- 'for_each_oldnew_mst_mgr_in_state'
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- 'for_each_oldnew_plane_in_state'
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||||
- 'for_each_oldnew_plane_in_state_reverse'
|
||||
- 'for_each_oldnew_private_obj_in_state'
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- 'for_each_old_plane_in_state'
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- 'for_each_old_private_obj_in_state'
|
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- 'for_each_online_cpu'
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- 'for_each_online_node'
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- 'for_each_online_pgdat'
|
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- 'for_each_pci_bridge'
|
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- 'for_each_pci_dev'
|
||||
- 'for_each_pci_msi_entry'
|
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- 'for_each_pcm_streams'
|
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- 'for_each_physmem_range'
|
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- 'for_each_populated_zone'
|
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- 'for_each_possible_cpu'
|
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- 'for_each_present_cpu'
|
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- 'for_each_prime_number'
|
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- 'for_each_prime_number_from'
|
||||
- 'for_each_process'
|
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- 'for_each_process_thread'
|
||||
- 'for_each_prop_codec_conf'
|
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- 'for_each_prop_dai_codec'
|
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- 'for_each_prop_dai_cpu'
|
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- 'for_each_prop_dlc_codecs'
|
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- 'for_each_prop_dlc_cpus'
|
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- 'for_each_prop_dlc_platforms'
|
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- 'for_each_property_of_node'
|
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- 'for_each_registered_fb'
|
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- 'for_each_requested_gpio'
|
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- 'for_each_requested_gpio_in_range'
|
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- 'for_each_reserved_mem_range'
|
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- 'for_each_reserved_mem_region'
|
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- 'for_each_rtd_codec_dais'
|
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- 'for_each_rtd_components'
|
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- 'for_each_rtd_cpu_dais'
|
||||
- 'for_each_rtd_dais'
|
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- 'for_each_set_bit'
|
||||
- 'for_each_set_bit_from'
|
||||
- 'for_each_set_clump8'
|
||||
- 'for_each_sg'
|
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- 'for_each_sg_dma_page'
|
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- 'for_each_sg_page'
|
||||
- 'for_each_sgtable_dma_page'
|
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- 'for_each_sgtable_dma_sg'
|
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- 'for_each_sgtable_page'
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- 'for_each_sgtable_sg'
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- 'for_each_sibling_event'
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- 'for_each_subelement'
|
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- 'for_each_subelement_extid'
|
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- 'for_each_subelement_id'
|
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- '__for_each_thread'
|
||||
- 'for_each_thread'
|
||||
- 'for_each_unicast_dest_pgid'
|
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- 'for_each_vsi'
|
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- 'for_each_wakeup_source'
|
||||
- 'for_each_zone'
|
||||
- 'for_each_zone_zonelist'
|
||||
- 'for_each_zone_zonelist_nodemask'
|
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- 'fwnode_for_each_available_child_node'
|
||||
- 'fwnode_for_each_child_node'
|
||||
- 'fwnode_graph_for_each_endpoint'
|
||||
- 'gadget_for_each_ep'
|
||||
- 'genradix_for_each'
|
||||
- 'genradix_for_each_from'
|
||||
- 'hash_for_each'
|
||||
- 'hash_for_each_possible'
|
||||
- 'hash_for_each_possible_rcu'
|
||||
- 'hash_for_each_possible_rcu_notrace'
|
||||
- 'hash_for_each_possible_safe'
|
||||
- 'hash_for_each_rcu'
|
||||
- 'hash_for_each_safe'
|
||||
- 'hctx_for_each_ctx'
|
||||
- 'hlist_bl_for_each_entry'
|
||||
- 'hlist_bl_for_each_entry_rcu'
|
||||
- 'hlist_bl_for_each_entry_safe'
|
||||
- 'hlist_for_each'
|
||||
- 'hlist_for_each_entry'
|
||||
- 'hlist_for_each_entry_continue'
|
||||
- 'hlist_for_each_entry_continue_rcu'
|
||||
- 'hlist_for_each_entry_continue_rcu_bh'
|
||||
- 'hlist_for_each_entry_from'
|
||||
- 'hlist_for_each_entry_from_rcu'
|
||||
- 'hlist_for_each_entry_rcu'
|
||||
- 'hlist_for_each_entry_rcu_bh'
|
||||
- 'hlist_for_each_entry_rcu_notrace'
|
||||
- 'hlist_for_each_entry_safe'
|
||||
- 'hlist_for_each_entry_srcu'
|
||||
- '__hlist_for_each_rcu'
|
||||
- 'hlist_for_each_safe'
|
||||
- 'hlist_nulls_for_each_entry'
|
||||
- 'hlist_nulls_for_each_entry_from'
|
||||
- 'hlist_nulls_for_each_entry_rcu'
|
||||
- 'hlist_nulls_for_each_entry_safe'
|
||||
- 'i3c_bus_for_each_i2cdev'
|
||||
- 'i3c_bus_for_each_i3cdev'
|
||||
- 'ide_host_for_each_port'
|
||||
- 'ide_port_for_each_dev'
|
||||
- 'ide_port_for_each_present_dev'
|
||||
- 'idr_for_each_entry'
|
||||
- 'idr_for_each_entry_continue'
|
||||
- 'idr_for_each_entry_continue_ul'
|
||||
- 'idr_for_each_entry_ul'
|
||||
- 'in_dev_for_each_ifa_rcu'
|
||||
- 'in_dev_for_each_ifa_rtnl'
|
||||
- 'inet_bind_bucket_for_each'
|
||||
- 'inet_lhash2_for_each_icsk_rcu'
|
||||
- 'key_for_each'
|
||||
- 'key_for_each_safe'
|
||||
- 'klp_for_each_func'
|
||||
- 'klp_for_each_func_safe'
|
||||
- 'klp_for_each_func_static'
|
||||
- 'klp_for_each_object'
|
||||
- 'klp_for_each_object_safe'
|
||||
- 'klp_for_each_object_static'
|
||||
- 'kunit_suite_for_each_test_case'
|
||||
- 'kvm_for_each_memslot'
|
||||
- 'kvm_for_each_vcpu'
|
||||
- 'list_for_each'
|
||||
- 'list_for_each_codec'
|
||||
- 'list_for_each_codec_safe'
|
||||
- 'list_for_each_continue'
|
||||
- 'list_for_each_entry'
|
||||
- 'list_for_each_entry_continue'
|
||||
- 'list_for_each_entry_continue_rcu'
|
||||
- 'list_for_each_entry_continue_reverse'
|
||||
- 'list_for_each_entry_from'
|
||||
- 'list_for_each_entry_from_rcu'
|
||||
- 'list_for_each_entry_from_reverse'
|
||||
- 'list_for_each_entry_lockless'
|
||||
- 'list_for_each_entry_rcu'
|
||||
- 'list_for_each_entry_reverse'
|
||||
- 'list_for_each_entry_safe'
|
||||
- 'list_for_each_entry_safe_continue'
|
||||
- 'list_for_each_entry_safe_from'
|
||||
- 'list_for_each_entry_safe_reverse'
|
||||
- 'list_for_each_entry_srcu'
|
||||
- 'list_for_each_prev'
|
||||
- 'list_for_each_prev_safe'
|
||||
- 'list_for_each_safe'
|
||||
- 'llist_for_each'
|
||||
- 'llist_for_each_entry'
|
||||
- 'llist_for_each_entry_safe'
|
||||
- 'llist_for_each_safe'
|
||||
- 'mci_for_each_dimm'
|
||||
- 'media_device_for_each_entity'
|
||||
- 'media_device_for_each_intf'
|
||||
- 'media_device_for_each_link'
|
||||
- 'media_device_for_each_pad'
|
||||
- 'nanddev_io_for_each_page'
|
||||
- 'netdev_for_each_lower_dev'
|
||||
- 'netdev_for_each_lower_private'
|
||||
- 'netdev_for_each_lower_private_rcu'
|
||||
- 'netdev_for_each_mc_addr'
|
||||
- 'netdev_for_each_uc_addr'
|
||||
- 'netdev_for_each_upper_dev_rcu'
|
||||
- 'netdev_hw_addr_list_for_each'
|
||||
- 'nft_rule_for_each_expr'
|
||||
- 'nla_for_each_attr'
|
||||
- 'nla_for_each_nested'
|
||||
- 'nlmsg_for_each_attr'
|
||||
- 'nlmsg_for_each_msg'
|
||||
- 'nr_neigh_for_each'
|
||||
- 'nr_neigh_for_each_safe'
|
||||
- 'nr_node_for_each'
|
||||
- 'nr_node_for_each_safe'
|
||||
- 'of_for_each_phandle'
|
||||
- 'of_property_for_each_string'
|
||||
- 'of_property_for_each_u32'
|
||||
- 'pci_bus_for_each_resource'
|
||||
- 'pcl_for_each_chunk'
|
||||
- 'pcl_for_each_segment'
|
||||
- 'pcm_for_each_format'
|
||||
- 'ping_portaddr_for_each_entry'
|
||||
- 'plist_for_each'
|
||||
- 'plist_for_each_continue'
|
||||
- 'plist_for_each_entry'
|
||||
- 'plist_for_each_entry_continue'
|
||||
- 'plist_for_each_entry_safe'
|
||||
- 'plist_for_each_safe'
|
||||
- 'pnp_for_each_card'
|
||||
- 'pnp_for_each_dev'
|
||||
- 'protocol_for_each_card'
|
||||
- 'protocol_for_each_dev'
|
||||
- 'queue_for_each_hw_ctx'
|
||||
- 'radix_tree_for_each_slot'
|
||||
- 'radix_tree_for_each_tagged'
|
||||
- 'rb_for_each'
|
||||
- 'rbtree_postorder_for_each_entry_safe'
|
||||
- 'rdma_for_each_block'
|
||||
- 'rdma_for_each_port'
|
||||
- 'rdma_umem_for_each_dma_block'
|
||||
- 'resource_list_for_each_entry'
|
||||
- 'resource_list_for_each_entry_safe'
|
||||
- 'rhl_for_each_entry_rcu'
|
||||
- 'rhl_for_each_rcu'
|
||||
- 'rht_for_each'
|
||||
- 'rht_for_each_entry'
|
||||
- 'rht_for_each_entry_from'
|
||||
- 'rht_for_each_entry_rcu'
|
||||
- 'rht_for_each_entry_rcu_from'
|
||||
- 'rht_for_each_entry_safe'
|
||||
- 'rht_for_each_from'
|
||||
- 'rht_for_each_rcu'
|
||||
- 'rht_for_each_rcu_from'
|
||||
- '__rq_for_each_bio'
|
||||
- 'rq_for_each_bvec'
|
||||
- 'rq_for_each_segment'
|
||||
- 'scsi_for_each_prot_sg'
|
||||
- 'scsi_for_each_sg'
|
||||
- 'sctp_for_each_hentry'
|
||||
- 'sctp_skb_for_each'
|
||||
- 'shdma_for_each_chan'
|
||||
- '__shost_for_each_device'
|
||||
- 'shost_for_each_device'
|
||||
- 'sk_for_each'
|
||||
- 'sk_for_each_bound'
|
||||
- 'sk_for_each_entry_offset_rcu'
|
||||
- 'sk_for_each_from'
|
||||
- 'sk_for_each_rcu'
|
||||
- 'sk_for_each_safe'
|
||||
- 'sk_nulls_for_each'
|
||||
- 'sk_nulls_for_each_from'
|
||||
- 'sk_nulls_for_each_rcu'
|
||||
- 'snd_array_for_each'
|
||||
- 'snd_pcm_group_for_each_entry'
|
||||
- 'snd_soc_dapm_widget_for_each_path'
|
||||
- 'snd_soc_dapm_widget_for_each_path_safe'
|
||||
- 'snd_soc_dapm_widget_for_each_sink_path'
|
||||
- 'snd_soc_dapm_widget_for_each_source_path'
|
||||
- 'tb_property_for_each'
|
||||
- 'tcf_exts_for_each_action'
|
||||
- 'udp_portaddr_for_each_entry'
|
||||
- 'udp_portaddr_for_each_entry_rcu'
|
||||
- 'usb_hub_for_each_child'
|
||||
- 'v4l2_device_for_each_subdev'
|
||||
- 'v4l2_m2m_for_each_dst_buf'
|
||||
- 'v4l2_m2m_for_each_dst_buf_safe'
|
||||
- 'v4l2_m2m_for_each_src_buf'
|
||||
- 'v4l2_m2m_for_each_src_buf_safe'
|
||||
- 'virtio_device_for_each_vq'
|
||||
- 'while_for_each_ftrace_op'
|
||||
- 'xa_for_each'
|
||||
- 'xa_for_each_marked'
|
||||
- 'xa_for_each_range'
|
||||
- 'xa_for_each_start'
|
||||
- 'xas_for_each'
|
||||
- 'xas_for_each_conflict'
|
||||
- 'xas_for_each_marked'
|
||||
- 'xbc_array_for_each_value'
|
||||
- 'xbc_for_each_key_value'
|
||||
- 'xbc_node_for_each_array_value'
|
||||
- 'xbc_node_for_each_child'
|
||||
- 'xbc_node_for_each_key_value'
|
||||
- 'zorro_for_each_dev'
|
||||
|
||||
#IncludeBlocks: Preserve # Unknown to clang-format-5.0
|
||||
IncludeCategories:
|
||||
- Regex: '.*'
|
||||
Priority: 1
|
||||
IncludeIsMainRegex: '(Test)?$'
|
||||
IndentCaseLabels: false
|
||||
#IndentPPDirectives: None # Unknown to clang-format-5.0
|
||||
IndentWidth: 8
|
||||
IndentWrappedFunctionNames: false
|
||||
JavaScriptQuotes: Leave
|
||||
JavaScriptWrapImports: true
|
||||
KeepEmptyLinesAtTheStartOfBlocks: false
|
||||
MacroBlockBegin: ''
|
||||
MacroBlockEnd: ''
|
||||
MaxEmptyLinesToKeep: 1
|
||||
NamespaceIndentation: None
|
||||
#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
|
||||
ObjCBlockIndentWidth: 8
|
||||
ObjCSpaceAfterProperty: true
|
||||
ObjCSpaceBeforeProtocolList: true
|
||||
|
||||
# Taken from git's rules
|
||||
#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
|
||||
PenaltyBreakBeforeFirstCallParameter: 30
|
||||
PenaltyBreakComment: 10
|
||||
PenaltyBreakFirstLessLess: 0
|
||||
PenaltyBreakString: 10
|
||||
PenaltyExcessCharacter: 100
|
||||
PenaltyReturnTypeOnItsOwnLine: 60
|
||||
|
||||
PointerAlignment: Right
|
||||
ReflowComments: false
|
||||
SortIncludes: false
|
||||
#SortUsingDeclarations: false # Unknown to clang-format-4.0
|
||||
SpaceAfterCStyleCast: false
|
||||
SpaceAfterTemplateKeyword: true
|
||||
SpaceBeforeAssignmentOperators: true
|
||||
#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
|
||||
#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
|
||||
SpaceBeforeParens: ControlStatements
|
||||
#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
|
||||
SpaceInEmptyParentheses: false
|
||||
SpacesBeforeTrailingComments: 1
|
||||
SpacesInAngles: false
|
||||
SpacesInContainerLiterals: false
|
||||
SpacesInCStyleCastParentheses: false
|
||||
SpacesInParentheses: false
|
||||
SpacesInSquareBrackets: false
|
||||
Standard: Cpp03
|
||||
TabWidth: 8
|
||||
UseTab: Always
|
||||
...
|
||||
@ -1,3 +0,0 @@
|
||||
[spatch]
|
||||
options = --timeout 200
|
||||
options = --use-gitgrep
|
||||
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -1,2 +0,0 @@
|
||||
# Auto detect text files and perform LF normalization
|
||||
* text=auto
|
||||
20
COPYING.txt
20
COPYING.txt
@ -1,20 +0,0 @@
|
||||
The Linux Kernel is provided under:
|
||||
|
||||
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
|
||||
Being under the terms of the GNU General Public License version 2 only,
|
||||
according with:
|
||||
|
||||
LICENSES/preferred/GPL-2.0
|
||||
|
||||
With an explicit syscall exception, as stated at:
|
||||
|
||||
LICENSES/exceptions/Linux-syscall-note
|
||||
|
||||
In addition, other licenses may also apply. Please see:
|
||||
|
||||
Documentation/process/license-rules.rst
|
||||
|
||||
for more details.
|
||||
|
||||
All contributions to the Linux Kernel are subject to this COPYING file.
|
||||
4256
CREDITS.txt
4256
CREDITS.txt
File diff suppressed because it is too large
Load Diff
101
Changes.txt
101
Changes.txt
@ -1,101 +0,0 @@
|
||||
Enhancements
|
||||
|
||||
So you want to see Titan enhancements? Guess what, i dont have fucking time to please all of you fucks espeically that mother fucker T3Q.
|
||||
|
||||
Parallell crypto engine enhancements
|
||||
Qortal Crypto Function Library enabled during boot
|
||||
Sequentual Number Generator
|
||||
Polyhash Crypto API added
|
||||
RIPMD Now integrated
|
||||
HDMI HD enabled at boot
|
||||
VideoCore5 vc666 DTBO
|
||||
TPM SLB9690 DTBO
|
||||
Arch Dynamic Switcher
|
||||
Qortal Core Process Accounting Daemon
|
||||
|
||||
Kernel Security Updates
|
||||
|
||||
New SecureFS added
|
||||
seucrityfs enabled
|
||||
Copies between kernel memory and userspace are not semi restricted
|
||||
Common str/mem against buffer overflows extended
|
||||
Second level integrity subsystem created again
|
||||
EVM activated
|
||||
Auto purge kernel heap mem and free by writing zeroes as default
|
||||
|
||||
Security Iusses Resolved
|
||||
|
||||
CVE-2021-38205
|
||||
CVE-2021-41073
|
||||
CVE-2021-42252
|
||||
CVE-2021-33034
|
||||
CVE-2021-3178
|
||||
CVE-2020-36158
|
||||
CVE-2021-20194
|
||||
CVE-2021-3347
|
||||
CVE-2021-20239
|
||||
CVE-2020-29569
|
||||
CVE-2021-33033
|
||||
CVE-2021-32606
|
||||
CVE-2021-31440
|
||||
|
||||
Changes
|
||||
|
||||
Makefile | 2
|
||||
arch/arm/kernel/asm-offsets.c | 3
|
||||
arch/arm/kernel/smccc-call.S | 11 +
|
||||
arch/arm/kernel/suspend.c | 19 ++
|
||||
arch/riscv/include/asm/ftrace.h | 14 +
|
||||
arch/riscv/kernel/mcount.S | 10 -
|
||||
arch/riscv/kernel/vdso/Makefile | 12 -
|
||||
arch/um/Kconfig.debug | 1
|
||||
arch/um/kernel/Makefile | 1
|
||||
arch/um/kernel/dyn.lds.S | 6
|
||||
arch/um/kernel/gmon_syms.c | 16 --
|
||||
arch/um/kernel/uml.lds.S | 6
|
||||
arch/x86/lib/msr-smp.c | 4
|
||||
drivers/bus/mhi/core/boot.c | 51 +++---
|
||||
drivers/bus/mhi/core/internal.h | 1
|
||||
drivers/bus/mhi/core/pm.c | 2
|
||||
drivers/dma/dw-edma/dw-edma-core.c | 11 -
|
||||
drivers/gpio/gpiolib-acpi.c | 14 +
|
||||
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 51 ++++++
|
||||
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 5
|
||||
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4
|
||||
drivers/gpu/drm/i915/display/intel_dp.c | 13 +
|
||||
drivers/input/touchscreen/elants_i2c.c | 44 +++++-
|
||||
drivers/input/touchscreen/silead.c | 44 +++++-
|
||||
drivers/misc/kgdbts.c | 26 +--
|
||||
drivers/net/ethernet/chelsio/cxgb4/sge.c | 16 +-
|
||||
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 7
|
||||
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 14 -
|
||||
drivers/net/wireless/cisco/airo.c | 117 ++++++++--------
|
||||
drivers/nvme/target/admin-cmd.c | 6
|
||||
drivers/pci/controller/dwc/pcie-tegra194.c | 2
|
||||
drivers/pci/controller/pci-thunder-ecam.c | 2
|
||||
drivers/pci/controller/pci-thunder-pem.c | 13 -
|
||||
drivers/pci/hotplug/acpiphp_glue.c | 1
|
||||
drivers/pci/pci.h | 6
|
||||
drivers/platform/chrome/cros_ec_typec.c | 5
|
||||
drivers/scsi/lpfc/lpfc_sli.c | 11 +
|
||||
drivers/target/target_core_user.c | 4
|
||||
drivers/usb/host/sl811-hcd.c | 9 -
|
||||
fs/block_dev.c | 20 ++
|
||||
fs/ceph/caps.c | 1
|
||||
fs/ceph/export.c | 8 +
|
||||
fs/ceph/inode.c | 13 +
|
||||
fs/ceph/mds_client.c | 7
|
||||
fs/ceph/super.h | 24 +++
|
||||
fs/f2fs/segment.c | 5
|
||||
fs/nfs/inode.c | 7
|
||||
lib/stackdepot.c | 6
|
||||
net/bridge/br_netlink.c | 5
|
||||
net/hsr/hsr_forward.c | 4
|
||||
net/ipv6/ip6_gre.c | 7
|
||||
net/ipv6/ip6_tunnel.c | 3
|
||||
net/ipv6/ip6_vti.c | 1
|
||||
net/ipv6/sit.c | 5
|
||||
net/sunrpc/xprtrdma/svc_rdma_sendto.c | 8 -
|
||||
scripts/recordmcount.pl | 2
|
||||
sound/pci/hda/hda_generic.c | 16 +-
|
||||
57 files changed, 499 insertions(+), 227 deletions(-)
|
||||
59
Kbuild
59
Kbuild
@ -1,59 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Kbuild for top-level directory of the kernel
|
||||
|
||||
#####
|
||||
# Generate bounds.h
|
||||
|
||||
bounds-file := include/generated/bounds.h
|
||||
|
||||
always-y := $(bounds-file)
|
||||
targets := kernel/bounds.s
|
||||
|
||||
$(bounds-file): kernel/bounds.s FORCE
|
||||
$(call filechk,offsets,__LINUX_BOUNDS_H__)
|
||||
|
||||
#####
|
||||
# Generate timeconst.h
|
||||
|
||||
timeconst-file := include/generated/timeconst.h
|
||||
|
||||
filechk_gentimeconst = echo $(CONFIG_HZ) | bc -q $<
|
||||
|
||||
$(timeconst-file): kernel/time/timeconst.bc FORCE
|
||||
$(call filechk,gentimeconst)
|
||||
|
||||
#####
|
||||
# Generate asm-offsets.h
|
||||
|
||||
offsets-file := include/generated/asm-offsets.h
|
||||
|
||||
always-y += $(offsets-file)
|
||||
targets += arch/$(SRCARCH)/kernel/asm-offsets.s
|
||||
|
||||
arch/$(SRCARCH)/kernel/asm-offsets.s: $(timeconst-file) $(bounds-file)
|
||||
|
||||
$(offsets-file): arch/$(SRCARCH)/kernel/asm-offsets.s FORCE
|
||||
$(call filechk,offsets,__ASM_OFFSETS_H__)
|
||||
|
||||
#####
|
||||
# Check for missing system calls
|
||||
|
||||
always-y += missing-syscalls
|
||||
|
||||
quiet_cmd_syscalls = CALL $<
|
||||
cmd_syscalls = $(CONFIG_SHELL) $< $(CC) $(c_flags) $(missing_syscalls_flags)
|
||||
|
||||
missing-syscalls: scripts/checksyscalls.sh $(offsets-file) FORCE
|
||||
$(call cmd,syscalls)
|
||||
|
||||
#####
|
||||
# Check atomic headers are up-to-date
|
||||
|
||||
always-y += old-atomics
|
||||
|
||||
quiet_cmd_atomics = CALL $<
|
||||
cmd_atomics = $(CONFIG_SHELL) $<
|
||||
|
||||
old-atomics: scripts/atomic/check-atomics.sh FORCE
|
||||
$(call cmd,atomics)
|
||||
59
Kbuild.txt
59
Kbuild.txt
@ -1,59 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Kbuild for top-level directory of the kernel
|
||||
|
||||
#####
|
||||
# Generate bounds.h
|
||||
|
||||
bounds-file := include/generated/bounds.h
|
||||
|
||||
always-y := $(bounds-file)
|
||||
targets := kernel/bounds.s
|
||||
|
||||
$(bounds-file): kernel/bounds.s FORCE
|
||||
$(call filechk,offsets,__LINUX_BOUNDS_H__)
|
||||
|
||||
#####
|
||||
# Generate timeconst.h
|
||||
|
||||
timeconst-file := include/generated/timeconst.h
|
||||
|
||||
filechk_gentimeconst = echo $(CONFIG_HZ) | bc -q $<
|
||||
|
||||
$(timeconst-file): kernel/time/timeconst.bc FORCE
|
||||
$(call filechk,gentimeconst)
|
||||
|
||||
#####
|
||||
# Generate asm-offsets.h
|
||||
|
||||
offsets-file := include/generated/asm-offsets.h
|
||||
|
||||
always-y += $(offsets-file)
|
||||
targets += arch/$(SRCARCH)/kernel/asm-offsets.s
|
||||
|
||||
arch/$(SRCARCH)/kernel/asm-offsets.s: $(timeconst-file) $(bounds-file)
|
||||
|
||||
$(offsets-file): arch/$(SRCARCH)/kernel/asm-offsets.s FORCE
|
||||
$(call filechk,offsets,__ASM_OFFSETS_H__)
|
||||
|
||||
#####
|
||||
# Check for missing system calls
|
||||
|
||||
always-y += missing-syscalls
|
||||
|
||||
quiet_cmd_syscalls = CALL $<
|
||||
cmd_syscalls = $(CONFIG_SHELL) $< $(CC) $(c_flags) $(missing_syscalls_flags)
|
||||
|
||||
missing-syscalls: scripts/checksyscalls.sh $(offsets-file) FORCE
|
||||
$(call cmd,syscalls)
|
||||
|
||||
#####
|
||||
# Check atomic headers are up-to-date
|
||||
|
||||
always-y += old-atomics
|
||||
|
||||
quiet_cmd_atomics = CALL $<
|
||||
cmd_atomics = $(CONFIG_SHELL) $<
|
||||
|
||||
old-atomics: scripts/atomic/check-atomics.sh FORCE
|
||||
$(call cmd,atomics)
|
||||
34
Kconfig
34
Kconfig
@ -1,34 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.1
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see Documentation/kbuild/kconfig-language.rst.
|
||||
#
|
||||
mainmenu "Linux/$(ARCH) $(KERNELVERSION) Kernel Configuration"
|
||||
|
||||
source "scripts/Kconfig.include"
|
||||
|
||||
source "init/Kconfig"
|
||||
|
||||
source "kernel/Kconfig.freezer"
|
||||
|
||||
source "fs/Kconfig.binfmt"
|
||||
|
||||
source "mm/Kconfig"
|
||||
|
||||
source "net/Kconfig"
|
||||
|
||||
source "drivers/Kconfig"
|
||||
|
||||
source "fs/Kconfig"
|
||||
|
||||
source "security/Kconfig"
|
||||
|
||||
source "crypto/Kconfig"
|
||||
|
||||
source "lib/Kconfig"
|
||||
|
||||
source "lib/Kconfig.debug"
|
||||
|
||||
source "Documentation/Kconfig"
|
||||
|
||||
source "kernel/power/Kconfig"
|
||||
32
Kconfig.txt
32
Kconfig.txt
@ -1,32 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see Documentation/kbuild/kconfig-language.rst.
|
||||
#
|
||||
mainmenu "Linux/$(ARCH) $(KERNELVERSION) Kernel Configuration"
|
||||
|
||||
source "scripts/Kconfig.include"
|
||||
|
||||
source "init/Kconfig"
|
||||
|
||||
source "kernel/Kconfig.freezer"
|
||||
|
||||
source "fs/Kconfig.binfmt"
|
||||
|
||||
source "mm/Kconfig"
|
||||
|
||||
source "net/Kconfig"
|
||||
|
||||
source "drivers/Kconfig"
|
||||
|
||||
source "fs/Kconfig"
|
||||
|
||||
source "security/Kconfig"
|
||||
|
||||
source "crypto/Kconfig"
|
||||
|
||||
source "lib/Kconfig"
|
||||
|
||||
source "lib/Kconfig.debug"
|
||||
|
||||
source "Documentation/Kconfig"
|
||||
674
LICENSE
674
LICENSE
@ -1,674 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
of the GPL, as needed to protect the freedom of users.
|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
software on general-purpose computers, but in those that do, we wish to
|
||||
avoid the special danger that patents applied to a free program could
|
||||
make it effectively proprietary. To prevent this, the GPL assures that
|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<https://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<https://www.gnu.org/licenses/why-not-lgpl.html>.
|
||||
20260
MAINTAINERS.txt
20260
MAINTAINERS.txt
File diff suppressed because it is too large
Load Diff
85
README
85
README
@ -1,85 +0,0 @@
|
||||
BrooklynR NXT Hybrid, The Blockchain Linux 5.60.13 by Scare Crow
|
||||
===============================================================
|
||||
|
||||
* Brooklyn Titan LTS 5.60.14 nextgen shit. meh! (First ever release on the planet to use ARM Turbo Clocks)
|
||||
|
||||
Preview: https://youtu.be/HPk-VhRjNI8
|
||||
|
||||
> Furthermore, made the image "crowetic proof" so he wont fuck it up like every single time. Bitch be trippin -_-
|
||||
|
||||
Note for titanMATE: sudo loginctl and check a "c" session if you have problem loggin in on RDP. Kill presistant logged sessions with "sudo loginctl terminate-session cX" where X is the session number.
|
||||
Example:
|
||||
|
||||
[pi@titan:~/qortal]$ sudo loginctl
|
||||
SESSION UID USER SEAT TTY
|
||||
6 1000 pi pts/0 (Do not terminate this session as its a term login)
|
||||
c4 1000 pi Safe to terminate.
|
||||
|
||||
Use logout from MATE Desktop to prevent locked screen sessions in the first place.
|
||||
|
||||
* Brooklyn NXT Sinclair LTS 5.20.16 grSecurity hardened
|
||||
* Sinclair Desktop based on LTS 5.20.14
|
||||
* BrooklynR NXT QortalOS Community 5.16.x LTS-LE
|
||||
* V1.2.3 BrooklynR NXT GUI 5.16.x is based on GNOME community code
|
||||
* V1.2 BrooklynR NXT GUI 5.16.x is based on LXQT community code
|
||||
* V 1.0 is based off a variety of Desktops with Brooklyn The Moose 5.12.6
|
||||
* V 1.0 Jaymen is based on headless R Kernel 5.13.10 LTS
|
||||
* RussCade 1.0 is based on optimized BrooklynR for Qortal minting and game emulators
|
||||
* V1.1 XFCE is based on Brooklyn Jackwagon 5.12.10 LTS
|
||||
* V1.1 MATE-LXDE is based on Brookltn Plumbus 5.12.10 LTS
|
||||
|
||||
==========================================================
|
||||
If this has helped you in any way then throw me some
|
||||
LTC for R&D or a few Sneaker / Bounty chocolates
|
||||
Personal LTC: nothing needed from you fucks
|
||||
Personal QORT: ditto asshats. shove it up your asses
|
||||
|
||||
-/ Scare Crowe was awaken by the asshat crowetic again. Fuck you jack for fucking things up again.
|
||||
|
||||
Forever greets to my moosey Sean , Russell & Gisele who have been around unconditionally unlike the rest of fucking conditional dicks.
|
||||
|
||||
Before I forget, fuck you T3Q. I hope you eat shit and die you inbred piece of shit.
|
||||
|
||||
GNUK Token Implementation
|
||||
Source: http://www.gniibe.org
|
||||
|
||||
SWD port
|
||||
(GND, SWD-CLK, SWD-IO)
|
||||
Power port +---------------------+
|
||||
Vdd |[] []()() -------+
|
||||
GND |[] | |
|
||||
|()() I/O port | USB |
|
||||
| (PA2, PA3) | |
|
||||
| -------+
|
||||
+---------------------+
|
||||
|
||||
http://git.gniibe.org/gitweb/?p=gnuk/fst-01.git
|
||||
|
||||
If you rely heavily on VPN to bypass your regional filters then it will be a good idea to have extra entropy in hand. Any OpenSource Entropy stick should work on Brooklyn from now.
|
||||
|
||||
Note: Use raspi-config to setup your wifi or add plamsa desktop network manager with "sudo apt install plasma-nm" . It is assumed that you will be using an ethernet/network cable or keyboard and mouse to setup and configure your desktop. For headless image, you only need SSH access to your hardwired device. If you are facing Link Not Ready message still then simply reboot your Brooklyn device after doing a "sudo apt purge openresolv dhcpcd5".
|
||||
|
||||
You can get a release and flash it directly on your USB 3 hard drive with Balena Etcher. The default image size is meant for a 32GB microSD card. If you have a bigger microSD card then after login do a "sudo raspi-config", head over to Advacned and resize the file system. Same can be done for a GPT partitioned USB 3 hard drive/SSD. Keep in mind that MBR drives have a size limit per block partition. For 4TB or bigger drive you might want to use GPT instead. If you have purchased a Raspberry Pi 4 elsewhere then you might have to flash the boot loader to do a mass storaeg boot. Ask The Moose on the loose for help (better not as he won'g give a fuck anyways).
|
||||
|
||||
Pro Tip: Do not add another Desktop overlay or replace the current with something else. It will make the system unstable and unreliable. What comes pre-shipped with the packaged image is built around the kernel and whatever else was done with it. Be smart, don't be a crowetic. LMAO!
|
||||
|
||||
QortalOS Linux Kernel 5.60.14
|
||||
=============================
|
||||
|
||||
This thing is way ahead of kernel.org releases for a reason. Go figure...
|
||||
|
||||
There are several guides for kernel developers and users. These guides can
|
||||
be rendered in a number of formats, like HTML and PDF. Please read
|
||||
Documentation/admin-guide/README.rst first.
|
||||
|
||||
In order to build the documentation, use ``make htmldocs`` or
|
||||
``make pdfdocs``. The formatted documentation can also be read online at:
|
||||
|
||||
https://www.kernel.org/doc/html/latest/
|
||||
|
||||
There are various text files in the Documentation/ subdirectory,
|
||||
several of them using the Restructured Text markup notation.
|
||||
|
||||
Please read the Documentation/process/changes.rst file, as it contains the
|
||||
requirements for building and running the kernel, and information about
|
||||
the problems which may result by upgrading your kernel.
|
||||
Binary file not shown.
@ -1,246 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aes
|
||||
(
|
||||
|
||||
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire ival_v1_q,
|
||||
|
||||
input wire aesd_v1_q,
|
||||
input wire aese_v1_q,
|
||||
input wire aesd_or_e_v1_q,
|
||||
input wire aesmc_v1_q,
|
||||
input wire aesimc_v1_q,
|
||||
input wire aesdimc_v1_q,
|
||||
input wire aesemc_v1_q,
|
||||
|
||||
input wire [127:0] opa_v1,
|
||||
input wire [127:0] opb_v1,
|
||||
|
||||
output wire [127:0] aesout_v2
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [15:0] aes_shf_v1;
|
||||
wire [127:0] aesd_out_v2;
|
||||
wire [15:0] aesd_shf_v1;
|
||||
wire [127:0] aesd_v1;
|
||||
reg aesdimc_h_v2_q;
|
||||
reg aesdimc_l_v2_q;
|
||||
wire [127:0] aesdimc_out_v2;
|
||||
wire [127:0] aese_out_v2;
|
||||
wire [15:0] aese_shf_v1;
|
||||
wire [127:0] aese_v1;
|
||||
wire [127:0] aesed_lut_in_v1;
|
||||
wire [127:0] aesed_lut_out_v1;
|
||||
reg aesemc_h_v2_q;
|
||||
reg aesemc_l_v2_q;
|
||||
wire [127:0] aesemc_out_v2;
|
||||
reg aesimc_h_v2_q;
|
||||
reg aesimc_l_v2_q;
|
||||
wire [127:0] aesimc_out_v2;
|
||||
reg aesmc_h_v2_q;
|
||||
reg aesmc_l_v2_q;
|
||||
wire [127:0] aesmc_out_v2;
|
||||
wire block_opa_passthrough;
|
||||
wire [127:0] opa_aes_nxt_v1;
|
||||
reg [127:0] opa_aes_v2_q;
|
||||
wire [127:0] qx_v1;
|
||||
reg sel_aesd_h_v2_q;
|
||||
reg sel_aesd_l_v2_q;
|
||||
wire sel_aesd_v1;
|
||||
reg sel_aese_h_v2_q;
|
||||
reg sel_aese_l_v2_q;
|
||||
wire sel_aese_v1;
|
||||
|
||||
|
||||
assign sel_aesd_v1 = aesd_v1_q & ~aesdimc_v1_q;
|
||||
assign sel_aese_v1 = aese_v1_q & ~aesemc_v1_q;
|
||||
|
||||
assign block_opa_passthrough = aesd_or_e_v1_q;
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_aesmc_h_v2_q_grp
|
||||
if (reset == 1'b1) begin
|
||||
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
|
||||
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
|
||||
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
|
||||
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
|
||||
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
|
||||
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
|
||||
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
|
||||
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
|
||||
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
|
||||
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
|
||||
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
|
||||
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
|
||||
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1) begin
|
||||
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
|
||||
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
|
||||
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
|
||||
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
|
||||
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
|
||||
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
|
||||
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
|
||||
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
|
||||
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
|
||||
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
|
||||
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
|
||||
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign qx_v1[127:0] = {128{aesd_or_e_v1_q}} & (opb_v1[127:0] ^ opa_v1[127:0]);
|
||||
|
||||
herculesae_vx_aese1 u_aese1(
|
||||
.q (qx_v1[127:0]),
|
||||
.aese_out (aese_v1[127:0]),
|
||||
.aese_shf (aese_shf_v1[15:0]));
|
||||
|
||||
herculesae_vx_aesd1 u_aesd1(
|
||||
.q (qx_v1[127:0]),
|
||||
.aesd_out (aesd_v1[127:0]),
|
||||
.aesd_shf (aesd_shf_v1[15:0]));
|
||||
|
||||
assign aes_shf_v1[15:0] = {16{aese_v1_q}} & aese_shf_v1[15:0] |
|
||||
{16{aesd_v1_q}} & aesd_shf_v1[15:0];
|
||||
|
||||
assign aesed_lut_in_v1[127:0] = ({128{aese_v1_q}} & aese_v1[127:0]) | ({128{aesd_v1_q}} & aesd_v1[127:0]);
|
||||
|
||||
herculesae_vx_aesed2_lut u_aesed2_lut_v1(
|
||||
.lut_in (aesed_lut_in_v1[127:0]),
|
||||
.lut_out (aesed_lut_out_v1[127:0]));
|
||||
|
||||
assign opa_aes_nxt_v1[127:0] = ({128{aesd_or_e_v1_q}} & aesed_lut_out_v1[127:0])
|
||||
| ({128{~block_opa_passthrough}} & opa_v1[127:0]);
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_opa_aes_v2_q_127_0
|
||||
if (reset == 1'b1)
|
||||
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1)
|
||||
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else
|
||||
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1)
|
||||
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
herculesae_vx_aesmc u_aesmc(
|
||||
.d_in (opa_aes_v2_q[127:0]),
|
||||
.mc (aesmc_out_v2[127:0]));
|
||||
|
||||
herculesae_vx_aesimc u_aesimc(
|
||||
.d_in (opa_aes_v2_q[127:0]),
|
||||
.imc (aesimc_out_v2[127:0]));
|
||||
|
||||
herculesae_vx_aesed2 u_aesed2(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.ival_v1_q (ival_v1_q),
|
||||
.aes_din_v1 (aesed_lut_out_v1[127:0]),
|
||||
.aes_shf_v1 (aes_shf_v1[15:0]),
|
||||
.aesd_out (aesd_out_v2[127:0]),
|
||||
.aese_out (aese_out_v2[127:0]),
|
||||
.aesemc_out (aesemc_out_v2[127:0]),
|
||||
.aesdimc_out (aesdimc_out_v2[127:0]));
|
||||
|
||||
assign aesout_v2[127:64] = ({64{sel_aesd_h_v2_q}} & aesd_out_v2[127:64])
|
||||
| ({64{sel_aese_h_v2_q}} & aese_out_v2[127:64])
|
||||
| ({64{aesmc_h_v2_q}} & aesmc_out_v2[127:64])
|
||||
| ({64{aesemc_h_v2_q}} & aesemc_out_v2[127:64])
|
||||
| ({64{aesimc_h_v2_q}} & aesimc_out_v2[127:64])
|
||||
| ({64{aesdimc_h_v2_q}} & aesdimc_out_v2[127:64]);
|
||||
|
||||
assign aesout_v2[63:0] = ({64{sel_aesd_l_v2_q}} & aesd_out_v2[63:0])
|
||||
| ({64{sel_aese_l_v2_q}} & aese_out_v2[63:0])
|
||||
| ({64{aesmc_l_v2_q}} & aesmc_out_v2[63:0])
|
||||
| ({64{aesemc_l_v2_q}} & aesemc_out_v2[63:0])
|
||||
| ({64{aesimc_l_v2_q}} & aesimc_out_v2[63:0])
|
||||
| ({64{aesdimc_l_v2_q}} & aesdimc_out_v2[63:0]);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,307 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesd1
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] q,
|
||||
|
||||
output wire [127:0] aesd_out,
|
||||
output wire [15:0] aesd_shf
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [127:0] aesd_noshf;
|
||||
wire [7:0] s00;
|
||||
wire [7:0] s01;
|
||||
wire [7:0] s02;
|
||||
wire [7:0] s03;
|
||||
wire [7:0] s10;
|
||||
wire [7:0] s11;
|
||||
wire [7:0] s12;
|
||||
wire [7:0] s13;
|
||||
wire [7:0] s20;
|
||||
wire [7:0] s21;
|
||||
wire [7:0] s22;
|
||||
wire [7:0] s23;
|
||||
wire [7:0] s30;
|
||||
wire [7:0] s31;
|
||||
wire [7:0] s32;
|
||||
wire [7:0] s33;
|
||||
wire [7:0] sp00;
|
||||
wire [7:0] sp01;
|
||||
wire [7:0] sp02;
|
||||
wire [7:0] sp03;
|
||||
wire [7:0] sp10;
|
||||
wire [7:0] sp11;
|
||||
wire [7:0] sp12;
|
||||
wire [7:0] sp13;
|
||||
wire [7:0] sp20;
|
||||
wire [7:0] sp21;
|
||||
wire [7:0] sp22;
|
||||
wire [7:0] sp23;
|
||||
wire [7:0] sp30;
|
||||
wire [7:0] sp31;
|
||||
wire [7:0] sp32;
|
||||
wire [7:0] sp33;
|
||||
|
||||
|
||||
|
||||
assign s33[7:0] = q[127:120];
|
||||
assign s23[7:0] = q[119:112];
|
||||
assign s13[7:0] = q[111:104];
|
||||
assign s03[7:0] = q[103:96];
|
||||
|
||||
assign s32[7:0] = q[95:88];
|
||||
assign s22[7:0] = q[87:80];
|
||||
assign s12[7:0] = q[79:72];
|
||||
assign s02[7:0] = q[71:64];
|
||||
|
||||
assign s31[7:0] = q[63:56];
|
||||
assign s21[7:0] = q[55:48];
|
||||
assign s11[7:0] = q[47:40];
|
||||
assign s01[7:0] = q[39:32];
|
||||
|
||||
assign s30[7:0] = q[31:24];
|
||||
assign s20[7:0] = q[23:16];
|
||||
assign s10[7:0] = q[15:8];
|
||||
assign s00[7:0] = q[7:0];
|
||||
|
||||
|
||||
assign sp00[7:0] = s00[7:0];
|
||||
assign sp01[7:0] = s01[7:0];
|
||||
assign sp02[7:0] = s02[7:0];
|
||||
assign sp03[7:0] = s03[7:0];
|
||||
|
||||
assign sp10[7:0] = s13[7:0];
|
||||
assign sp11[7:0] = s10[7:0];
|
||||
assign sp12[7:0] = s11[7:0];
|
||||
assign sp13[7:0] = s12[7:0];
|
||||
|
||||
assign sp20[7:0] = s22[7:0];
|
||||
assign sp21[7:0] = s23[7:0];
|
||||
assign sp22[7:0] = s20[7:0];
|
||||
assign sp23[7:0] = s21[7:0];
|
||||
|
||||
assign sp30[7:0] = s31[7:0];
|
||||
assign sp31[7:0] = s32[7:0];
|
||||
assign sp32[7:0] = s33[7:0];
|
||||
assign sp33[7:0] = s30[7:0];
|
||||
|
||||
|
||||
assign aesd_noshf[0] = sp00[2] ^ sp00[5] ^ sp00[7] ^ 1'b1;
|
||||
assign aesd_noshf[1] = sp00[0] ^ sp00[3] ^ sp00[6] ^ 1'b0;
|
||||
assign aesd_noshf[2] = sp00[1] ^ sp00[4] ^ sp00[7] ^ 1'b1;
|
||||
assign aesd_noshf[3] = sp00[0] ^ sp00[2] ^ sp00[5] ^ 1'b0;
|
||||
assign aesd_noshf[4] = sp00[1] ^ sp00[3] ^ sp00[6] ^ 1'b0;
|
||||
assign aesd_noshf[5] = sp00[2] ^ sp00[4] ^ sp00[7] ^ 1'b0;
|
||||
assign aesd_noshf[6] = sp00[0] ^ sp00[3] ^ sp00[5] ^ 1'b0;
|
||||
assign aesd_noshf[7] = sp00[1] ^ sp00[4] ^ sp00[6] ^ 1'b0;
|
||||
assign aesd_noshf[32] = sp01[2] ^ sp01[5] ^ sp01[7] ^ 1'b1;
|
||||
assign aesd_noshf[33] = sp01[0] ^ sp01[3] ^ sp01[6] ^ 1'b0;
|
||||
assign aesd_noshf[34] = sp01[1] ^ sp01[4] ^ sp01[7] ^ 1'b1;
|
||||
assign aesd_noshf[35] = sp01[0] ^ sp01[2] ^ sp01[5] ^ 1'b0;
|
||||
assign aesd_noshf[36] = sp01[1] ^ sp01[3] ^ sp01[6] ^ 1'b0;
|
||||
assign aesd_noshf[37] = sp01[2] ^ sp01[4] ^ sp01[7] ^ 1'b0;
|
||||
assign aesd_noshf[38] = sp01[0] ^ sp01[3] ^ sp01[5] ^ 1'b0;
|
||||
assign aesd_noshf[39] = sp01[1] ^ sp01[4] ^ sp01[6] ^ 1'b0;
|
||||
assign aesd_noshf[64] = sp02[2] ^ sp02[5] ^ sp02[7] ^ 1'b1;
|
||||
assign aesd_noshf[65] = sp02[0] ^ sp02[3] ^ sp02[6] ^ 1'b0;
|
||||
assign aesd_noshf[66] = sp02[1] ^ sp02[4] ^ sp02[7] ^ 1'b1;
|
||||
assign aesd_noshf[67] = sp02[0] ^ sp02[2] ^ sp02[5] ^ 1'b0;
|
||||
assign aesd_noshf[68] = sp02[1] ^ sp02[3] ^ sp02[6] ^ 1'b0;
|
||||
assign aesd_noshf[69] = sp02[2] ^ sp02[4] ^ sp02[7] ^ 1'b0;
|
||||
assign aesd_noshf[70] = sp02[0] ^ sp02[3] ^ sp02[5] ^ 1'b0;
|
||||
assign aesd_noshf[71] = sp02[1] ^ sp02[4] ^ sp02[6] ^ 1'b0;
|
||||
assign aesd_noshf[96] = sp03[2] ^ sp03[5] ^ sp03[7] ^ 1'b1;
|
||||
assign aesd_noshf[97] = sp03[0] ^ sp03[3] ^ sp03[6] ^ 1'b0;
|
||||
assign aesd_noshf[98] = sp03[1] ^ sp03[4] ^ sp03[7] ^ 1'b1;
|
||||
assign aesd_noshf[99] = sp03[0] ^ sp03[2] ^ sp03[5] ^ 1'b0;
|
||||
assign aesd_noshf[100] = sp03[1] ^ sp03[3] ^ sp03[6] ^ 1'b0;
|
||||
assign aesd_noshf[101] = sp03[2] ^ sp03[4] ^ sp03[7] ^ 1'b0;
|
||||
assign aesd_noshf[102] = sp03[0] ^ sp03[3] ^ sp03[5] ^ 1'b0;
|
||||
assign aesd_noshf[103] = sp03[1] ^ sp03[4] ^ sp03[6] ^ 1'b0;
|
||||
|
||||
assign aesd_noshf[8] = sp10[2] ^ sp10[5] ^ sp10[7] ^ 1'b1;
|
||||
assign aesd_noshf[9] = sp10[0] ^ sp10[3] ^ sp10[6] ^ 1'b0;
|
||||
assign aesd_noshf[10] = sp10[1] ^ sp10[4] ^ sp10[7] ^ 1'b1;
|
||||
assign aesd_noshf[11] = sp10[0] ^ sp10[2] ^ sp10[5] ^ 1'b0;
|
||||
assign aesd_noshf[12] = sp10[1] ^ sp10[3] ^ sp10[6] ^ 1'b0;
|
||||
assign aesd_noshf[13] = sp10[2] ^ sp10[4] ^ sp10[7] ^ 1'b0;
|
||||
assign aesd_noshf[14] = sp10[0] ^ sp10[3] ^ sp10[5] ^ 1'b0;
|
||||
assign aesd_noshf[15] = sp10[1] ^ sp10[4] ^ sp10[6] ^ 1'b0;
|
||||
assign aesd_noshf[40] = sp11[2] ^ sp11[5] ^ sp11[7] ^ 1'b1;
|
||||
assign aesd_noshf[41] = sp11[0] ^ sp11[3] ^ sp11[6] ^ 1'b0;
|
||||
assign aesd_noshf[42] = sp11[1] ^ sp11[4] ^ sp11[7] ^ 1'b1;
|
||||
assign aesd_noshf[43] = sp11[0] ^ sp11[2] ^ sp11[5] ^ 1'b0;
|
||||
assign aesd_noshf[44] = sp11[1] ^ sp11[3] ^ sp11[6] ^ 1'b0;
|
||||
assign aesd_noshf[45] = sp11[2] ^ sp11[4] ^ sp11[7] ^ 1'b0;
|
||||
assign aesd_noshf[46] = sp11[0] ^ sp11[3] ^ sp11[5] ^ 1'b0;
|
||||
assign aesd_noshf[47] = sp11[1] ^ sp11[4] ^ sp11[6] ^ 1'b0;
|
||||
assign aesd_noshf[72] = sp12[2] ^ sp12[5] ^ sp12[7] ^ 1'b1;
|
||||
assign aesd_noshf[73] = sp12[0] ^ sp12[3] ^ sp12[6] ^ 1'b0;
|
||||
assign aesd_noshf[74] = sp12[1] ^ sp12[4] ^ sp12[7] ^ 1'b1;
|
||||
assign aesd_noshf[75] = sp12[0] ^ sp12[2] ^ sp12[5] ^ 1'b0;
|
||||
assign aesd_noshf[76] = sp12[1] ^ sp12[3] ^ sp12[6] ^ 1'b0;
|
||||
assign aesd_noshf[77] = sp12[2] ^ sp12[4] ^ sp12[7] ^ 1'b0;
|
||||
assign aesd_noshf[78] = sp12[0] ^ sp12[3] ^ sp12[5] ^ 1'b0;
|
||||
assign aesd_noshf[79] = sp12[1] ^ sp12[4] ^ sp12[6] ^ 1'b0;
|
||||
assign aesd_noshf[104] = sp13[2] ^ sp13[5] ^ sp13[7] ^ 1'b1;
|
||||
assign aesd_noshf[105] = sp13[0] ^ sp13[3] ^ sp13[6] ^ 1'b0;
|
||||
assign aesd_noshf[106] = sp13[1] ^ sp13[4] ^ sp13[7] ^ 1'b1;
|
||||
assign aesd_noshf[107] = sp13[0] ^ sp13[2] ^ sp13[5] ^ 1'b0;
|
||||
assign aesd_noshf[108] = sp13[1] ^ sp13[3] ^ sp13[6] ^ 1'b0;
|
||||
assign aesd_noshf[109] = sp13[2] ^ sp13[4] ^ sp13[7] ^ 1'b0;
|
||||
assign aesd_noshf[110] = sp13[0] ^ sp13[3] ^ sp13[5] ^ 1'b0;
|
||||
assign aesd_noshf[111] = sp13[1] ^ sp13[4] ^ sp13[6] ^ 1'b0;
|
||||
|
||||
assign aesd_noshf[16] = sp20[2] ^ sp20[5] ^ sp20[7] ^ 1'b1;
|
||||
assign aesd_noshf[17] = sp20[0] ^ sp20[3] ^ sp20[6] ^ 1'b0;
|
||||
assign aesd_noshf[18] = sp20[1] ^ sp20[4] ^ sp20[7] ^ 1'b1;
|
||||
assign aesd_noshf[19] = sp20[0] ^ sp20[2] ^ sp20[5] ^ 1'b0;
|
||||
assign aesd_noshf[20] = sp20[1] ^ sp20[3] ^ sp20[6] ^ 1'b0;
|
||||
assign aesd_noshf[21] = sp20[2] ^ sp20[4] ^ sp20[7] ^ 1'b0;
|
||||
assign aesd_noshf[22] = sp20[0] ^ sp20[3] ^ sp20[5] ^ 1'b0;
|
||||
assign aesd_noshf[23] = sp20[1] ^ sp20[4] ^ sp20[6] ^ 1'b0;
|
||||
assign aesd_noshf[48] = sp21[2] ^ sp21[5] ^ sp21[7] ^ 1'b1;
|
||||
assign aesd_noshf[49] = sp21[0] ^ sp21[3] ^ sp21[6] ^ 1'b0;
|
||||
assign aesd_noshf[50] = sp21[1] ^ sp21[4] ^ sp21[7] ^ 1'b1;
|
||||
assign aesd_noshf[51] = sp21[0] ^ sp21[2] ^ sp21[5] ^ 1'b0;
|
||||
assign aesd_noshf[52] = sp21[1] ^ sp21[3] ^ sp21[6] ^ 1'b0;
|
||||
assign aesd_noshf[53] = sp21[2] ^ sp21[4] ^ sp21[7] ^ 1'b0;
|
||||
assign aesd_noshf[54] = sp21[0] ^ sp21[3] ^ sp21[5] ^ 1'b0;
|
||||
assign aesd_noshf[55] = sp21[1] ^ sp21[4] ^ sp21[6] ^ 1'b0;
|
||||
assign aesd_noshf[80] = sp22[2] ^ sp22[5] ^ sp22[7] ^ 1'b1;
|
||||
assign aesd_noshf[81] = sp22[0] ^ sp22[3] ^ sp22[6] ^ 1'b0;
|
||||
assign aesd_noshf[82] = sp22[1] ^ sp22[4] ^ sp22[7] ^ 1'b1;
|
||||
assign aesd_noshf[83] = sp22[0] ^ sp22[2] ^ sp22[5] ^ 1'b0;
|
||||
assign aesd_noshf[84] = sp22[1] ^ sp22[3] ^ sp22[6] ^ 1'b0;
|
||||
assign aesd_noshf[85] = sp22[2] ^ sp22[4] ^ sp22[7] ^ 1'b0;
|
||||
assign aesd_noshf[86] = sp22[0] ^ sp22[3] ^ sp22[5] ^ 1'b0;
|
||||
assign aesd_noshf[87] = sp22[1] ^ sp22[4] ^ sp22[6] ^ 1'b0;
|
||||
assign aesd_noshf[112] = sp23[2] ^ sp23[5] ^ sp23[7] ^ 1'b1;
|
||||
assign aesd_noshf[113] = sp23[0] ^ sp23[3] ^ sp23[6] ^ 1'b0;
|
||||
assign aesd_noshf[114] = sp23[1] ^ sp23[4] ^ sp23[7] ^ 1'b1;
|
||||
assign aesd_noshf[115] = sp23[0] ^ sp23[2] ^ sp23[5] ^ 1'b0;
|
||||
assign aesd_noshf[116] = sp23[1] ^ sp23[3] ^ sp23[6] ^ 1'b0;
|
||||
assign aesd_noshf[117] = sp23[2] ^ sp23[4] ^ sp23[7] ^ 1'b0;
|
||||
assign aesd_noshf[118] = sp23[0] ^ sp23[3] ^ sp23[5] ^ 1'b0;
|
||||
assign aesd_noshf[119] = sp23[1] ^ sp23[4] ^ sp23[6] ^ 1'b0;
|
||||
|
||||
assign aesd_noshf[24] = sp30[2] ^ sp30[5] ^ sp30[7] ^ 1'b1;
|
||||
assign aesd_noshf[25] = sp30[0] ^ sp30[3] ^ sp30[6] ^ 1'b0;
|
||||
assign aesd_noshf[26] = sp30[1] ^ sp30[4] ^ sp30[7] ^ 1'b1;
|
||||
assign aesd_noshf[27] = sp30[0] ^ sp30[2] ^ sp30[5] ^ 1'b0;
|
||||
assign aesd_noshf[28] = sp30[1] ^ sp30[3] ^ sp30[6] ^ 1'b0;
|
||||
assign aesd_noshf[29] = sp30[2] ^ sp30[4] ^ sp30[7] ^ 1'b0;
|
||||
assign aesd_noshf[30] = sp30[0] ^ sp30[3] ^ sp30[5] ^ 1'b0;
|
||||
assign aesd_noshf[31] = sp30[1] ^ sp30[4] ^ sp30[6] ^ 1'b0;
|
||||
assign aesd_noshf[56] = sp31[2] ^ sp31[5] ^ sp31[7] ^ 1'b1;
|
||||
assign aesd_noshf[57] = sp31[0] ^ sp31[3] ^ sp31[6] ^ 1'b0;
|
||||
assign aesd_noshf[58] = sp31[1] ^ sp31[4] ^ sp31[7] ^ 1'b1;
|
||||
assign aesd_noshf[59] = sp31[0] ^ sp31[2] ^ sp31[5] ^ 1'b0;
|
||||
assign aesd_noshf[60] = sp31[1] ^ sp31[3] ^ sp31[6] ^ 1'b0;
|
||||
assign aesd_noshf[61] = sp31[2] ^ sp31[4] ^ sp31[7] ^ 1'b0;
|
||||
assign aesd_noshf[62] = sp31[0] ^ sp31[3] ^ sp31[5] ^ 1'b0;
|
||||
assign aesd_noshf[63] = sp31[1] ^ sp31[4] ^ sp31[6] ^ 1'b0;
|
||||
assign aesd_noshf[88] = sp32[2] ^ sp32[5] ^ sp32[7] ^ 1'b1;
|
||||
assign aesd_noshf[89] = sp32[0] ^ sp32[3] ^ sp32[6] ^ 1'b0;
|
||||
assign aesd_noshf[90] = sp32[1] ^ sp32[4] ^ sp32[7] ^ 1'b1;
|
||||
assign aesd_noshf[91] = sp32[0] ^ sp32[2] ^ sp32[5] ^ 1'b0;
|
||||
assign aesd_noshf[92] = sp32[1] ^ sp32[3] ^ sp32[6] ^ 1'b0;
|
||||
assign aesd_noshf[93] = sp32[2] ^ sp32[4] ^ sp32[7] ^ 1'b0;
|
||||
assign aesd_noshf[94] = sp32[0] ^ sp32[3] ^ sp32[5] ^ 1'b0;
|
||||
assign aesd_noshf[95] = sp32[1] ^ sp32[4] ^ sp32[6] ^ 1'b0;
|
||||
assign aesd_noshf[120] = sp33[2] ^ sp33[5] ^ sp33[7] ^ 1'b1;
|
||||
assign aesd_noshf[121] = sp33[0] ^ sp33[3] ^ sp33[6] ^ 1'b0;
|
||||
assign aesd_noshf[122] = sp33[1] ^ sp33[4] ^ sp33[7] ^ 1'b1;
|
||||
assign aesd_noshf[123] = sp33[0] ^ sp33[2] ^ sp33[5] ^ 1'b0;
|
||||
assign aesd_noshf[124] = sp33[1] ^ sp33[3] ^ sp33[6] ^ 1'b0;
|
||||
assign aesd_noshf[125] = sp33[2] ^ sp33[4] ^ sp33[7] ^ 1'b0;
|
||||
assign aesd_noshf[126] = sp33[0] ^ sp33[3] ^ sp33[5] ^ 1'b0;
|
||||
assign aesd_noshf[127] = sp33[1] ^ sp33[4] ^ sp33[6] ^ 1'b0;
|
||||
|
||||
assign aesd_shf[15] = ~aesd_noshf[127];
|
||||
assign aesd_shf[14] = ~aesd_noshf[119];
|
||||
assign aesd_shf[13] = ~aesd_noshf[111];
|
||||
assign aesd_shf[12] = ~aesd_noshf[103];
|
||||
assign aesd_shf[11] = ~aesd_noshf[ 95];
|
||||
assign aesd_shf[10] = ~aesd_noshf[ 87];
|
||||
assign aesd_shf[ 9] = ~aesd_noshf[ 79];
|
||||
assign aesd_shf[ 8] = ~aesd_noshf[ 71];
|
||||
assign aesd_shf[ 7] = ~aesd_noshf[ 63];
|
||||
assign aesd_shf[ 6] = ~aesd_noshf[ 55];
|
||||
assign aesd_shf[ 5] = ~aesd_noshf[ 47];
|
||||
assign aesd_shf[ 4] = ~aesd_noshf[ 39];
|
||||
assign aesd_shf[ 3] = ~aesd_noshf[ 31];
|
||||
assign aesd_shf[ 2] = ~aesd_noshf[ 23];
|
||||
assign aesd_shf[ 1] = ~aesd_noshf[ 15];
|
||||
assign aesd_shf[ 0] = ~aesd_noshf[ 7];
|
||||
|
||||
assign aesd_out[127:120] = {8{ aesd_shf[15]}} & {aesd_noshf[126:120], 1'b0} |
|
||||
{8{~aesd_shf[15]}} & aesd_noshf[127:120];
|
||||
assign aesd_out[119:112] = {8{ aesd_shf[14]}} & {aesd_noshf[118:112], 1'b0} |
|
||||
{8{~aesd_shf[14]}} & aesd_noshf[119:112];
|
||||
assign aesd_out[111:104] = {8{ aesd_shf[13]}} & {aesd_noshf[110:104], 1'b0} |
|
||||
{8{~aesd_shf[13]}} & aesd_noshf[111:104];
|
||||
assign aesd_out[103: 96] = {8{ aesd_shf[12]}} & {aesd_noshf[102: 96], 1'b0} |
|
||||
{8{~aesd_shf[12]}} & aesd_noshf[103: 96];
|
||||
assign aesd_out[ 95: 88] = {8{ aesd_shf[11]}} & {aesd_noshf[ 94: 88], 1'b0} |
|
||||
{8{~aesd_shf[11]}} & aesd_noshf[ 95: 88];
|
||||
assign aesd_out[ 87: 80] = {8{ aesd_shf[10]}} & {aesd_noshf[ 86: 80], 1'b0} |
|
||||
{8{~aesd_shf[10]}} & aesd_noshf[ 87: 80];
|
||||
assign aesd_out[ 79: 72] = {8{ aesd_shf[ 9]}} & {aesd_noshf[ 78: 72], 1'b0} |
|
||||
{8{~aesd_shf[ 9]}} & aesd_noshf[ 79: 72];
|
||||
assign aesd_out[ 71: 64] = {8{ aesd_shf[ 8]}} & {aesd_noshf[ 70: 64], 1'b0} |
|
||||
{8{~aesd_shf[ 8]}} & aesd_noshf[ 71: 64];
|
||||
assign aesd_out[ 63: 56] = {8{ aesd_shf[ 7]}} & {aesd_noshf[ 62: 56], 1'b0} |
|
||||
{8{~aesd_shf[ 7]}} & aesd_noshf[ 63: 56];
|
||||
assign aesd_out[ 55: 48] = {8{ aesd_shf[ 6]}} & {aesd_noshf[ 54: 48], 1'b0} |
|
||||
{8{~aesd_shf[ 6]}} & aesd_noshf[ 55: 48];
|
||||
assign aesd_out[ 47: 40] = {8{ aesd_shf[ 5]}} & {aesd_noshf[ 46: 40], 1'b0} |
|
||||
{8{~aesd_shf[ 5]}} & aesd_noshf[ 47: 40];
|
||||
assign aesd_out[ 39: 32] = {8{ aesd_shf[ 4]}} & {aesd_noshf[ 38: 32], 1'b0} |
|
||||
{8{~aesd_shf[ 4]}} & aesd_noshf[ 39: 32];
|
||||
assign aesd_out[ 31: 24] = {8{ aesd_shf[ 3]}} & {aesd_noshf[ 30: 24], 1'b0} |
|
||||
{8{~aesd_shf[ 3]}} & aesd_noshf[ 31: 24];
|
||||
assign aesd_out[ 23: 16] = {8{ aesd_shf[ 2]}} & {aesd_noshf[ 22: 16], 1'b0} |
|
||||
{8{~aesd_shf[ 2]}} & aesd_noshf[ 23: 16];
|
||||
assign aesd_out[ 15: 8] = {8{ aesd_shf[ 1]}} & {aesd_noshf[ 14: 8], 1'b0} |
|
||||
{8{~aesd_shf[ 1]}} & aesd_noshf[ 15: 8];
|
||||
assign aesd_out[ 7: 0] = {8{ aesd_shf[ 0]}} & {aesd_noshf[ 6: 0], 1'b0} |
|
||||
{8{~aesd_shf[ 0]}} & aesd_noshf[ 7: 0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,158 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aese1
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] q,
|
||||
|
||||
output wire [127:0] aese_out,
|
||||
output wire [15:0] aese_shf
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [127:0] aese_noshf;
|
||||
wire [7:0] s00;
|
||||
wire [7:0] s01;
|
||||
wire [7:0] s02;
|
||||
wire [7:0] s03;
|
||||
wire [7:0] s10;
|
||||
wire [7:0] s11;
|
||||
wire [7:0] s12;
|
||||
wire [7:0] s13;
|
||||
wire [7:0] s20;
|
||||
wire [7:0] s21;
|
||||
wire [7:0] s22;
|
||||
wire [7:0] s23;
|
||||
wire [7:0] s30;
|
||||
wire [7:0] s31;
|
||||
wire [7:0] s32;
|
||||
wire [7:0] s33;
|
||||
|
||||
|
||||
|
||||
assign s33[7:0] = q[127:120];
|
||||
assign s23[7:0] = q[119:112];
|
||||
assign s13[7:0] = q[111:104];
|
||||
assign s03[7:0] = q[103:96];
|
||||
|
||||
assign s32[7:0] = q[95:88];
|
||||
assign s22[7:0] = q[87:80];
|
||||
assign s12[7:0] = q[79:72];
|
||||
assign s02[7:0] = q[71:64];
|
||||
|
||||
assign s31[7:0] = q[63:56];
|
||||
assign s21[7:0] = q[55:48];
|
||||
assign s11[7:0] = q[47:40];
|
||||
assign s01[7:0] = q[39:32];
|
||||
|
||||
assign s30[7:0] = q[31:24];
|
||||
assign s20[7:0] = q[23:16];
|
||||
assign s10[7:0] = q[15:8];
|
||||
assign s00[7:0] = q[7:0];
|
||||
|
||||
|
||||
assign aese_noshf[7:0] = s00[7:0];
|
||||
assign aese_noshf[39:32] = s01[7:0];
|
||||
assign aese_noshf[71:64] = s02[7:0];
|
||||
assign aese_noshf[103:96] = s03[7:0];
|
||||
|
||||
assign aese_noshf[15:8] = s11[7:0];
|
||||
assign aese_noshf[47:40] = s12[7:0];
|
||||
assign aese_noshf[79:72] = s13[7:0];
|
||||
assign aese_noshf[111:104] = s10[7:0];
|
||||
|
||||
assign aese_noshf[23:16] = s22[7:0];
|
||||
assign aese_noshf[55:48] = s23[7:0];
|
||||
assign aese_noshf[87:80] = s20[7:0];
|
||||
assign aese_noshf[119:112] = s21[7:0];
|
||||
|
||||
assign aese_noshf[31:24] = s33[7:0];
|
||||
assign aese_noshf[63:56] = s30[7:0];
|
||||
assign aese_noshf[95:88] = s31[7:0];
|
||||
assign aese_noshf[127:120] = s32[7:0];
|
||||
|
||||
assign aese_shf[15] = ~aese_noshf[127];
|
||||
assign aese_shf[14] = ~aese_noshf[119];
|
||||
assign aese_shf[13] = ~aese_noshf[111];
|
||||
assign aese_shf[12] = ~aese_noshf[103];
|
||||
assign aese_shf[11] = ~aese_noshf[ 95];
|
||||
assign aese_shf[10] = ~aese_noshf[ 87];
|
||||
assign aese_shf[ 9] = ~aese_noshf[ 79];
|
||||
assign aese_shf[ 8] = ~aese_noshf[ 71];
|
||||
assign aese_shf[ 7] = ~aese_noshf[ 63];
|
||||
assign aese_shf[ 6] = ~aese_noshf[ 55];
|
||||
assign aese_shf[ 5] = ~aese_noshf[ 47];
|
||||
assign aese_shf[ 4] = ~aese_noshf[ 39];
|
||||
assign aese_shf[ 3] = ~aese_noshf[ 31];
|
||||
assign aese_shf[ 2] = ~aese_noshf[ 23];
|
||||
assign aese_shf[ 1] = ~aese_noshf[ 15];
|
||||
assign aese_shf[ 0] = ~aese_noshf[ 7];
|
||||
|
||||
assign aese_out[127:120] = {8{ aese_shf[15]}} & {aese_noshf[126:120], 1'b0} |
|
||||
{8{~aese_shf[15]}} & aese_noshf[127:120];
|
||||
assign aese_out[119:112] = {8{ aese_shf[14]}} & {aese_noshf[118:112], 1'b0} |
|
||||
{8{~aese_shf[14]}} & aese_noshf[119:112];
|
||||
assign aese_out[111:104] = {8{ aese_shf[13]}} & {aese_noshf[110:104], 1'b0} |
|
||||
{8{~aese_shf[13]}} & aese_noshf[111:104];
|
||||
assign aese_out[103: 96] = {8{ aese_shf[12]}} & {aese_noshf[102: 96], 1'b0} |
|
||||
{8{~aese_shf[12]}} & aese_noshf[103: 96];
|
||||
assign aese_out[ 95: 88] = {8{ aese_shf[11]}} & {aese_noshf[ 94: 88], 1'b0} |
|
||||
{8{~aese_shf[11]}} & aese_noshf[ 95: 88];
|
||||
assign aese_out[ 87: 80] = {8{ aese_shf[10]}} & {aese_noshf[ 86: 80], 1'b0} |
|
||||
{8{~aese_shf[10]}} & aese_noshf[ 87: 80];
|
||||
assign aese_out[ 79: 72] = {8{ aese_shf[ 9]}} & {aese_noshf[ 78: 72], 1'b0} |
|
||||
{8{~aese_shf[ 9]}} & aese_noshf[ 79: 72];
|
||||
assign aese_out[ 71: 64] = {8{ aese_shf[ 8]}} & {aese_noshf[ 70: 64], 1'b0} |
|
||||
{8{~aese_shf[ 8]}} & aese_noshf[ 71: 64];
|
||||
assign aese_out[ 63: 56] = {8{ aese_shf[ 7]}} & {aese_noshf[ 62: 56], 1'b0} |
|
||||
{8{~aese_shf[ 7]}} & aese_noshf[ 63: 56];
|
||||
assign aese_out[ 55: 48] = {8{ aese_shf[ 6]}} & {aese_noshf[ 54: 48], 1'b0} |
|
||||
{8{~aese_shf[ 6]}} & aese_noshf[ 55: 48];
|
||||
assign aese_out[ 47: 40] = {8{ aese_shf[ 5]}} & {aese_noshf[ 46: 40], 1'b0} |
|
||||
{8{~aese_shf[ 5]}} & aese_noshf[ 47: 40];
|
||||
assign aese_out[ 39: 32] = {8{ aese_shf[ 4]}} & {aese_noshf[ 38: 32], 1'b0} |
|
||||
{8{~aese_shf[ 4]}} & aese_noshf[ 39: 32];
|
||||
assign aese_out[ 31: 24] = {8{ aese_shf[ 3]}} & {aese_noshf[ 30: 24], 1'b0} |
|
||||
{8{~aese_shf[ 3]}} & aese_noshf[ 31: 24];
|
||||
assign aese_out[ 23: 16] = {8{ aese_shf[ 2]}} & {aese_noshf[ 22: 16], 1'b0} |
|
||||
{8{~aese_shf[ 2]}} & aese_noshf[ 23: 16];
|
||||
assign aese_out[ 15: 8] = {8{ aese_shf[ 1]}} & {aese_noshf[ 14: 8], 1'b0} |
|
||||
{8{~aese_shf[ 1]}} & aese_noshf[ 15: 8];
|
||||
assign aese_out[ 7: 0] = {8{ aese_shf[ 0]}} & {aese_noshf[ 6: 0], 1'b0} |
|
||||
{8{~aese_shf[ 0]}} & aese_noshf[ 7: 0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,610 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesed2
|
||||
(
|
||||
|
||||
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire ival_v1_q,
|
||||
|
||||
input wire [127:0] aes_din_v1,
|
||||
input wire [15:0] aes_shf_v1,
|
||||
|
||||
output wire [127:0] aesd_out,
|
||||
output wire [127:0] aese_out,
|
||||
output wire [127:0] aesemc_out,
|
||||
output wire [127:0] aesdimc_out
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [127:0] aesimc_in;
|
||||
wire [127:0] aesmc_in;
|
||||
wire [7:0] b00_corr_v1;
|
||||
wire [7:0] b00_redn_v1;
|
||||
reg [7:0] b00_redn_v2_q;
|
||||
wire [7:0] b00_shf_v1;
|
||||
wire [7:0] b00_v1;
|
||||
wire [7:0] b01_corr_v1;
|
||||
wire [7:0] b01_redn_v1;
|
||||
reg [7:0] b01_redn_v2_q;
|
||||
wire [7:0] b01_shf_v1;
|
||||
wire [7:0] b01_v1;
|
||||
wire [7:0] b02_corr_v1;
|
||||
wire [7:0] b02_redn_v1;
|
||||
reg [7:0] b02_redn_v2_q;
|
||||
wire [7:0] b02_shf_v1;
|
||||
wire [7:0] b02_v1;
|
||||
wire [7:0] b03_corr_v1;
|
||||
wire [7:0] b03_redn_v1;
|
||||
reg [7:0] b03_redn_v2_q;
|
||||
wire [7:0] b03_shf_v1;
|
||||
wire [7:0] b03_v1;
|
||||
wire [7:0] b10_corr_v1;
|
||||
wire [7:0] b10_redn_v1;
|
||||
reg [7:0] b10_redn_v2_q;
|
||||
wire [7:0] b10_shf_v1;
|
||||
wire [7:0] b10_v1;
|
||||
wire [7:0] b11_corr_v1;
|
||||
wire [7:0] b11_redn_v1;
|
||||
reg [7:0] b11_redn_v2_q;
|
||||
wire [7:0] b11_shf_v1;
|
||||
wire [7:0] b11_v1;
|
||||
wire [7:0] b12_corr_v1;
|
||||
wire [7:0] b12_redn_v1;
|
||||
reg [7:0] b12_redn_v2_q;
|
||||
wire [7:0] b12_shf_v1;
|
||||
wire [7:0] b12_v1;
|
||||
wire [7:0] b13_corr_v1;
|
||||
wire [7:0] b13_redn_v1;
|
||||
reg [7:0] b13_redn_v2_q;
|
||||
wire [7:0] b13_shf_v1;
|
||||
wire [7:0] b13_v1;
|
||||
wire [7:0] b20_corr_v1;
|
||||
wire [7:0] b20_redn_v1;
|
||||
reg [7:0] b20_redn_v2_q;
|
||||
wire [7:0] b20_shf_v1;
|
||||
wire [7:0] b20_v1;
|
||||
wire [7:0] b21_corr_v1;
|
||||
wire [7:0] b21_redn_v1;
|
||||
reg [7:0] b21_redn_v2_q;
|
||||
wire [7:0] b21_shf_v1;
|
||||
wire [7:0] b21_v1;
|
||||
wire [7:0] b22_corr_v1;
|
||||
wire [7:0] b22_redn_v1;
|
||||
reg [7:0] b22_redn_v2_q;
|
||||
wire [7:0] b22_shf_v1;
|
||||
wire [7:0] b22_v1;
|
||||
wire [7:0] b23_corr_v1;
|
||||
wire [7:0] b23_redn_v1;
|
||||
reg [7:0] b23_redn_v2_q;
|
||||
wire [7:0] b23_shf_v1;
|
||||
wire [7:0] b23_v1;
|
||||
wire [7:0] b30_corr_v1;
|
||||
wire [7:0] b30_redn_v1;
|
||||
reg [7:0] b30_redn_v2_q;
|
||||
wire [7:0] b30_shf_v1;
|
||||
wire [7:0] b30_v1;
|
||||
wire [7:0] b31_corr_v1;
|
||||
wire [7:0] b31_redn_v1;
|
||||
reg [7:0] b31_redn_v2_q;
|
||||
wire [7:0] b31_shf_v1;
|
||||
wire [7:0] b31_v1;
|
||||
wire [7:0] b32_corr_v1;
|
||||
wire [7:0] b32_redn_v1;
|
||||
reg [7:0] b32_redn_v2_q;
|
||||
wire [7:0] b32_shf_v1;
|
||||
wire [7:0] b32_v1;
|
||||
wire [7:0] b33_corr_v1;
|
||||
wire [7:0] b33_redn_v1;
|
||||
reg [7:0] b33_redn_v2_q;
|
||||
wire [7:0] b33_shf_v1;
|
||||
wire [7:0] b33_v1;
|
||||
|
||||
|
||||
|
||||
assign b33_v1[7:0] = aes_din_v1[127:120];
|
||||
assign b23_v1[7:0] = aes_din_v1[119:112];
|
||||
assign b13_v1[7:0] = aes_din_v1[111:104];
|
||||
assign b03_v1[7:0] = aes_din_v1[103:96];
|
||||
assign b32_v1[7:0] = aes_din_v1[95:88];
|
||||
assign b22_v1[7:0] = aes_din_v1[87:80];
|
||||
assign b12_v1[7:0] = aes_din_v1[79:72];
|
||||
assign b02_v1[7:0] = aes_din_v1[71:64];
|
||||
assign b31_v1[7:0] = aes_din_v1[63:56];
|
||||
assign b21_v1[7:0] = aes_din_v1[55:48];
|
||||
assign b11_v1[7:0] = aes_din_v1[47:40];
|
||||
assign b01_v1[7:0] = aes_din_v1[39:32];
|
||||
assign b30_v1[7:0] = aes_din_v1[31:24];
|
||||
assign b20_v1[7:0] = aes_din_v1[23:16];
|
||||
assign b10_v1[7:0] = aes_din_v1[15:8];
|
||||
assign b00_v1[7:0] = aes_din_v1[7:0];
|
||||
assign b33_shf_v1[7:0] = {8{ aes_shf_v1[15]}} & {b33_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[15]}} & {b33_v1[7:0]};
|
||||
assign b23_shf_v1[7:0] = {8{ aes_shf_v1[14]}} & {b23_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[14]}} & {b23_v1[7:0]};
|
||||
assign b13_shf_v1[7:0] = {8{ aes_shf_v1[13]}} & {b13_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[13]}} & {b13_v1[7:0]};
|
||||
assign b03_shf_v1[7:0] = {8{ aes_shf_v1[12]}} & {b03_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[12]}} & {b03_v1[7:0]};
|
||||
assign b32_shf_v1[7:0] = {8{ aes_shf_v1[11]}} & {b32_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[11]}} & {b32_v1[7:0]};
|
||||
assign b22_shf_v1[7:0] = {8{ aes_shf_v1[10]}} & {b22_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[10]}} & {b22_v1[7:0]};
|
||||
assign b12_shf_v1[7:0] = {8{ aes_shf_v1[ 9]}} & {b12_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 9]}} & {b12_v1[7:0]};
|
||||
assign b02_shf_v1[7:0] = {8{ aes_shf_v1[ 8]}} & {b02_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 8]}} & {b02_v1[7:0]};
|
||||
assign b31_shf_v1[7:0] = {8{ aes_shf_v1[ 7]}} & {b31_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 7]}} & {b31_v1[7:0]};
|
||||
assign b21_shf_v1[7:0] = {8{ aes_shf_v1[ 6]}} & {b21_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 6]}} & {b21_v1[7:0]};
|
||||
assign b11_shf_v1[7:0] = {8{ aes_shf_v1[ 5]}} & {b11_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 5]}} & {b11_v1[7:0]};
|
||||
assign b01_shf_v1[7:0] = {8{ aes_shf_v1[ 4]}} & {b01_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 4]}} & {b01_v1[7:0]};
|
||||
assign b30_shf_v1[7:0] = {8{ aes_shf_v1[ 3]}} & {b30_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 3]}} & {b30_v1[7:0]};
|
||||
assign b20_shf_v1[7:0] = {8{ aes_shf_v1[ 2]}} & {b20_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 2]}} & {b20_v1[7:0]};
|
||||
assign b10_shf_v1[7:0] = {8{ aes_shf_v1[ 1]}} & {b10_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 1]}} & {b10_v1[7:0]};
|
||||
assign b00_shf_v1[7:0] = {8{ aes_shf_v1[ 0]}} & {b00_v1[6:0], 1'b0} |
|
||||
{8{~aes_shf_v1[ 0]}} & {b00_v1[7:0]};
|
||||
|
||||
|
||||
|
||||
|
||||
assign b33_corr_v1[7:0] = {8{aes_shf_v1[15]}} & {8{b33_v1[7]}} & 8'h1b;
|
||||
assign b23_corr_v1[7:0] = {8{aes_shf_v1[14]}} & {8{b23_v1[7]}} & 8'h1b;
|
||||
assign b13_corr_v1[7:0] = {8{aes_shf_v1[13]}} & {8{b13_v1[7]}} & 8'h1b;
|
||||
assign b03_corr_v1[7:0] = {8{aes_shf_v1[12]}} & {8{b03_v1[7]}} & 8'h1b;
|
||||
assign b32_corr_v1[7:0] = {8{aes_shf_v1[11]}} & {8{b32_v1[7]}} & 8'h1b;
|
||||
assign b22_corr_v1[7:0] = {8{aes_shf_v1[10]}} & {8{b22_v1[7]}} & 8'h1b;
|
||||
assign b12_corr_v1[7:0] = {8{aes_shf_v1[ 9]}} & {8{b12_v1[7]}} & 8'h1b;
|
||||
assign b02_corr_v1[7:0] = {8{aes_shf_v1[ 8]}} & {8{b02_v1[7]}} & 8'h1b;
|
||||
assign b31_corr_v1[7:0] = {8{aes_shf_v1[ 7]}} & {8{b31_v1[7]}} & 8'h1b;
|
||||
assign b21_corr_v1[7:0] = {8{aes_shf_v1[ 6]}} & {8{b21_v1[7]}} & 8'h1b;
|
||||
assign b11_corr_v1[7:0] = {8{aes_shf_v1[ 5]}} & {8{b11_v1[7]}} & 8'h1b;
|
||||
assign b01_corr_v1[7:0] = {8{aes_shf_v1[ 4]}} & {8{b01_v1[7]}} & 8'h1b;
|
||||
assign b30_corr_v1[7:0] = {8{aes_shf_v1[ 3]}} & {8{b30_v1[7]}} & 8'h1b;
|
||||
assign b20_corr_v1[7:0] = {8{aes_shf_v1[ 2]}} & {8{b20_v1[7]}} & 8'h1b;
|
||||
assign b10_corr_v1[7:0] = {8{aes_shf_v1[ 1]}} & {8{b10_v1[7]}} & 8'h1b;
|
||||
assign b00_corr_v1[7:0] = {8{aes_shf_v1[ 0]}} & {8{b00_v1[7]}} & 8'h1b;
|
||||
|
||||
assign b33_redn_v1[7:0] = b33_corr_v1[7:0] ^ b33_shf_v1[7:0];
|
||||
assign b23_redn_v1[7:0] = b23_corr_v1[7:0] ^ b23_shf_v1[7:0];
|
||||
assign b13_redn_v1[7:0] = b13_corr_v1[7:0] ^ b13_shf_v1[7:0];
|
||||
assign b03_redn_v1[7:0] = b03_corr_v1[7:0] ^ b03_shf_v1[7:0];
|
||||
assign b32_redn_v1[7:0] = b32_corr_v1[7:0] ^ b32_shf_v1[7:0];
|
||||
assign b22_redn_v1[7:0] = b22_corr_v1[7:0] ^ b22_shf_v1[7:0];
|
||||
assign b12_redn_v1[7:0] = b12_corr_v1[7:0] ^ b12_shf_v1[7:0];
|
||||
assign b02_redn_v1[7:0] = b02_corr_v1[7:0] ^ b02_shf_v1[7:0];
|
||||
assign b31_redn_v1[7:0] = b31_corr_v1[7:0] ^ b31_shf_v1[7:0];
|
||||
assign b21_redn_v1[7:0] = b21_corr_v1[7:0] ^ b21_shf_v1[7:0];
|
||||
assign b11_redn_v1[7:0] = b11_corr_v1[7:0] ^ b11_shf_v1[7:0];
|
||||
assign b01_redn_v1[7:0] = b01_corr_v1[7:0] ^ b01_shf_v1[7:0];
|
||||
assign b30_redn_v1[7:0] = b30_corr_v1[7:0] ^ b30_shf_v1[7:0];
|
||||
assign b20_redn_v1[7:0] = b20_corr_v1[7:0] ^ b20_shf_v1[7:0];
|
||||
assign b10_redn_v1[7:0] = b10_corr_v1[7:0] ^ b10_shf_v1[7:0];
|
||||
assign b00_redn_v1[7:0] = b00_corr_v1[7:0] ^ b00_shf_v1[7:0];
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_b33_redn_v2_q_7_0_grp
|
||||
if (reset == 1'b1) begin
|
||||
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
|
||||
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
|
||||
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
|
||||
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
|
||||
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
|
||||
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
|
||||
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
|
||||
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
|
||||
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
|
||||
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
|
||||
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
|
||||
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
|
||||
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
|
||||
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
|
||||
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
|
||||
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
|
||||
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1) begin
|
||||
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
|
||||
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
|
||||
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
|
||||
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
|
||||
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
|
||||
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
|
||||
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
|
||||
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
|
||||
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
|
||||
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
|
||||
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
|
||||
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
|
||||
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
|
||||
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
|
||||
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
|
||||
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign aesd_out[127:120] = b33_redn_v2_q[7:0];
|
||||
assign aesd_out[119:112] = b23_redn_v2_q[7:0];
|
||||
assign aesd_out[111:104] = b13_redn_v2_q[7:0];
|
||||
assign aesd_out[103:96] = b03_redn_v2_q[7:0];
|
||||
|
||||
assign aesd_out[95:88] = b32_redn_v2_q[7:0];
|
||||
assign aesd_out[87:80] = b22_redn_v2_q[7:0];
|
||||
assign aesd_out[79:72] = b12_redn_v2_q[7:0];
|
||||
assign aesd_out[71:64] = b02_redn_v2_q[7:0];
|
||||
|
||||
assign aesd_out[63:56] = b31_redn_v2_q[7:0];
|
||||
assign aesd_out[55:48] = b21_redn_v2_q[7:0];
|
||||
assign aesd_out[47:40] = b11_redn_v2_q[7:0];
|
||||
assign aesd_out[39:32] = b01_redn_v2_q[7:0];
|
||||
|
||||
assign aesd_out[31:24] = b30_redn_v2_q[7:0];
|
||||
assign aesd_out[23:16] = b20_redn_v2_q[7:0];
|
||||
assign aesd_out[15:8] = b10_redn_v2_q[7:0];
|
||||
assign aesd_out[7:0] = b00_redn_v2_q[7:0];
|
||||
|
||||
|
||||
assign aesimc_in[127:0] = aesd_out[127:0];
|
||||
|
||||
herculesae_vx_aesimc u_aesimc(
|
||||
.d_in (aesimc_in[127:0]),
|
||||
.imc (aesdimc_out[127:0])
|
||||
);
|
||||
|
||||
assign aese_out[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aese_out[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aese_out[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aese_out[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
|
||||
assign aese_out[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
assign aese_out[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
|
||||
assign aese_out[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
|
||||
assign aese_out[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
|
||||
assign aese_out[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
|
||||
|
||||
assign aesmc_in[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aesmc_in[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aesmc_in[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
assign aesmc_in[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
|
||||
assign aesmc_in[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
assign aesmc_in[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
|
||||
assign aesmc_in[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
|
||||
assign aesmc_in[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
|
||||
assign aesmc_in[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
|
||||
|
||||
herculesae_vx_aesmc u_aesmc(
|
||||
.d_in (aesmc_in[127:0]),
|
||||
.mc (aesemc_out[127:0])
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,93 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesed2_lut
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] lut_in,
|
||||
|
||||
|
||||
output wire [127:0] lut_out
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [7:0] b00;
|
||||
wire [7:0] b01;
|
||||
wire [7:0] b02;
|
||||
wire [7:0] b03;
|
||||
wire [7:0] b10;
|
||||
wire [7:0] b11;
|
||||
wire [7:0] b12;
|
||||
wire [7:0] b13;
|
||||
wire [7:0] b20;
|
||||
wire [7:0] b21;
|
||||
wire [7:0] b22;
|
||||
wire [7:0] b23;
|
||||
wire [7:0] b30;
|
||||
wire [7:0] b31;
|
||||
wire [7:0] b32;
|
||||
wire [7:0] b33;
|
||||
|
||||
herculesae_vx_aesinv u_inv_lut0(.lut_in(lut_in[127:120]), .lut_out(b33[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut1(.lut_in(lut_in[119:112]), .lut_out(b23[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut2(.lut_in(lut_in[111:104]), .lut_out(b13[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut3(.lut_in(lut_in[103:96]), .lut_out(b03[7:0]));
|
||||
|
||||
herculesae_vx_aesinv u_inv_lut4(.lut_in(lut_in[95:88]), .lut_out(b32[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut5(.lut_in(lut_in[87:80]), .lut_out(b22[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut6(.lut_in(lut_in[79:72]), .lut_out(b12[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut7(.lut_in(lut_in[71:64]), .lut_out(b02[7:0]));
|
||||
|
||||
herculesae_vx_aesinv u_inv_lut8 (.lut_in(lut_in[63:56]), .lut_out(b31[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut9 (.lut_in(lut_in[55:48]), .lut_out(b21[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut10(.lut_in(lut_in[47:40]), .lut_out(b11[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut11(.lut_in(lut_in[39:32]), .lut_out(b01[7:0]));
|
||||
|
||||
herculesae_vx_aesinv u_inv_lut12(.lut_in(lut_in[31:24]), .lut_out(b30[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut13(.lut_in(lut_in[23:16]), .lut_out(b20[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut14(.lut_in(lut_in[15:8]), .lut_out(b10[7:0]));
|
||||
herculesae_vx_aesinv u_inv_lut15(.lut_in(lut_in[7:0]), .lut_out(b00[7:0]));
|
||||
|
||||
assign lut_out[127:0] = {b33[7:0],b23[7:0],b13[7:0],b03[7:0],
|
||||
b32[7:0],b22[7:0],b12[7:0],b02[7:0],
|
||||
b31[7:0],b21[7:0],b11[7:0],b01[7:0],
|
||||
b30[7:0],b20[7:0],b10[7:0],b00[7:0]
|
||||
};
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,234 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesimc
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] d_in,
|
||||
|
||||
output wire [127:0] imc
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [7:0] i00;
|
||||
wire [7:0] i01;
|
||||
wire [7:0] i02;
|
||||
wire [7:0] i03;
|
||||
wire [7:0] i10;
|
||||
wire [7:0] i11;
|
||||
wire [7:0] i12;
|
||||
wire [7:0] i13;
|
||||
wire [7:0] i20;
|
||||
wire [7:0] i21;
|
||||
wire [7:0] i22;
|
||||
wire [7:0] i23;
|
||||
wire [7:0] i30;
|
||||
wire [7:0] i31;
|
||||
wire [7:0] i32;
|
||||
wire [7:0] i33;
|
||||
wire [7:0] s00;
|
||||
wire [10:0] s00_nr;
|
||||
wire [7:0] s01;
|
||||
wire [10:0] s01_nr;
|
||||
wire [7:0] s02;
|
||||
wire [10:0] s02_nr;
|
||||
wire [7:0] s03;
|
||||
wire [10:0] s03_nr;
|
||||
wire [7:0] s10;
|
||||
wire [10:0] s10_nr;
|
||||
wire [7:0] s11;
|
||||
wire [10:0] s11_nr;
|
||||
wire [7:0] s12;
|
||||
wire [10:0] s12_nr;
|
||||
wire [7:0] s13;
|
||||
wire [10:0] s13_nr;
|
||||
wire [7:0] s20;
|
||||
wire [10:0] s20_nr;
|
||||
wire [7:0] s21;
|
||||
wire [10:0] s21_nr;
|
||||
wire [7:0] s22;
|
||||
wire [10:0] s22_nr;
|
||||
wire [7:0] s23;
|
||||
wire [10:0] s23_nr;
|
||||
wire [7:0] s30;
|
||||
wire [10:0] s30_nr;
|
||||
wire [7:0] s31;
|
||||
wire [10:0] s31_nr;
|
||||
wire [7:0] s32;
|
||||
wire [10:0] s32_nr;
|
||||
wire [7:0] s33;
|
||||
wire [10:0] s33_nr;
|
||||
|
||||
|
||||
assign i33[7:0] = d_in[127:120];
|
||||
assign i23[7:0] = d_in[119:112];
|
||||
assign i13[7:0] = d_in[111:104];
|
||||
assign i03[7:0] = d_in[103:96];
|
||||
|
||||
assign i32[7:0] = d_in[95:88];
|
||||
assign i22[7:0] = d_in[87:80];
|
||||
assign i12[7:0] = d_in[79:72];
|
||||
assign i02[7:0] = d_in[71:64];
|
||||
|
||||
assign i31[7:0] = d_in[63:56];
|
||||
assign i21[7:0] = d_in[55:48];
|
||||
assign i11[7:0] = d_in[47:40];
|
||||
assign i01[7:0] = d_in[39:32];
|
||||
|
||||
assign i30[7:0] = d_in[31:24];
|
||||
assign i20[7:0] = d_in[23:16];
|
||||
assign i10[7:0] = d_in[15:8];
|
||||
assign i00[7:0] = d_in[7:0];
|
||||
|
||||
|
||||
|
||||
assign s00_nr[10:0] = {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {2'b00,i00[7:0],1'b0}
|
||||
^ {i10[7:0],3'b000} ^ {2'b00,i10[7:0],1'b0} ^ {3'b000,i10[7:0]}
|
||||
^ {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {3'b000,i20[7:0]}
|
||||
^ {i30[7:0],3'b000} ^ {3'b000,i30[7:0]};
|
||||
assign s00[7:0] = s00_nr[7:0] ^ ({8{s00_nr[8]}} & 8'h1b) ^ ({8{s00_nr[9]}} & 8'h36) ^ ({8{s00_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s01_nr[10:0] = {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {2'b00,i01[7:0],1'b0}
|
||||
^ {i11[7:0],3'b000} ^ {2'b00,i11[7:0],1'b0} ^ {3'b000,i11[7:0]}
|
||||
^ {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {3'b000,i21[7:0]}
|
||||
^ {i31[7:0],3'b000} ^ {3'b000,i31[7:0]};
|
||||
assign s01[7:0] = s01_nr[7:0] ^ ({8{s01_nr[8]}} & 8'h1b) ^ ({8{s01_nr[9]}} & 8'h36) ^ ({8{s01_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s02_nr[10:0] = {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {2'b00,i02[7:0],1'b0}
|
||||
^ {i12[7:0],3'b000} ^ {2'b00,i12[7:0],1'b0} ^ {3'b000,i12[7:0]}
|
||||
^ {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {3'b000,i22[7:0]}
|
||||
^ {i32[7:0],3'b000} ^ {3'b000,i32[7:0]};
|
||||
assign s02[7:0] = s02_nr[7:0] ^ ({8{s02_nr[8]}} & 8'h1b) ^ ({8{s02_nr[9]}} & 8'h36) ^ ({8{s02_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s03_nr[10:0] = {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {2'b00,i03[7:0],1'b0}
|
||||
^ {i13[7:0],3'b000} ^ {2'b00,i13[7:0],1'b0} ^ {3'b000,i13[7:0]}
|
||||
^ {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {3'b000,i23[7:0]}
|
||||
^ {i33[7:0],3'b000} ^ {3'b000,i33[7:0]};
|
||||
assign s03[7:0] = s03_nr[7:0] ^ ({8{s03_nr[8]}} & 8'h1b) ^ ({8{s03_nr[9]}} & 8'h36) ^ ({8{s03_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s10_nr[10:0] = {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {2'b00,i10[7:0],1'b0}
|
||||
^ {i20[7:0],3'b000} ^ {2'b00,i20[7:0],1'b0} ^ {3'b000,i20[7:0]}
|
||||
^ {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {3'b000,i30[7:0]}
|
||||
^ {i00[7:0],3'b000} ^ {3'b000,i00[7:0]};
|
||||
assign s10[7:0] = s10_nr[7:0] ^ ({8{s10_nr[8]}} & 8'h1b) ^ ({8{s10_nr[9]}} & 8'h36) ^ ({8{s10_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s11_nr[10:0] = {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {2'b00,i11[7:0],1'b0}
|
||||
^ {i21[7:0],3'b000} ^ {2'b00,i21[7:0],1'b0} ^ {3'b000,i21[7:0]}
|
||||
^ {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {3'b000,i31[7:0]}
|
||||
^ {i01[7:0],3'b000} ^ {3'b000,i01[7:0]};
|
||||
assign s11[7:0] = s11_nr[7:0] ^ ({8{s11_nr[8]}} & 8'h1b) ^ ({8{s11_nr[9]}} & 8'h36) ^ ({8{s11_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s12_nr[10:0] = {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {2'b00,i12[7:0],1'b0}
|
||||
^ {i22[7:0],3'b000} ^ {2'b00,i22[7:0],1'b0} ^ {3'b000,i22[7:0]}
|
||||
^ {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {3'b000,i32[7:0]}
|
||||
^ {i02[7:0],3'b000} ^ {3'b000,i02[7:0]};
|
||||
assign s12[7:0] = s12_nr[7:0] ^ ({8{s12_nr[8]}} & 8'h1b) ^ ({8{s12_nr[9]}} & 8'h36) ^ ({8{s12_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s13_nr[10:0] = {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {2'b00,i13[7:0],1'b0}
|
||||
^ {i23[7:0],3'b000} ^ {2'b00,i23[7:0],1'b0} ^ {3'b000,i23[7:0]}
|
||||
^ {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {3'b000,i33[7:0]}
|
||||
^ {i03[7:0],3'b000} ^ {3'b000,i03[7:0]};
|
||||
assign s13[7:0] = s13_nr[7:0] ^ ({8{s13_nr[8]}} & 8'h1b) ^ ({8{s13_nr[9]}} & 8'h36) ^ ({8{s13_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s20_nr[10:0] = {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {2'b00,i20[7:0],1'b0}
|
||||
^ {i30[7:0],3'b000} ^ {2'b00,i30[7:0],1'b0} ^ {3'b000,i30[7:0]}
|
||||
^ {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {3'b000,i00[7:0]}
|
||||
^ {i10[7:0],3'b000} ^ {3'b000,i10[7:0]};
|
||||
assign s20[7:0] = s20_nr[7:0] ^ ({8{s20_nr[8]}} & 8'h1b) ^ ({8{s20_nr[9]}} & 8'h36) ^ ({8{s20_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s21_nr[10:0] = {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {2'b00,i21[7:0],1'b0}
|
||||
^ {i31[7:0],3'b000} ^ {2'b00,i31[7:0],1'b0} ^ {3'b000,i31[7:0]}
|
||||
^ {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {3'b000,i01[7:0]}
|
||||
^ {i11[7:0],3'b000} ^ {3'b000,i11[7:0]};
|
||||
assign s21[7:0] = s21_nr[7:0] ^ ({8{s21_nr[8]}} & 8'h1b) ^ ({8{s21_nr[9]}} & 8'h36) ^ ({8{s21_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s22_nr[10:0] = {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {2'b00,i22[7:0],1'b0}
|
||||
^ {i32[7:0],3'b000} ^ {2'b00,i32[7:0],1'b0} ^ {3'b000,i32[7:0]}
|
||||
^ {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {3'b000,i02[7:0]}
|
||||
^ {i12[7:0],3'b000} ^ {3'b000,i12[7:0]};
|
||||
assign s22[7:0] = s22_nr[7:0] ^ ({8{s22_nr[8]}} & 8'h1b) ^ ({8{s22_nr[9]}} & 8'h36) ^ ({8{s22_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s23_nr[10:0] = {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {2'b00,i23[7:0],1'b0}
|
||||
^ {i33[7:0],3'b000} ^ {2'b00,i33[7:0],1'b0} ^ {3'b000,i33[7:0]}
|
||||
^ {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {3'b000,i03[7:0]}
|
||||
^ {i13[7:0],3'b000} ^ {3'b000,i13[7:0]};
|
||||
assign s23[7:0] = s23_nr[7:0] ^ ({8{s23_nr[8]}} & 8'h1b) ^ ({8{s23_nr[9]}} & 8'h36) ^ ({8{s23_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s30_nr[10:0] = {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {2'b00,i30[7:0],1'b0}
|
||||
^ {i00[7:0],3'b000} ^ {2'b00,i00[7:0],1'b0} ^ {3'b000,i00[7:0]}
|
||||
^ {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {3'b000,i10[7:0]}
|
||||
^ {i20[7:0],3'b000} ^ {3'b000,i20[7:0]};
|
||||
assign s30[7:0] = s30_nr[7:0] ^ ({8{s30_nr[8]}} & 8'h1b) ^ ({8{s30_nr[9]}} & 8'h36) ^ ({8{s30_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s31_nr[10:0] = {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {2'b00,i31[7:0],1'b0}
|
||||
^ {i01[7:0],3'b000} ^ {2'b00,i01[7:0],1'b0} ^ {3'b000,i01[7:0]}
|
||||
^ {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {3'b000,i11[7:0]}
|
||||
^ {i21[7:0],3'b000} ^ {3'b000,i21[7:0]};
|
||||
assign s31[7:0] = s31_nr[7:0] ^ ({8{s31_nr[8]}} & 8'h1b) ^ ({8{s31_nr[9]}} & 8'h36) ^ ({8{s31_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s32_nr[10:0] = {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {2'b00,i32[7:0],1'b0}
|
||||
^ {i02[7:0],3'b000} ^ {2'b00,i02[7:0],1'b0} ^ {3'b000,i02[7:0]}
|
||||
^ {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {3'b000,i12[7:0]}
|
||||
^ {i22[7:0],3'b000} ^ {3'b000,i22[7:0]};
|
||||
assign s32[7:0] = s32_nr[7:0] ^ ({8{s32_nr[8]}} & 8'h1b) ^ ({8{s32_nr[9]}} & 8'h36) ^ ({8{s32_nr[10]}} & 8'h6c);
|
||||
|
||||
assign s33_nr[10:0] = {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {2'b00,i33[7:0],1'b0}
|
||||
^ {i03[7:0],3'b000} ^ {2'b00,i03[7:0],1'b0} ^ {3'b000,i03[7:0]}
|
||||
^ {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {3'b000,i13[7:0]}
|
||||
^ {i23[7:0],3'b000} ^ {3'b000,i23[7:0]};
|
||||
assign s33[7:0] = s33_nr[7:0] ^ ({8{s33_nr[8]}} & 8'h1b) ^ ({8{s33_nr[9]}} & 8'h36) ^ ({8{s33_nr[10]}} & 8'h6c);
|
||||
|
||||
assign imc[127:120] = s33[7:0];
|
||||
assign imc[119:112] = s23[7:0];
|
||||
assign imc[111:104] = s13[7:0];
|
||||
assign imc[103:96] = s03[7:0];
|
||||
|
||||
assign imc[95:88] = s32[7:0];
|
||||
assign imc[87:80] = s22[7:0];
|
||||
assign imc[79:72] = s12[7:0];
|
||||
assign imc[71:64] = s02[7:0];
|
||||
|
||||
assign imc[63:56] = s31[7:0];
|
||||
assign imc[55:48] = s21[7:0];
|
||||
assign imc[47:40] = s11[7:0];
|
||||
assign imc[39:32] = s01[7:0];
|
||||
|
||||
assign imc[31:24] = s30[7:0];
|
||||
assign imc[23:16] = s20[7:0];
|
||||
assign imc[15:8] = s10[7:0];
|
||||
assign imc[7:0] = s00[7:0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,517 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesinv
|
||||
(
|
||||
|
||||
|
||||
input wire [7:0] lut_in,
|
||||
output wire [7:0] lut_out
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign lut_out[7] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[0]) | (
|
||||
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[1]
|
||||
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
|
||||
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
|
||||
&lut_in[5]&lut_in[3]&!lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]&lut_in[0]);
|
||||
|
||||
assign lut_out[6] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (
|
||||
!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[6]&lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&lut_in[0]) | (
|
||||
lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[5]
|
||||
&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[4]
|
||||
&lut_in[3]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]);
|
||||
|
||||
assign lut_out[5] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]) | (
|
||||
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]
|
||||
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
|
||||
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
|
||||
&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (!lut_in[7]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[5]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]
|
||||
&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (
|
||||
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[1]&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[4]&lut_in[2]&lut_in[1]);
|
||||
|
||||
assign lut_out[4] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
|
||||
&lut_in[3]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]) | (!lut_in[7]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[1]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]) | (!lut_in[7]&!lut_in[6]
|
||||
&lut_in[4]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]);
|
||||
|
||||
assign lut_out[3] = (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[2]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[5]
|
||||
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]
|
||||
&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&lut_in[4]
|
||||
&lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[0]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[1]) | (
|
||||
!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]);
|
||||
|
||||
assign lut_out[2] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]
|
||||
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
|
||||
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
|
||||
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[2]&lut_in[1]&lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]
|
||||
&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&!lut_in[3]&!lut_in[1]);
|
||||
|
||||
assign lut_out[1] = (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
|
||||
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
|
||||
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
|
||||
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (
|
||||
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (lut_in[7]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]
|
||||
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
|
||||
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[4]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
|
||||
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]
|
||||
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]
|
||||
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]) | (lut_in[7]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
|
||||
!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]);
|
||||
|
||||
assign lut_out[0] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
|
||||
&!lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
|
||||
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
|
||||
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
|
||||
&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
|
||||
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
|
||||
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
|
||||
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
|
||||
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
|
||||
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
|
||||
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
|
||||
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
|
||||
lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
|
||||
&lut_in[2]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
|
||||
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[4]&!lut_in[3]&lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
|
||||
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
|
||||
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]
|
||||
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[2]
|
||||
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
|
||||
&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]
|
||||
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
|
||||
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
|
||||
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (!lut_in[7]
|
||||
&!lut_in[6]&lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]
|
||||
&!lut_in[4]&lut_in[1]&lut_in[0]);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,186 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_aesmc
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] d_in,
|
||||
|
||||
output wire [127:0] mc
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [7:0] i00;
|
||||
wire [7:0] i01;
|
||||
wire [7:0] i02;
|
||||
wire [7:0] i03;
|
||||
wire [7:0] i10;
|
||||
wire [7:0] i11;
|
||||
wire [7:0] i12;
|
||||
wire [7:0] i13;
|
||||
wire [7:0] i20;
|
||||
wire [7:0] i21;
|
||||
wire [7:0] i22;
|
||||
wire [7:0] i23;
|
||||
wire [7:0] i30;
|
||||
wire [7:0] i31;
|
||||
wire [7:0] i32;
|
||||
wire [7:0] i33;
|
||||
wire [7:0] s00;
|
||||
wire [7:0] s01;
|
||||
wire [7:0] s02;
|
||||
wire [7:0] s03;
|
||||
wire [7:0] s10;
|
||||
wire [7:0] s11;
|
||||
wire [7:0] s12;
|
||||
wire [7:0] s13;
|
||||
wire [7:0] s20;
|
||||
wire [7:0] s21;
|
||||
wire [7:0] s22;
|
||||
wire [7:0] s23;
|
||||
wire [7:0] s30;
|
||||
wire [7:0] s31;
|
||||
wire [7:0] s32;
|
||||
wire [7:0] s33;
|
||||
|
||||
|
||||
assign i33[7:0] = d_in[127:120];
|
||||
assign i23[7:0] = d_in[119:112];
|
||||
assign i13[7:0] = d_in[111:104];
|
||||
assign i03[7:0] = d_in[103:96];
|
||||
|
||||
assign i32[7:0] = d_in[95:88];
|
||||
assign i22[7:0] = d_in[87:80];
|
||||
assign i12[7:0] = d_in[79:72];
|
||||
assign i02[7:0] = d_in[71:64];
|
||||
|
||||
assign i31[7:0] = d_in[63:56];
|
||||
assign i21[7:0] = d_in[55:48];
|
||||
assign i11[7:0] = d_in[47:40];
|
||||
assign i01[7:0] = d_in[39:32];
|
||||
|
||||
assign i30[7:0] = d_in[31:24];
|
||||
assign i20[7:0] = d_in[23:16];
|
||||
assign i10[7:0] = d_in[15:8];
|
||||
assign i00[7:0] = d_in[7:0];
|
||||
|
||||
|
||||
assign s00[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b)
|
||||
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) ^ i10[7:0]
|
||||
^ i20[7:0]
|
||||
^ i30[7:0];
|
||||
assign s01[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b)
|
||||
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) ^ i11[7:0]
|
||||
^ i21[7:0]
|
||||
^ i31[7:0];
|
||||
assign s02[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b)
|
||||
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) ^ i12[7:0]
|
||||
^ i22[7:0]
|
||||
^ i32[7:0];
|
||||
assign s03[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b)
|
||||
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) ^ i13[7:0]
|
||||
^ i23[7:0]
|
||||
^ i33[7:0];
|
||||
assign s10[7:0] = i00[7:0]
|
||||
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b)
|
||||
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) ^ i20[7:0]
|
||||
^ i30[7:0];
|
||||
assign s11[7:0] = i01[7:0]
|
||||
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b)
|
||||
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) ^ i21[7:0]
|
||||
^ i31[7:0];
|
||||
assign s12[7:0] = i02[7:0]
|
||||
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b)
|
||||
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) ^ i22[7:0]
|
||||
^ i32[7:0];
|
||||
assign s13[7:0] = i03[7:0]
|
||||
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b)
|
||||
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) ^ i23[7:0]
|
||||
^ i33[7:0];
|
||||
assign s20[7:0] = i00[7:0]
|
||||
^ i10[7:0]
|
||||
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b)
|
||||
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b) ^ i30[7:0];
|
||||
assign s21[7:0] = i01[7:0]
|
||||
^ i11[7:0]
|
||||
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b)
|
||||
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b) ^ i31[7:0];
|
||||
assign s22[7:0] = i02[7:0]
|
||||
^ i12[7:0]
|
||||
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b)
|
||||
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b) ^ i32[7:0];
|
||||
assign s23[7:0] = i03[7:0]
|
||||
^ i13[7:0]
|
||||
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b)
|
||||
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b) ^ i33[7:0];
|
||||
assign s30[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) ^ i00[7:0]
|
||||
^ i10[7:0]
|
||||
^ i20[7:0]
|
||||
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b);
|
||||
assign s31[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) ^ i01[7:0]
|
||||
^ i11[7:0]
|
||||
^ i21[7:0]
|
||||
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b);
|
||||
assign s32[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) ^ i02[7:0]
|
||||
^ i12[7:0]
|
||||
^ i22[7:0]
|
||||
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b);
|
||||
assign s33[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) ^ i03[7:0]
|
||||
^ i13[7:0]
|
||||
^ i23[7:0]
|
||||
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b);
|
||||
|
||||
assign mc[127:120] = s33[7:0];
|
||||
assign mc[119:112] = s23[7:0];
|
||||
assign mc[111:104] = s13[7:0];
|
||||
assign mc[103:96] = s03[7:0];
|
||||
|
||||
assign mc[95:88] = s32[7:0];
|
||||
assign mc[87:80] = s22[7:0];
|
||||
assign mc[79:72] = s12[7:0];
|
||||
assign mc[71:64] = s02[7:0];
|
||||
|
||||
assign mc[63:56] = s31[7:0];
|
||||
assign mc[55:48] = s21[7:0];
|
||||
assign mc[47:40] = s11[7:0];
|
||||
assign mc[39:32] = s01[7:0];
|
||||
|
||||
assign mc[31:24] = s30[7:0];
|
||||
assign mc[23:16] = s20[7:0];
|
||||
assign mc[15:8] = s10[7:0];
|
||||
assign mc[7:0] = s00[7:0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,966 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_crypt
|
||||
(
|
||||
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire ival_v1_q,
|
||||
input wire sha1c_v1_q,
|
||||
input wire sha1p_v1_q,
|
||||
input wire sha1m_v1_q,
|
||||
input wire sha1cpm_v1_q,
|
||||
input wire sha256h_v1_q,
|
||||
input wire sha256h2_v1_q,
|
||||
input wire sha256hh2_v1_q,
|
||||
input wire sha1h_v1_q,
|
||||
input wire sha1su0_v1_q,
|
||||
input wire sha1su1_v1_q,
|
||||
input wire sha256su0_v1_q,
|
||||
input wire sha256su1_v1_q,
|
||||
input wire sha256su1_dup_x_v1_q,
|
||||
input wire sha256su1_dup_y_v1_q,
|
||||
input wire sha256su1_dup_z_v1_q,
|
||||
|
||||
input wire [127:0] opa_v1,
|
||||
input wire [127:0] opb_v1,
|
||||
input wire [127:0] opc_v1,
|
||||
|
||||
output wire [127:0] cryptout_v2,
|
||||
output wire [127:0] cryptout_v4,
|
||||
output wire crypt_active
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire block_opa_passthrough;
|
||||
wire [63:0] carry1c_v1;
|
||||
wire [63:0] carry4c_v3;
|
||||
wire [31:0] carry4c_v4;
|
||||
wire [63:0] carry_2c4c_v2;
|
||||
wire [31:0] carry_sha1cpm_v1;
|
||||
wire [31:0] carry_sha1cpm_v2;
|
||||
wire [31:0] carry_sha1cpm_v3;
|
||||
wire [31:0] carry_sha1cpm_v4;
|
||||
wire [63:0] carry_sha256h32_v1;
|
||||
wire [63:0] carry_sha256h32_v2;
|
||||
wire [63:0] carry_sha256h32_v3;
|
||||
wire [31:0] carry_sha256h32_v4;
|
||||
wire [31:0] carry_sha256su0_v1;
|
||||
wire [63:0] carry_sha256su1_v1;
|
||||
wire [63:0] carry_sha256su1_v2;
|
||||
wire ival_en;
|
||||
wire ival_v1_or_v2;
|
||||
wire ival_v2_4latency;
|
||||
reg ival_v2_q;
|
||||
reg ival_v3_q;
|
||||
wire [127:0] newa_v1;
|
||||
wire [127:0] newa_v2;
|
||||
wire [127:0] newa_v3;
|
||||
wire [127:0] newb_v1;
|
||||
wire [127:0] newb_v2;
|
||||
wire [127:0] newb_v3;
|
||||
wire [95:0] newc_v1;
|
||||
wire [127:0] newx_v4;
|
||||
wire [127:0] newy_v4;
|
||||
reg [127:0] opa_v2_q;
|
||||
reg [127:0] opa_v3_q;
|
||||
reg [127:0] opa_v4_q;
|
||||
reg [127:0] opb_v2_q;
|
||||
reg [127:0] opb_v3_q;
|
||||
reg [127:0] opb_v4_q;
|
||||
reg [95:0] opc_v2_q;
|
||||
reg [63:0] opc_v3_q;
|
||||
reg [31:0] opc_v4_q;
|
||||
wire [127:0] sha1_out_v1;
|
||||
wire sha1_v1;
|
||||
wire [127:0] sha1_xin_v1;
|
||||
wire [31:0] sha1_yin_v1;
|
||||
wire [31:0] sha1_zin_v1;
|
||||
reg sha1c_v2_q;
|
||||
reg sha1c_v3_q;
|
||||
reg sha1c_v4_q;
|
||||
reg sha1cpm_h_v4_q;
|
||||
reg sha1cpm_l_v4_q;
|
||||
reg sha1cpm_v2_q;
|
||||
reg sha1cpm_v3_q;
|
||||
reg sha1cpm_v4_q;
|
||||
wire [127:0] sha1cpm_x_v1;
|
||||
wire [127:0] sha1cpm_x_v2;
|
||||
wire [127:0] sha1cpm_x_v3;
|
||||
wire [127:0] sha1cpm_x_v4;
|
||||
wire [127:0] sha1cpm_y_v1;
|
||||
wire [127:0] sha1cpm_y_v2;
|
||||
wire [127:0] sha1cpm_y_v3;
|
||||
wire [31:0] sha1cpm_y_v4;
|
||||
wire [31:0] sha1h_qnin_v1;
|
||||
reg sha1m_v2_q;
|
||||
reg sha1m_v3_q;
|
||||
reg sha1m_v4_q;
|
||||
reg sha1p_v2_q;
|
||||
reg sha1p_v3_q;
|
||||
reg sha1p_v4_q;
|
||||
wire [127:0] sha1su0_q_v1;
|
||||
reg sha1su0_v2_q;
|
||||
wire [127:0] sha1su1_qdin_v1;
|
||||
wire [127:0] sha1su1_qnin_v1;
|
||||
wire [127:0] sha256_xin_v1;
|
||||
wire [127:0] sha256_yin_v1;
|
||||
wire [31:0] sha256_zin_v1;
|
||||
reg sha256h2_h_v4_q;
|
||||
reg sha256h2_l_v4_q;
|
||||
reg sha256h2_v2_q;
|
||||
reg sha256h2_v3_q;
|
||||
reg sha256h2_v4_q;
|
||||
reg sha256h_h_v4_q;
|
||||
reg sha256h_l_v4_q;
|
||||
reg sha256h_v2_q;
|
||||
reg sha256h_v3_q;
|
||||
reg sha256h_v4_q;
|
||||
wire [127:0] sha256h_x_v1;
|
||||
wire [127:0] sha256h_x_v2;
|
||||
wire [127:0] sha256h_x_v3;
|
||||
wire [127:0] sha256h_x_v4;
|
||||
wire [127:0] sha256h_y_v1;
|
||||
wire [127:0] sha256h_y_v2;
|
||||
wire [127:0] sha256h_y_v3;
|
||||
wire [127:0] sha256h_y_v4;
|
||||
wire sha256hh2_v2;
|
||||
wire sha256hh2_v3;
|
||||
wire sha256hh2_v4;
|
||||
wire [127:0] sha256su0_out_v1;
|
||||
wire [127:0] sha256su0_qdin_v1;
|
||||
wire [127:0] sha256su0_qnin_v1;
|
||||
reg sha256su1_dup_x_v2_q;
|
||||
reg sha256su1_dup_y_v2_q;
|
||||
reg sha256su1_dup_z_v2_q;
|
||||
reg sha256su1_h_v2_q;
|
||||
reg sha256su1_l_v2_q;
|
||||
reg sha256su1_v2_q;
|
||||
wire [63:0] sha256su1_x_v1;
|
||||
wire [63:0] sha256su1_x_v2;
|
||||
reg sha_inst_h_v2_q;
|
||||
reg sha_inst_l_v2_q;
|
||||
wire sha_inst_v1;
|
||||
reg sha_inst_v2_q;
|
||||
wire short_pipe_out_v3_en;
|
||||
wire [31:0] sigma0_v3;
|
||||
wire [31:0] sigma0_v4;
|
||||
wire [31:0] sigma1_v3;
|
||||
wire [63:0] sum1c_v1;
|
||||
wire [63:0] sum4c_v3;
|
||||
wire [31:0] sum4c_v4;
|
||||
wire [63:0] sum_2c4c_v2;
|
||||
wire [31:0] sum_sha1cpm_v1;
|
||||
wire [31:0] sum_sha1cpm_v2;
|
||||
wire [31:0] sum_sha1cpm_v3;
|
||||
wire [31:0] sum_sha1cpm_v4;
|
||||
wire [63:0] sum_sha256h32_v1;
|
||||
wire [63:0] sum_sha256h32_v2;
|
||||
wire [63:0] sum_sha256h32_v3;
|
||||
wire [31:0] sum_sha256h32_v4;
|
||||
wire [31:0] sum_sha256su0_v1;
|
||||
wire [63:0] sum_sha256su1_v1;
|
||||
wire [63:0] sum_sha256su1_v2;
|
||||
wire [63:0] sumnr1c_v1;
|
||||
wire [63:0] sumnr4c_v3;
|
||||
wire [31:0] sumnr4c_v4;
|
||||
wire [63:0] sumnr_2c4c_v2;
|
||||
wire [63:0] sumres_sha256su1_v2;
|
||||
wire [31:0] tchoose_v3;
|
||||
wire [31:0] tmajority_v3;
|
||||
wire [31:0] tmajority_v4;
|
||||
wire unused_cout1c2_v1;
|
||||
wire unused_cout1c_v1;
|
||||
wire unused_cout2_2c4c_v2;
|
||||
wire unused_cout2_4c_v3;
|
||||
wire unused_cout4c_v3;
|
||||
wire unused_cout4c_v4;
|
||||
wire unused_cout_2c4c_v2;
|
||||
wire unused_cout_sha256su1h_v2;
|
||||
wire unused_cout_sha256su1l_v2;
|
||||
wire [32:0] x_fa2_c_v4;
|
||||
wire [31:0] x_fa2_s_v4;
|
||||
wire [127:0] x_v1;
|
||||
wire [127:0] x_v2;
|
||||
wire [127:0] x_v3;
|
||||
wire [127:0] x_v4;
|
||||
wire xprime_carry;
|
||||
wire [127:96] xprime_v4;
|
||||
wire [32:0] xy_fa0_c_v3;
|
||||
wire [31:0] xy_fa0_s_v3;
|
||||
wire [32:0] xy_fa1_c_v3;
|
||||
wire [31:0] xy_fa1_c_v4;
|
||||
wire [31:0] xy_fa1_s_v3;
|
||||
wire [31:0] xy_fa1_s_v4;
|
||||
wire [32:0] y_fa2_c_v4;
|
||||
wire [31:0] y_fa2_s_v4;
|
||||
wire [32:0] y_fa3_c_v4;
|
||||
wire [31:0] y_fa3_s_v4;
|
||||
wire [127:0] y_v1;
|
||||
wire [127:0] y_v2;
|
||||
wire [127:0] y_v3;
|
||||
wire [127:0] y_v4;
|
||||
wire [127:96] yprime_v4;
|
||||
wire [127:0] z_v1;
|
||||
wire [95:0] z_v2;
|
||||
wire [63:0] z_v3;
|
||||
wire [31:0] z_v4;
|
||||
|
||||
|
||||
|
||||
assign ival_en = ival_v1_q | ival_v2_q | ival_v3_q;
|
||||
|
||||
assign short_pipe_out_v3_en = sha_inst_v2_q | sha1su0_v2_q | sha256su1_v2_q;
|
||||
|
||||
assign ival_v2_4latency = ~short_pipe_out_v3_en & ival_v2_q;
|
||||
|
||||
assign ival_v1_or_v2 = ival_v1_q | ival_v2_q;
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_ival_v2_q
|
||||
if (reset == 1'b1)
|
||||
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_en == 1'b1)
|
||||
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
|
||||
else if (reset == 1'b0 && ival_en == 1'b0)
|
||||
begin
|
||||
end
|
||||
else
|
||||
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else if (ival_en == 1'b1)
|
||||
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_ival_v3_q
|
||||
if (reset == 1'b1)
|
||||
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_en == 1'b1)
|
||||
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
|
||||
else if (reset == 1'b0 && ival_en == 1'b0)
|
||||
begin
|
||||
end
|
||||
else
|
||||
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else if (ival_en == 1'b1)
|
||||
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_sha1c_v2_q_grp
|
||||
if (reset == 1'b1) begin
|
||||
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
|
||||
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
|
||||
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
|
||||
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
|
||||
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
|
||||
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
|
||||
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
|
||||
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
|
||||
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1) begin
|
||||
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
|
||||
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
|
||||
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
|
||||
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
|
||||
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
|
||||
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
|
||||
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
|
||||
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
|
||||
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_sha1c_v3_q_grp
|
||||
if (reset == 1'b1) begin
|
||||
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
|
||||
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
|
||||
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
|
||||
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
|
||||
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
|
||||
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
|
||||
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v2_4latency == 1'b1) begin
|
||||
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
|
||||
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
|
||||
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
|
||||
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
|
||||
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
|
||||
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_sha1c_v4_q_grp
|
||||
if (reset == 1'b1) begin
|
||||
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
|
||||
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
|
||||
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
|
||||
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
|
||||
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
|
||||
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v3_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v3_q == 1'b1) begin
|
||||
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
|
||||
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
|
||||
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
|
||||
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
|
||||
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
|
||||
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
|
||||
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign sha1_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q;
|
||||
|
||||
assign sha1h_qnin_v1[ 31:0] = {32{sha1h_v1_q}} & opa_v1[ 31:0];
|
||||
assign sha1su1_qdin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opb_v1[127:0];
|
||||
assign sha1su1_qnin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opa_v1[127:0];
|
||||
assign sha1su0_q_v1[127:0] = {128{sha1su0_v1_q}} & opc_v1[127:0];
|
||||
|
||||
herculesae_vx_sha1 u_sha1(
|
||||
.sha1h_v1_i (sha1h_v1_q),
|
||||
.sha1su0_v1_i (sha1su0_v1_q),
|
||||
.sha1su1_v1_i (sha1su1_v1_q),
|
||||
.sha1h_qn (sha1h_qnin_v1[31:0]),
|
||||
.sha1su0_qd (sha1su0_q_v1[127:0]),
|
||||
.sha1su1_qd (sha1su1_qdin_v1[127:0]),
|
||||
.sha1su1_qn (sha1su1_qnin_v1[127:0]),
|
||||
.sha1_v1_o (sha1_out_v1[127:0]));
|
||||
|
||||
|
||||
|
||||
assign sha256su0_qdin_v1[127:0] = {128{sha256su0_v1_q}} & opb_v1[127:0];
|
||||
assign sha256su0_qnin_v1[127:0] = {128{sha256su0_v1_q}} & opa_v1[127:0];
|
||||
|
||||
herculesae_vx_sha256su0 u_sha256su0(
|
||||
.qd (sha256su0_qdin_v1[127:0]),
|
||||
.qn (sha256su0_qnin_v1[ 31:0]),
|
||||
.sumd (sumnr1c_v1[31:0]),
|
||||
.suma (sum_sha256su0_v1[31:0]),
|
||||
.sumb (carry_sha256su0_v1[31:0]),
|
||||
.d (sha256su0_out_v1[127:0]));
|
||||
|
||||
|
||||
|
||||
|
||||
herculesae_vx_sha256su1 u_sha256su1_v1(
|
||||
.sha256su1_x_op (sha256su1_dup_x_v1_q),
|
||||
.sha256su1_y_op (sha256su1_dup_y_v1_q),
|
||||
.sha256su1_z_op (sha256su1_dup_z_v1_q),
|
||||
.x (opc_v1[63:0]),
|
||||
.y (opa_v1[95:32]),
|
||||
.z (opb_v1[127:64]),
|
||||
.sumnr (sumnr1c_v1[63:0]),
|
||||
.sum_3to2 (sum_sha256su1_v1[63:0]),
|
||||
.carry_3to2 (carry_sha256su1_v1[63:0]),
|
||||
.newx (sha256su1_x_v1[63:0]));
|
||||
|
||||
|
||||
|
||||
assign x_v1[127:0] = opc_v1[127:0];
|
||||
assign y_v1[127:0] = opa_v1[127:0];
|
||||
assign z_v1[127:0] = opb_v1[127:0];
|
||||
|
||||
assign sha1_xin_v1[127:0] = {128{sha1cpm_v1_q}} & x_v1[127:0];
|
||||
assign sha1_yin_v1[31:0] = { 32{sha1cpm_v1_q}} & y_v1[31:0];
|
||||
assign sha1_zin_v1[31:0] = { 32{sha1cpm_v1_q}} & z_v1[31:0];
|
||||
|
||||
herculesae_vx_sha1cpm u_sha1cpm_v1(
|
||||
.choose (sha1c_v1_q),
|
||||
.parity (sha1p_v1_q),
|
||||
.majority (sha1m_v1_q),
|
||||
.cpm (sha1cpm_v1_q),
|
||||
.x (sha1_xin_v1[127:0]),
|
||||
.y (sha1_yin_v1[31:0]),
|
||||
.z (sha1_zin_v1[31:0]),
|
||||
.t2 (sumnr1c_v1[31:0]),
|
||||
.fa1_s (sum_sha1cpm_v1[31:0]),
|
||||
.fa1_c (carry_sha1cpm_v1[31:0]),
|
||||
.newx (sha1cpm_x_v1[127:0]),
|
||||
.newy (sha1cpm_y_v1[31:0]));
|
||||
assign sha1cpm_y_v1[127:32] = {96{sha1cpm_v1_q}} & y_v1[127:32];
|
||||
|
||||
assign sha256_xin_v1[127:0] = {128{sha256hh2_v1_q}} & x_v1[127:0];
|
||||
assign sha256_yin_v1[127:0] = {128{sha256hh2_v1_q}} & y_v1[127:0];
|
||||
assign sha256_zin_v1[ 31:0] = {32{ sha256hh2_v1_q}} & z_v1[31:0];
|
||||
|
||||
herculesae_vx_sha256h32 u_sha256h32_v1(
|
||||
.x (sha256_xin_v1[127:0]),
|
||||
.y (sha256_yin_v1[127:0]),
|
||||
.z (sha256_zin_v1[31:0]),
|
||||
.sumnr (sumnr1c_v1[63:0]),
|
||||
.sum (sum_sha256h32_v1[63:0]),
|
||||
.carry (carry_sha256h32_v1[63:0]),
|
||||
.newx (sha256h_x_v1[127:0]),
|
||||
.newy (sha256h_y_v1[127:0]));
|
||||
|
||||
|
||||
assign sum1c_v1[31:0] = {32{sha256su0_v1_q}} & sum_sha256su0_v1[31:0]
|
||||
| {32{sha1cpm_v1_q }} & sum_sha1cpm_v1[31:0]
|
||||
| {32{sha256hh2_v1_q}} & sum_sha256h32_v1[31:0]
|
||||
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[31:0];
|
||||
assign carry1c_v1[31:0] = {32{sha256su0_v1_q}} & carry_sha256su0_v1[31:0]
|
||||
| {32{sha1cpm_v1_q }} & carry_sha1cpm_v1[31:0]
|
||||
| {32{sha256hh2_v1_q}} & carry_sha256h32_v1[31:0]
|
||||
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[31:0];
|
||||
|
||||
|
||||
assign {unused_cout1c_v1, sumnr1c_v1[31:0]} = sum1c_v1[31:0] + carry1c_v1[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign sum1c_v1[63:32] = {32{sha256hh2_v1_q}} & sum_sha256h32_v1[63:32]
|
||||
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[63:32];
|
||||
assign carry1c_v1[63:32] = {32{sha256hh2_v1_q}} & carry_sha256h32_v1[63:32]
|
||||
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[63:32];
|
||||
|
||||
|
||||
assign {unused_cout1c2_v1, sumnr1c_v1[63:32]} = sum1c_v1[63:32] + carry1c_v1[63:32] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
assign sha_inst_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q | sha256su0_v1_q;
|
||||
|
||||
assign block_opa_passthrough = sha_inst_v1 | sha256su1_v1_q |
|
||||
sha256hh2_v1_q | sha1cpm_v1_q;
|
||||
|
||||
assign newa_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_y_v1[127:0])
|
||||
| ({128{sha256hh2_v1_q}} & sha256h_y_v1[127:0])
|
||||
| ({128{sha256su1_v1_q}} & {opb_v1[31:0],opa_v1[127:32]})
|
||||
| ({128{sha256su0_v1_q}} & sha256su0_out_v1[127:0])
|
||||
| ({128{sha1_v1}} & sha1_out_v1[127:0])
|
||||
| ({128{~(block_opa_passthrough)}} & opa_v1[127:0]);
|
||||
|
||||
assign newb_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_x_v1[127:0])
|
||||
| ({128{sha256hh2_v1_q}} & sha256h_x_v1[127:0])
|
||||
| ({128{sha256su1_v1_q}} & {opc_v1[127:64], sha256su1_x_v1[63:0]});
|
||||
|
||||
assign newc_v1[95:0] = opb_v1[127:32];
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_opa_v2_q_127_0_grp
|
||||
if (reset == 1'b1) begin
|
||||
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
|
||||
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
|
||||
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
|
||||
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1) begin
|
||||
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
|
||||
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
|
||||
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
assign x_v2[127:0] = opb_v2_q[127:0];
|
||||
assign y_v2[127:0] = opa_v2_q[127:0];
|
||||
assign z_v2[95:0] = opc_v2_q[95:0];
|
||||
|
||||
|
||||
herculesae_vx_sha256su1 u_sha256su1_v2(
|
||||
.sha256su1_x_op (sha256su1_dup_x_v2_q),
|
||||
.sha256su1_y_op (sha256su1_dup_y_v2_q),
|
||||
.sha256su1_z_op (sha256su1_dup_z_v2_q),
|
||||
.x (x_v2[127:64]),
|
||||
.y (y_v2[127:64]),
|
||||
.z (x_v2[63:0]),
|
||||
.sumnr (sumres_sha256su1_v2[63:0]),
|
||||
.sum_3to2 (sum_sha256su1_v2[63:0]),
|
||||
.carry_3to2 (carry_sha256su1_v2[63:0]),
|
||||
.newx (sha256su1_x_v2[63:0]));
|
||||
|
||||
|
||||
|
||||
herculesae_vx_sha1cpm u_sha1cpm_v2(
|
||||
.choose (sha1c_v2_q),
|
||||
.parity (sha1p_v2_q),
|
||||
.majority (sha1m_v2_q),
|
||||
.cpm (sha1cpm_v2_q),
|
||||
.x (x_v2[127:0]),
|
||||
.y (y_v2[31:0]),
|
||||
.z (z_v2[31:0]),
|
||||
.t2 (sumnr_2c4c_v2[31:0]),
|
||||
.fa1_s (sum_sha1cpm_v2[31:0]),
|
||||
.fa1_c (carry_sha1cpm_v2[31:0]),
|
||||
.newx (sha1cpm_x_v2[127:0]),
|
||||
.newy (sha1cpm_y_v2[31:0]));
|
||||
|
||||
assign sha1cpm_y_v2[127:32] = y_v2[127:32];
|
||||
|
||||
herculesae_vx_sha256h32 u_sha256h32_v2(
|
||||
.x (x_v2[127:0]),
|
||||
.y (y_v2[127:0]),
|
||||
.z (z_v2[31:0]),
|
||||
.sumnr (sumnr_2c4c_v2[63:0]),
|
||||
.sum (sum_sha256h32_v2[63:0]),
|
||||
.carry (carry_sha256h32_v2[63:0]),
|
||||
.newx (sha256h_x_v2[127:0]),
|
||||
.newy (sha256h_y_v2[127:0]));
|
||||
|
||||
|
||||
assign sha256hh2_v2 = sha256h_v2_q | sha256h2_v2_q;
|
||||
|
||||
|
||||
assign sum_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & sum_sha1cpm_v2[31:0] |
|
||||
{32{sha256hh2_v2}} & sum_sha256h32_v2[31:0];
|
||||
assign carry_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & carry_sha1cpm_v2[31:0] |
|
||||
{32{sha256hh2_v2}} & carry_sha256h32_v2[31:0];
|
||||
|
||||
assign {unused_cout_2c4c_v2, sumnr_2c4c_v2[31:0]} = sum_2c4c_v2[31:0] + carry_2c4c_v2[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
|
||||
assign sum_2c4c_v2[63:32] = {32{sha256hh2_v2}} & sum_sha256h32_v2[63:32];
|
||||
assign carry_2c4c_v2[63:32] = {32{sha256hh2_v2}} & carry_sha256h32_v2[63:32];
|
||||
|
||||
assign {unused_cout2_2c4c_v2, sumnr_2c4c_v2[63:32]} = sum_2c4c_v2[63:32] + carry_2c4c_v2[63:32] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
assign {unused_cout_sha256su1l_v2, sumres_sha256su1_v2[31:0]} = sum_sha256su1_v2[31:0] + carry_sha256su1_v2[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign {unused_cout_sha256su1h_v2, sumres_sha256su1_v2[63:32]} = sum_sha256su1_v2[63:32] + carry_sha256su1_v2[63:32] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
assign newb_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_x_v2[127:0])
|
||||
| ({128{sha256hh2_v2}} & sha256h_x_v2[127:0]);
|
||||
|
||||
assign newa_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_y_v2[127:0])
|
||||
| ({128{sha256hh2_v2}} & sha256h_y_v2[127:0]);
|
||||
|
||||
|
||||
assign cryptout_v2[127:64] = ({64{sha256su1_h_v2_q}} & sha256su1_x_v2[63:0])
|
||||
| ({64{sha_inst_h_v2_q}} & opa_v2_q[127:64]);
|
||||
|
||||
assign cryptout_v2[63:0] = ({64{sha256su1_l_v2_q}} & opb_v2_q[63:0])
|
||||
| ({64{sha_inst_l_v2_q}} & opa_v2_q[63:0]);
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_opa_v3_q_127_0_grp
|
||||
if (reset == 1'b1) begin
|
||||
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
|
||||
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
|
||||
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
|
||||
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v2_4latency == 1'b1) begin
|
||||
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
|
||||
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
|
||||
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign x_v3[127:0] = opb_v3_q[127:0];
|
||||
assign y_v3[127:0] = opa_v3_q[127:0];
|
||||
assign z_v3[63:0] = opc_v3_q[63:0];
|
||||
|
||||
herculesae_vx_sha1cpm u_sha1cpm_v3(
|
||||
.choose (sha1c_v3_q),
|
||||
.parity (sha1p_v3_q),
|
||||
.majority (sha1m_v3_q),
|
||||
.cpm (sha1cpm_v3_q),
|
||||
.x (x_v3[127:0]),
|
||||
.y (y_v3[31:0]),
|
||||
.z (z_v3[31:0]),
|
||||
.t2 (sumnr4c_v3[31:0]),
|
||||
.fa1_s (sum_sha1cpm_v3[31:0]),
|
||||
.fa1_c (carry_sha1cpm_v3[31:0]),
|
||||
.newx (sha1cpm_x_v3[127:0]),
|
||||
.newy (sha1cpm_y_v3[31:0]));
|
||||
assign sha1cpm_y_v3[127:32] = y_v3[127:32];
|
||||
|
||||
herculesae_vx_sha256h32 u_sha256h32_v3(
|
||||
.x (x_v3[127:0]),
|
||||
.y (y_v3[127:0]),
|
||||
.z (z_v3[31:0]),
|
||||
.sumnr (sumnr4c_v3[63:0]),
|
||||
.sum (sum_sha256h32_v3[63:0]),
|
||||
.carry (carry_sha256h32_v3[63:0]),
|
||||
.newx (sha256h_x_v3[127:0]),
|
||||
.newy (sha256h_y_v3[127:0]));
|
||||
|
||||
assign tchoose_v3[31:0] = (sha256h_y_v3[31:0] & sha256h_y_v3[63:32]) |
|
||||
(~sha256h_y_v3[31:0] & sha256h_y_v3[95:64]);
|
||||
|
||||
assign tmajority_v3[31:0] = (sha256h_x_v3[31:0] & sha256h_x_v3[63:32]) |
|
||||
(sha256h_x_v3[31:0] & sha256h_x_v3[95:64]) |
|
||||
(sha256h_x_v3[63:32] & sha256h_x_v3[95:64]);
|
||||
|
||||
assign sigma0_v3[31:0] = {sha256h_x_v3[1:0], sha256h_x_v3[31:2]}
|
||||
^ {sha256h_x_v3[12:0], sha256h_x_v3[31:13]}
|
||||
^ {sha256h_x_v3[21:0], sha256h_x_v3[31:22]};
|
||||
|
||||
assign sigma1_v3[31:0] = {sha256h_y_v3[5:0], sha256h_y_v3[31:6]}
|
||||
^ {sha256h_y_v3[10:0], sha256h_y_v3[31:11]}
|
||||
^ {sha256h_y_v3[24:0], sha256h_y_v3[31:25]};
|
||||
|
||||
|
||||
assign xy_fa0_s_v3[31:0] = sha256h_y_v3[127:96] ^ z_v3[63:32] ^ tchoose_v3[31:0];
|
||||
|
||||
assign xy_fa0_c_v3[32:0] = {sha256h_y_v3[127:96] & z_v3[63:32] | tchoose_v3[31:0] &
|
||||
(sha256h_y_v3[127:96] | z_v3[63:32]), 1'b0};
|
||||
|
||||
|
||||
|
||||
assign xy_fa1_s_v3[31:0] = xy_fa0_s_v3[31:0] ^ xy_fa0_c_v3[31:0] ^ sigma1_v3[31:0];
|
||||
|
||||
assign xy_fa1_c_v3[32:0] = {xy_fa0_s_v3[31:0] & xy_fa0_c_v3[31:0] | sigma1_v3[31:0] &
|
||||
(xy_fa0_s_v3[31:0] | xy_fa0_c_v3[31:0]), 1'b0};
|
||||
|
||||
|
||||
assign sha256hh2_v3 = sha256h_v3_q | sha256h2_v3_q;
|
||||
|
||||
assign sum4c_v3[31:0] = {32{sha1cpm_v3_q}} & sum_sha1cpm_v3[31:0] |
|
||||
{32{sha256hh2_v3}} & sum_sha256h32_v3[31:0];
|
||||
assign carry4c_v3[31:0] = {32{sha1cpm_v3_q}} & carry_sha1cpm_v3[31:0] |
|
||||
{32{sha256hh2_v3}} & carry_sha256h32_v3[31:0];
|
||||
|
||||
assign {unused_cout4c_v3, sumnr4c_v3[31:0]} = sum4c_v3[31:0] + carry4c_v3[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign sum4c_v3[63:32] = sum_sha256h32_v3[63:32];
|
||||
assign carry4c_v3[63:32] = carry_sha256h32_v3[63:32];
|
||||
|
||||
assign {unused_cout2_4c_v3, sumnr4c_v3[63:32]} = sum4c_v3[63:32] + carry4c_v3[63:32] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
|
||||
assign newa_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_y_v3[127:0])
|
||||
| ({128{sha256h_v3_q}} & {sigma0_v3[31:0], tmajority_v3[31:0],
|
||||
xy_fa1_s_v3[31:0], xy_fa1_c_v3[31:0]})
|
||||
| ({128{sha256h2_v3_q}} & {sigma0_v3[31:0],tmajority_v3[31:0],
|
||||
xy_fa1_s_v3[31:0],xy_fa1_c_v3[31:0]});
|
||||
|
||||
assign newb_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_x_v3[127:0])
|
||||
| ({128{sha256h_v3_q }} & sha256h_x_v3[127:0])
|
||||
| ({128{sha256h2_v3_q }} & {sha256h_x_v3[127:96], sha256h_y_v3[95:0]});
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_opb_v4_q_127_0_grp
|
||||
if (reset == 1'b1) begin
|
||||
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'b0}};
|
||||
end
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
|
||||
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
|
||||
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
|
||||
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
|
||||
end
|
||||
else if (reset == 1'b0 && ival_v3_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else begin
|
||||
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'bx}};
|
||||
end
|
||||
`else
|
||||
else if (ival_v3_q == 1'b1) begin
|
||||
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
|
||||
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
|
||||
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
|
||||
end
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign x_v4[127:0] = opb_v4_q[127:0];
|
||||
assign y_v4[127:0] = opa_v4_q[127:0];
|
||||
assign z_v4[31:0] = opc_v4_q[31:0];
|
||||
|
||||
herculesae_vx_sha1cpm u_sha1cpm_v4(
|
||||
.choose (sha1c_v4_q),
|
||||
.parity (sha1p_v4_q),
|
||||
.majority (sha1m_v4_q),
|
||||
.cpm (sha1cpm_v4_q),
|
||||
.x (x_v4[127:0]),
|
||||
.y (y_v4[31:0]),
|
||||
.z (z_v4[31:0]),
|
||||
.t2 (sumnr4c_v4[31:0]),
|
||||
.fa1_s (sum_sha1cpm_v4[31:0]),
|
||||
.fa1_c (carry_sha1cpm_v4[31:0]),
|
||||
.newx (sha1cpm_x_v4[127:0]),
|
||||
.newy (sha1cpm_y_v4[31:0]));
|
||||
|
||||
assign sigma0_v4[31:0] = y_v4[127:96];
|
||||
assign tmajority_v4[31:0] = y_v4[95:64];
|
||||
assign xy_fa1_s_v4[31:0] = y_v4[63:32];
|
||||
assign xy_fa1_c_v4[31:0] = y_v4[31:0];
|
||||
|
||||
assign x_fa2_s_v4[31:0] = xy_fa1_s_v4[31:0] ^ xy_fa1_c_v4[31:0] ^ x_v4[127:96];
|
||||
assign x_fa2_c_v4[32:0] = {xy_fa1_s_v4[31:0] & xy_fa1_c_v4[31:0] |
|
||||
x_v4[127:96] & (xy_fa1_s_v4[31:0] |
|
||||
xy_fa1_c_v4[31:0]), 1'b0};
|
||||
|
||||
assign y_fa2_s_v4[31:0] = sigma0_v4[31:0] ^ tmajority_v4[31:0] ^ xy_fa1_c_v4[31:0];
|
||||
|
||||
assign y_fa2_c_v4[32:0] = {sigma0_v4[31:0] & tmajority_v4[31:0] |
|
||||
xy_fa1_c_v4[31:0] & (sigma0_v4[31:0] |
|
||||
tmajority_v4[31:0]), 1'b0};
|
||||
|
||||
|
||||
assign y_fa3_s_v4[31:0] = y_fa2_s_v4[31:0] ^ y_fa2_c_v4[31:0] ^ xy_fa1_s_v4[31:0];
|
||||
assign y_fa3_c_v4[32:0] = {y_fa2_s_v4[31:0] & y_fa2_c_v4[31:0] |
|
||||
xy_fa1_s_v4[31:0] & (y_fa2_s_v4[31:0] |
|
||||
y_fa2_c_v4[31:0]), 1'b0};
|
||||
|
||||
|
||||
assign {xprime_carry, xprime_v4[127:96]} = x_fa2_s_v4[31:0] + x_fa2_c_v4[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
|
||||
assign sha256hh2_v4 = sha256h_v4_q | sha256h2_v4_q;
|
||||
assign sum_sha256h32_v4[31:0] = y_fa3_s_v4[31:0];
|
||||
assign carry_sha256h32_v4[31:0] = y_fa3_c_v4[31:0];
|
||||
|
||||
assign sum4c_v4[31:0] = {32{sha1cpm_v4_q}} & sum_sha1cpm_v4[31:0] |
|
||||
{32{sha256hh2_v4}} & sum_sha256h32_v4[31:0];
|
||||
assign carry4c_v4[31:0] = {32{sha1cpm_v4_q}} & carry_sha1cpm_v4[31:0] |
|
||||
{32{sha256hh2_v4}} & carry_sha256h32_v4[31:0];
|
||||
|
||||
assign {unused_cout4c_v4, sumnr4c_v4[31:0]} = sum4c_v4[31:0] + carry4c_v4[31:0] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
assign yprime_v4[127:96] = sumnr4c_v4[31:0];
|
||||
|
||||
assign newx_v4[127:0] = {x_v4[95:0], yprime_v4[127:96]};
|
||||
assign newy_v4[127:0] = {x_v4[95:0], xprime_v4[127:96]};
|
||||
|
||||
assign sha256h_x_v4[127:0] = newx_v4[127:0];
|
||||
assign sha256h_y_v4[127:0] = newy_v4[127:0];
|
||||
|
||||
|
||||
assign cryptout_v4[63:0] = ({64{sha1cpm_l_v4_q}} & sha1cpm_x_v4[63:0])
|
||||
| ({64{sha256h_l_v4_q}} & sha256h_x_v4[63:0])
|
||||
| ({64{sha256h2_l_v4_q}} & sha256h_y_v4[63:0]);
|
||||
|
||||
assign cryptout_v4[127:64] = ({64{sha1cpm_h_v4_q}} & sha1cpm_x_v4[127:64])
|
||||
| ({64{sha256h_h_v4_q}} & sha256h_x_v4[127:64])
|
||||
| ({64{sha256h2_h_v4_q}} & sha256h_y_v4[127:64]);
|
||||
|
||||
|
||||
assign crypt_active = ival_v1_or_v2;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,257 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_pmull
|
||||
(
|
||||
|
||||
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire ival_v1_q,
|
||||
|
||||
input wire [63:0] opa_v1,
|
||||
input wire [63:0] opb_v1,
|
||||
|
||||
output reg [127:0] pmullout_v2_q
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [63:0] a_in;
|
||||
wire [63:0] b_in;
|
||||
wire [127:0] p_out;
|
||||
wire [63:0] pp0;
|
||||
wire [63:0] pp1;
|
||||
wire [63:0] pp2;
|
||||
wire [63:0] pp3;
|
||||
wire [63:0] pp4;
|
||||
wire [63:0] pp5;
|
||||
wire [63:0] pp6;
|
||||
wire [63:0] pp7;
|
||||
wire [63:0] pp8;
|
||||
wire [63:0] pp9;
|
||||
wire [63:0] pp10;
|
||||
wire [63:0] pp11;
|
||||
wire [63:0] pp12;
|
||||
wire [63:0] pp13;
|
||||
wire [63:0] pp14;
|
||||
wire [63:0] pp15;
|
||||
wire [63:0] pp16;
|
||||
wire [63:0] pp17;
|
||||
wire [63:0] pp18;
|
||||
wire [63:0] pp19;
|
||||
wire [63:0] pp20;
|
||||
wire [63:0] pp21;
|
||||
wire [63:0] pp22;
|
||||
wire [63:0] pp23;
|
||||
wire [63:0] pp24;
|
||||
wire [63:0] pp25;
|
||||
wire [63:0] pp26;
|
||||
wire [63:0] pp27;
|
||||
wire [63:0] pp28;
|
||||
wire [63:0] pp29;
|
||||
wire [63:0] pp30;
|
||||
wire [63:0] pp31;
|
||||
wire [63:0] pp32;
|
||||
wire [63:0] pp33;
|
||||
wire [63:0] pp34;
|
||||
wire [63:0] pp35;
|
||||
wire [63:0] pp36;
|
||||
wire [63:0] pp37;
|
||||
wire [63:0] pp38;
|
||||
wire [63:0] pp39;
|
||||
wire [63:0] pp40;
|
||||
wire [63:0] pp41;
|
||||
wire [63:0] pp42;
|
||||
wire [63:0] pp43;
|
||||
wire [63:0] pp44;
|
||||
wire [63:0] pp45;
|
||||
wire [63:0] pp46;
|
||||
wire [63:0] pp47;
|
||||
wire [63:0] pp48;
|
||||
wire [63:0] pp49;
|
||||
wire [63:0] pp50;
|
||||
wire [63:0] pp51;
|
||||
wire [63:0] pp52;
|
||||
wire [63:0] pp53;
|
||||
wire [63:0] pp54;
|
||||
wire [63:0] pp55;
|
||||
wire [63:0] pp56;
|
||||
wire [63:0] pp57;
|
||||
wire [63:0] pp58;
|
||||
wire [63:0] pp59;
|
||||
wire [63:0] pp60;
|
||||
wire [63:0] pp61;
|
||||
wire [63:0] pp62;
|
||||
wire [63:0] pp63;
|
||||
wire [66:0] rednl0_0;
|
||||
wire [66:0] rednl0_1;
|
||||
wire [66:0] rednl0_2;
|
||||
wire [66:0] rednl0_3;
|
||||
wire [66:0] rednl0_4;
|
||||
wire [66:0] rednl0_5;
|
||||
wire [66:0] rednl0_6;
|
||||
wire [66:0] rednl0_7;
|
||||
wire [66:0] rednl0_8;
|
||||
wire [66:0] rednl0_9;
|
||||
wire [66:0] rednl0_10;
|
||||
wire [66:0] rednl0_11;
|
||||
wire [66:0] rednl0_12;
|
||||
wire [66:0] rednl0_13;
|
||||
wire [66:0] rednl0_14;
|
||||
wire [66:0] rednl0_15;
|
||||
wire [78:0] rednl1_0;
|
||||
wire [78:0] rednl1_1;
|
||||
wire [78:0] rednl1_2;
|
||||
wire [78:0] rednl1_3;
|
||||
|
||||
|
||||
assign a_in[63:0] = opa_v1[63:0];
|
||||
assign b_in[63:0] = opb_v1[63:0];
|
||||
assign pp0[63:0] = {64{a_in[ 0]}} & b_in[63:0];
|
||||
assign pp1[63:0] = {64{a_in[ 1]}} & b_in[63:0];
|
||||
assign pp2[63:0] = {64{a_in[ 2]}} & b_in[63:0];
|
||||
assign pp3[63:0] = {64{a_in[ 3]}} & b_in[63:0];
|
||||
assign pp4[63:0] = {64{a_in[ 4]}} & b_in[63:0];
|
||||
assign pp5[63:0] = {64{a_in[ 5]}} & b_in[63:0];
|
||||
assign pp6[63:0] = {64{a_in[ 6]}} & b_in[63:0];
|
||||
assign pp7[63:0] = {64{a_in[ 7]}} & b_in[63:0];
|
||||
assign pp8[63:0] = {64{a_in[ 8]}} & b_in[63:0];
|
||||
assign pp9[63:0] = {64{a_in[ 9]}} & b_in[63:0];
|
||||
assign pp10[63:0] = {64{a_in[10]}} & b_in[63:0];
|
||||
assign pp11[63:0] = {64{a_in[11]}} & b_in[63:0];
|
||||
assign pp12[63:0] = {64{a_in[12]}} & b_in[63:0];
|
||||
assign pp13[63:0] = {64{a_in[13]}} & b_in[63:0];
|
||||
assign pp14[63:0] = {64{a_in[14]}} & b_in[63:0];
|
||||
assign pp15[63:0] = {64{a_in[15]}} & b_in[63:0];
|
||||
assign pp16[63:0] = {64{a_in[16]}} & b_in[63:0];
|
||||
assign pp17[63:0] = {64{a_in[17]}} & b_in[63:0];
|
||||
assign pp18[63:0] = {64{a_in[18]}} & b_in[63:0];
|
||||
assign pp19[63:0] = {64{a_in[19]}} & b_in[63:0];
|
||||
assign pp20[63:0] = {64{a_in[20]}} & b_in[63:0];
|
||||
assign pp21[63:0] = {64{a_in[21]}} & b_in[63:0];
|
||||
assign pp22[63:0] = {64{a_in[22]}} & b_in[63:0];
|
||||
assign pp23[63:0] = {64{a_in[23]}} & b_in[63:0];
|
||||
assign pp24[63:0] = {64{a_in[24]}} & b_in[63:0];
|
||||
assign pp25[63:0] = {64{a_in[25]}} & b_in[63:0];
|
||||
assign pp26[63:0] = {64{a_in[26]}} & b_in[63:0];
|
||||
assign pp27[63:0] = {64{a_in[27]}} & b_in[63:0];
|
||||
assign pp28[63:0] = {64{a_in[28]}} & b_in[63:0];
|
||||
assign pp29[63:0] = {64{a_in[29]}} & b_in[63:0];
|
||||
assign pp30[63:0] = {64{a_in[30]}} & b_in[63:0];
|
||||
assign pp31[63:0] = {64{a_in[31]}} & b_in[63:0];
|
||||
assign pp32[63:0] = {64{a_in[32]}} & b_in[63:0];
|
||||
assign pp33[63:0] = {64{a_in[33]}} & b_in[63:0];
|
||||
assign pp34[63:0] = {64{a_in[34]}} & b_in[63:0];
|
||||
assign pp35[63:0] = {64{a_in[35]}} & b_in[63:0];
|
||||
assign pp36[63:0] = {64{a_in[36]}} & b_in[63:0];
|
||||
assign pp37[63:0] = {64{a_in[37]}} & b_in[63:0];
|
||||
assign pp38[63:0] = {64{a_in[38]}} & b_in[63:0];
|
||||
assign pp39[63:0] = {64{a_in[39]}} & b_in[63:0];
|
||||
assign pp40[63:0] = {64{a_in[40]}} & b_in[63:0];
|
||||
assign pp41[63:0] = {64{a_in[41]}} & b_in[63:0];
|
||||
assign pp42[63:0] = {64{a_in[42]}} & b_in[63:0];
|
||||
assign pp43[63:0] = {64{a_in[43]}} & b_in[63:0];
|
||||
assign pp44[63:0] = {64{a_in[44]}} & b_in[63:0];
|
||||
assign pp45[63:0] = {64{a_in[45]}} & b_in[63:0];
|
||||
assign pp46[63:0] = {64{a_in[46]}} & b_in[63:0];
|
||||
assign pp47[63:0] = {64{a_in[47]}} & b_in[63:0];
|
||||
assign pp48[63:0] = {64{a_in[48]}} & b_in[63:0];
|
||||
assign pp49[63:0] = {64{a_in[49]}} & b_in[63:0];
|
||||
assign pp50[63:0] = {64{a_in[50]}} & b_in[63:0];
|
||||
assign pp51[63:0] = {64{a_in[51]}} & b_in[63:0];
|
||||
assign pp52[63:0] = {64{a_in[52]}} & b_in[63:0];
|
||||
assign pp53[63:0] = {64{a_in[53]}} & b_in[63:0];
|
||||
assign pp54[63:0] = {64{a_in[54]}} & b_in[63:0];
|
||||
assign pp55[63:0] = {64{a_in[55]}} & b_in[63:0];
|
||||
assign pp56[63:0] = {64{a_in[56]}} & b_in[63:0];
|
||||
assign pp57[63:0] = {64{a_in[57]}} & b_in[63:0];
|
||||
assign pp58[63:0] = {64{a_in[58]}} & b_in[63:0];
|
||||
assign pp59[63:0] = {64{a_in[59]}} & b_in[63:0];
|
||||
assign pp60[63:0] = {64{a_in[60]}} & b_in[63:0];
|
||||
assign pp61[63:0] = {64{a_in[61]}} & b_in[63:0];
|
||||
assign pp62[63:0] = {64{a_in[62]}} & b_in[63:0];
|
||||
assign pp63[63:0] = {64{a_in[63]}} & b_in[63:0];
|
||||
|
||||
assign rednl0_0[66:0] = { pp3[63:0], 3'b000} ^ {1'b0, pp2[63:0], 2'b00} ^ {2'b00, pp1[63:0], 1'b0} ^ {3'b000, pp0[63:0]};
|
||||
assign rednl0_1[66:0] = { pp7[63:0], 3'b000} ^ {1'b0, pp6[63:0], 2'b00} ^ {2'b00, pp5[63:0], 1'b0} ^ {3'b000, pp4[63:0]};
|
||||
assign rednl0_2[66:0] = {pp11[63:0], 3'b000} ^ {1'b0, pp10[63:0], 2'b00} ^ {2'b00, pp9[63:0], 1'b0} ^ {3'b000, pp8[63:0]};
|
||||
assign rednl0_3[66:0] = {pp15[63:0], 3'b000} ^ {1'b0, pp14[63:0], 2'b00} ^ {2'b00, pp13[63:0], 1'b0} ^ {3'b000, pp12[63:0]};
|
||||
assign rednl0_4[66:0] = {pp19[63:0], 3'b000} ^ {1'b0, pp18[63:0], 2'b00} ^ {2'b00, pp17[63:0], 1'b0} ^ {3'b000, pp16[63:0]};
|
||||
assign rednl0_5[66:0] = {pp23[63:0], 3'b000} ^ {1'b0, pp22[63:0], 2'b00} ^ {2'b00, pp21[63:0], 1'b0} ^ {3'b000, pp20[63:0]};
|
||||
assign rednl0_6[66:0] = {pp27[63:0], 3'b000} ^ {1'b0, pp26[63:0], 2'b00} ^ {2'b00, pp25[63:0], 1'b0} ^ {3'b000, pp24[63:0]};
|
||||
assign rednl0_7[66:0] = {pp31[63:0], 3'b000} ^ {1'b0, pp30[63:0], 2'b00} ^ {2'b00, pp29[63:0], 1'b0} ^ {3'b000, pp28[63:0]};
|
||||
assign rednl0_8[66:0] = {pp35[63:0], 3'b000} ^ {1'b0, pp34[63:0], 2'b00} ^ {2'b00, pp33[63:0], 1'b0} ^ {3'b000, pp32[63:0]};
|
||||
assign rednl0_9[66:0] = {pp39[63:0], 3'b000} ^ {1'b0, pp38[63:0], 2'b00} ^ {2'b00, pp37[63:0], 1'b0} ^ {3'b000, pp36[63:0]};
|
||||
assign rednl0_10[66:0] = {pp43[63:0], 3'b000} ^ {1'b0, pp42[63:0], 2'b00} ^ {2'b00, pp41[63:0], 1'b0} ^ {3'b000, pp40[63:0]};
|
||||
assign rednl0_11[66:0] = {pp47[63:0], 3'b000} ^ {1'b0, pp46[63:0], 2'b00} ^ {2'b00, pp45[63:0], 1'b0} ^ {3'b000, pp44[63:0]};
|
||||
assign rednl0_12[66:0] = {pp51[63:0], 3'b000} ^ {1'b0, pp50[63:0], 2'b00} ^ {2'b00, pp49[63:0], 1'b0} ^ {3'b000, pp48[63:0]};
|
||||
assign rednl0_13[66:0] = {pp55[63:0], 3'b000} ^ {1'b0, pp54[63:0], 2'b00} ^ {2'b00, pp53[63:0], 1'b0} ^ {3'b000, pp52[63:0]};
|
||||
assign rednl0_14[66:0] = {pp59[63:0], 3'b000} ^ {1'b0, pp58[63:0], 2'b00} ^ {2'b00, pp57[63:0], 1'b0} ^ {3'b000, pp56[63:0]};
|
||||
assign rednl0_15[66:0] = {pp63[63:0], 3'b000} ^ {1'b0, pp62[63:0], 2'b00} ^ {2'b00, pp61[63:0], 1'b0} ^ {3'b000, pp60[63:0]};
|
||||
|
||||
assign rednl1_0[78:0] = { rednl0_3[66:0], 12'h000} ^ {4'h0, rednl0_2[66:0], 8'h00} ^ {8'h00, rednl0_1[66:0], 4'h0} ^ {12'h000, rednl0_0[66:0]};
|
||||
assign rednl1_1[78:0] = { rednl0_7[66:0], 12'h000} ^ {4'h0, rednl0_6[66:0], 8'h00} ^ {8'h00, rednl0_5[66:0], 4'h0} ^ {12'h000, rednl0_4[66:0]};
|
||||
assign rednl1_2[78:0] = {rednl0_11[66:0], 12'h000} ^ {4'h0, rednl0_10[66:0], 8'h00} ^ {8'h00, rednl0_9[66:0], 4'h0} ^ {12'h000, rednl0_8[66:0]};
|
||||
assign rednl1_3[78:0] = {rednl0_15[66:0], 12'h000} ^ {4'h0, rednl0_14[66:0], 8'h00} ^ {8'h00, rednl0_13[66:0], 4'h0} ^ {12'h000, rednl0_12[66:0]};
|
||||
|
||||
assign p_out[15: 0] = rednl1_0[15: 0];
|
||||
assign p_out[31: 16] = rednl1_1[15: 0] ^ rednl1_0[31:16];
|
||||
assign p_out[47: 32] = rednl1_2[15: 0] ^ rednl1_1[31:16] ^ rednl1_0[47:32];
|
||||
assign p_out[78: 48] = rednl1_3[30: 0] ^ rednl1_2[46:16] ^ rednl1_1[62:32] ^ rednl1_0[78:48];
|
||||
assign p_out[94: 79] = rednl1_3[46:31] ^ rednl1_2[62:47] ^ rednl1_1[78:63];
|
||||
assign p_out[110: 95] = rednl1_3[62:47] ^ rednl1_2[78:63];
|
||||
assign p_out[127:111] = {1'b0, rednl1_3[78:63]};
|
||||
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin: u_pmullout_v2_q_127_0
|
||||
if (reset == 1'b1)
|
||||
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
|
||||
`ifdef HERCULESAE_XPROP_FLOP
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b1)
|
||||
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
|
||||
else if (reset == 1'b0 && ival_v1_q == 1'b0)
|
||||
begin
|
||||
end
|
||||
else
|
||||
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
|
||||
`else
|
||||
else if (ival_v1_q == 1'b1)
|
||||
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
|
||||
`endif
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,78 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_sha1
|
||||
(
|
||||
|
||||
|
||||
input wire sha1h_v1_i,
|
||||
input wire sha1su0_v1_i,
|
||||
input wire sha1su1_v1_i,
|
||||
input wire [31:0] sha1h_qn,
|
||||
input wire [127:0] sha1su0_qd,
|
||||
input wire [127:0] sha1su1_qd,
|
||||
input wire [127:0] sha1su1_qn,
|
||||
|
||||
output wire [127:0] sha1_v1_o
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [31:0] sha1h_v1;
|
||||
wire [63:0] sha1su0_opa_v1;
|
||||
wire [127:0] sha1su0_opb_v1;
|
||||
wire [127:0] sha1su0_opc_v1;
|
||||
wire [127:0] sha1su0_v1;
|
||||
wire [127:0] sha1su1_v1;
|
||||
wire [127:0] t;
|
||||
|
||||
assign sha1h_v1[31:0] = {sha1h_qn[1:0], sha1h_qn[31:2]};
|
||||
|
||||
assign sha1su0_opa_v1[63:0] = sha1su1_qn[63:0];
|
||||
assign sha1su0_opb_v1[127:0] = sha1su1_qd[127:0];
|
||||
assign sha1su0_opc_v1[127:0] = sha1su0_qd[127:0];
|
||||
|
||||
assign sha1su0_v1 [127:0] = sha1su0_opc_v1[127:0]
|
||||
^ {sha1su0_opa_v1[63:0], sha1su0_opc_v1[127:64]}
|
||||
^ sha1su0_opb_v1[127:0];
|
||||
assign t[127:0] = sha1su1_qd[127:0] ^ {{32{1'b0}}, sha1su1_qn[127:32]};
|
||||
assign sha1su1_v1[127:96] = {t[126:96], t[127]} ^ {t[29:0], t[31:30]};
|
||||
assign sha1su1_v1[95:64] = {t[94:64], t[95]};
|
||||
assign sha1su1_v1[63:32] = {t[62:32], t[63]};
|
||||
assign sha1su1_v1[31:0] = {t[30:0], t[31]};
|
||||
|
||||
assign sha1_v1_o[127:0] = {128{sha1su0_v1_i}} & sha1su0_v1[127:0] |
|
||||
{128{sha1su1_v1_i}} & sha1su1_v1[127:0] |
|
||||
{128{sha1h_v1_i}} & {{96{1'b0}}, sha1h_v1[31:0]};
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,101 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_sha1cpm
|
||||
(
|
||||
|
||||
|
||||
input wire choose,
|
||||
input wire parity,
|
||||
input wire majority,
|
||||
input wire cpm,
|
||||
input wire [127:0] x,
|
||||
input wire [31:0] y,
|
||||
input wire [31:0] z,
|
||||
input wire [31:0] t2,
|
||||
output wire [31:0] fa1_s,
|
||||
output wire [31:0] fa1_c,
|
||||
output wire [127:0] newx,
|
||||
output wire [31:0] newy
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [32:0] fa0_c;
|
||||
wire [31:0] fa0_s;
|
||||
wire shacpm_nop;
|
||||
wire [31:0] t1_nop;
|
||||
wire [31:0] t1c;
|
||||
wire [31:0] t1m;
|
||||
wire [31:0] t1p;
|
||||
wire [127:0] x1;
|
||||
wire [127:0] x_nop;
|
||||
wire [31:0] x_rol5_nop;
|
||||
wire [31:0] y_nop;
|
||||
wire [31:0] z_nop;
|
||||
|
||||
assign shacpm_nop = ~cpm;
|
||||
|
||||
|
||||
assign t1c[31:0] = (x[63:32] & x[95:64]) | (~x[63:32] & x[127:96]);
|
||||
assign t1p[31:0] = x[63:32] ^ x[95:64] ^ x[127:96];
|
||||
assign t1m[31:0] = (x[63:32] & x[95:64])
|
||||
| (x[63:32] & x[127:96])
|
||||
| (x[95:64] & x[127:96]);
|
||||
assign t1_nop[31:0] = ({32{choose}} & t1c[31:0])
|
||||
| ({32{parity}} & t1p[31:0])
|
||||
| ({32{majority}} & t1m[31:0]);
|
||||
assign x_rol5_nop[31:0] = {32{~shacpm_nop}} & {x[26:0], x[31:27]};
|
||||
|
||||
|
||||
assign y_nop[31:0] = {32{~shacpm_nop}} & y[31:0];
|
||||
assign z_nop[31:0] = {32{~shacpm_nop}} & z[31:0];
|
||||
|
||||
assign fa0_s[31:0] = y_nop[31:0] ^ x_rol5_nop[31:0] ^ z_nop[31:0];
|
||||
assign fa0_c[32:0] = {y_nop[31:0] & x_rol5_nop[31:0] | z_nop[31:0] & (y_nop[31:0] | x_rol5_nop[31:0]), 1'b0};
|
||||
|
||||
assign fa1_s[31:0] = fa0_s[31:0] ^ fa0_c[31:0] ^ t1_nop[31:0];
|
||||
assign fa1_c[31:0] = {fa0_s[30:0] & fa0_c[30:0] | t1_nop[30:0] & (fa0_s[30:0] | fa0_c[30:0]), 1'b0};
|
||||
|
||||
|
||||
assign x_nop[127:0] = {128{~shacpm_nop}} & x[127:0];
|
||||
|
||||
assign x1[127:64] = x_nop[127:64];
|
||||
assign x1[63:32] = {x_nop[33:32], x_nop[63:34]};
|
||||
assign x1[31:0] = x_nop[31:0];
|
||||
|
||||
assign newx[127:0] = {x1[95:0], t2[31:0]};
|
||||
assign newy[31:0] = x1[127:96];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,104 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_sha256h32
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] x,
|
||||
input wire [127:0] y,
|
||||
input wire [31:0] z,
|
||||
|
||||
input wire [63:0] sumnr,
|
||||
output wire [63:0] sum,
|
||||
output wire [63:0] carry,
|
||||
output wire [127:0] newx,
|
||||
output wire [127:0] newy
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [31:0] sigma0;
|
||||
wire [31:0] sigma1;
|
||||
wire [31:0] tchoose;
|
||||
wire [31:0] tmajority;
|
||||
wire [32:0] x_fa2_c;
|
||||
wire [31:0] x_fa2_s;
|
||||
wire [127:96] xprime;
|
||||
wire [32:0] xy_fa0_c;
|
||||
wire [31:0] xy_fa0_s;
|
||||
wire [32:0] xy_fa1_c;
|
||||
wire [31:0] xy_fa1_s;
|
||||
wire [32:0] y_fa2_c;
|
||||
wire [31:0] y_fa2_s;
|
||||
wire [31:0] y_fa3_c;
|
||||
wire [31:0] y_fa3_s;
|
||||
wire [127:96] yprime;
|
||||
|
||||
|
||||
assign tchoose[31:0] = (y[31:0] & y[63:32]) | (~y[31:0] & y[95:64]);
|
||||
assign tmajority[31:0] = (x[31:0] & x[63:32]) | (x[31:0] & x[95:64]) | (x[63:32] & x[95:64]);
|
||||
assign sigma0[31:0] = {x[1:0], x[31:2]}
|
||||
^ {x[12:0], x[31:13]}
|
||||
^ {x[21:0], x[31:22]};
|
||||
assign sigma1[31:0] = {y[5:0], y[31:6]}
|
||||
^ {y[10:0], y[31:11]}
|
||||
^ {y[24:0], y[31:25]};
|
||||
|
||||
|
||||
assign xy_fa0_s[31:0] = y[127:96] ^ z[31:0] ^ tchoose[31:0];
|
||||
assign xy_fa0_c[32:0] = {y[127:96] & z[31:0] | tchoose[31:0] & (y[127:96] | z[31:0]), 1'b0};
|
||||
|
||||
assign xy_fa1_s[31:0] = xy_fa0_s[31:0] ^ xy_fa0_c[31:0] ^ sigma1[31:0];
|
||||
assign xy_fa1_c[32:0] = {xy_fa0_s[31:0] & xy_fa0_c[31:0] | sigma1[31:0] & (xy_fa0_s[31:0] | xy_fa0_c[31:0]), 1'b0};
|
||||
|
||||
assign x_fa2_s[31:0] = xy_fa1_s[31:0] ^ xy_fa1_c[31:0] ^ x[127:96];
|
||||
assign x_fa2_c[32:0] = {xy_fa1_s[31:0] & xy_fa1_c[31:0] | x[127:96] & (xy_fa1_s[31:0] | xy_fa1_c[31:0]), 1'b0};
|
||||
|
||||
assign y_fa2_s[31:0] = sigma0[31:0] ^ tmajority[31:0] ^ xy_fa1_c[31:0];
|
||||
assign y_fa2_c[32:0] = {sigma0[31:0] & tmajority[31:0] | xy_fa1_c[31:0] & (sigma0[31:0] | tmajority[31:0]), 1'b0};
|
||||
|
||||
assign y_fa3_s[31:0] = y_fa2_s[31:0] ^ y_fa2_c[31:0] ^ xy_fa1_s[31:0];
|
||||
assign y_fa3_c[31:0] = {y_fa2_s[30:0] & y_fa2_c[30:0] | xy_fa1_s[30:0] & (y_fa2_s[30:0] | y_fa2_c[30:0]), 1'b0};
|
||||
|
||||
assign sum[63:0] = {x_fa2_s[31:0], y_fa3_s[31:0]};
|
||||
assign carry[63:0] = {x_fa2_c[31:0], y_fa3_c[31:0]};
|
||||
assign xprime[127:96] = sumnr[63:32];
|
||||
assign yprime[127:96] = sumnr[31:0];
|
||||
|
||||
assign newx[127:0] = {x[95:0], yprime[127:96]};
|
||||
assign newy[127:0] = {y[95:0], xprime[127:96]};
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,76 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_sha256su0
|
||||
(
|
||||
|
||||
|
||||
input wire [127:0] qd,
|
||||
input wire [31:0] qn,
|
||||
input wire [31:0] sumd,
|
||||
output wire [31:0] suma,
|
||||
output wire [31:0] sumb,
|
||||
output wire [127:0] d
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire d1_cout;
|
||||
wire d2_cout;
|
||||
wire d3_cout;
|
||||
wire [127:0] t;
|
||||
wire [127:0] t0;
|
||||
|
||||
assign t[127:0] = {qn[31:0], qd[127:32]};
|
||||
assign t0[127:96] = {t[102:96], t[127:103]} ^ {t[113:96], t[127:114]} ^ {3'b000, t[127:99]};
|
||||
assign t0[95:64] = {t[ 70:64], t[ 95: 71]} ^ {t[ 81:64], t[ 95: 82]} ^ {3'b000, t[ 95:67]};
|
||||
assign t0[63:32] = {t[ 38:32], t[ 63: 39]} ^ {t[ 49:32], t[ 63: 50]} ^ {3'b000, t[ 63:35]};
|
||||
assign t0[31:0] = {t[ 6: 0], t[ 31: 7]} ^ {t[ 17: 0], t[ 31: 18]} ^ {3'b000, t[ 31: 3]};
|
||||
|
||||
|
||||
assign {d3_cout, d[127:96]} = t0[127:96] + qd[127:96] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign {d2_cout, d[95:64]} = t0[95:64] + qd[95:64] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign {d1_cout, d[63:32]} = t0[63:32] + qd[63:32] + {{31{1'b0}}, 1'b0};
|
||||
|
||||
|
||||
assign suma[31:0] = t0[31:0];
|
||||
assign sumb[31:0] = qd[31:0];
|
||||
assign d[31:0] = sumd[31:0];
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
@ -1,90 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// SystemVerilog (IEEE Std 1800-2012)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
`include "herculesae_header.sv"
|
||||
|
||||
|
||||
module herculesae_vx_sha256su1
|
||||
(
|
||||
|
||||
|
||||
input wire sha256su1_x_op,
|
||||
input wire sha256su1_y_op,
|
||||
input wire sha256su1_z_op,
|
||||
input wire [63:0] x,
|
||||
input wire [63:0] y,
|
||||
input wire [63:0] z,
|
||||
input wire [63:0] sumnr,
|
||||
output wire [63:0] sum_3to2,
|
||||
output wire [63:0] carry_3to2,
|
||||
output wire [63:0] newx
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire [63:0] carry;
|
||||
wire [63:0] sum;
|
||||
wire [63:0] x_nop;
|
||||
wire [63:0] y_nop;
|
||||
wire [63:0] z_nop;
|
||||
wire [63:0] z_rot;
|
||||
wire [63:0] zror17;
|
||||
wire [63:0] zror19;
|
||||
wire [63:0] zshr10;
|
||||
|
||||
|
||||
|
||||
|
||||
assign x_nop[63:0] = x[63:0] & {64{sha256su1_x_op}};
|
||||
assign y_nop[63:0] = y[63:0] & {64{sha256su1_y_op}};
|
||||
assign z_nop[63:0] = z[63:0] & {64{sha256su1_z_op}};
|
||||
|
||||
assign zror17[63:0] = {z_nop[48:32], z_nop[63:49],
|
||||
z_nop[16:0], z_nop[31:17]};
|
||||
assign zror19[63:0] = {z_nop[50:32], z_nop[63:51],
|
||||
z_nop[18:0], z_nop[31:19]};
|
||||
assign zshr10[63:0] = {10'b00_0000_0000, z_nop[63:42],
|
||||
10'b00_0000_0000, z_nop[31:10]};
|
||||
assign z_rot[63:0] = zror17[63:0] ^ zror19[63:0] ^ zshr10[63:0];
|
||||
|
||||
assign sum[63:0] = (x_nop[63:0] ^ y_nop[63:0]) ^ z_rot[63:0];
|
||||
assign carry[63:32] = {(x_nop[62:32] & y_nop[62:32])
|
||||
| (y_nop[62:32] & z_rot[62:32])
|
||||
| (x_nop[62:32] & z_rot[62:32]), 1'b0};
|
||||
assign carry[31:0] = {(x_nop[30:0] & y_nop[30:0])
|
||||
| (y_nop[30:0] & z_rot[30:0])
|
||||
| (x_nop[30:0] & z_rot[30:0]), 1'b0};
|
||||
|
||||
assign sum_3to2[63:0] = sum[63:0];
|
||||
assign carry_3to2[63:0] = carry[63:0];
|
||||
assign newx[63:0] = sumnr[63:0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`define HERCULESAE_UNDEFINE
|
||||
`include "herculesae_header.sv"
|
||||
`undef HERCULESAE_UNDEFINE
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,351 +0,0 @@
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited.
|
||||
//
|
||||
// (C) COPYRIGHT 2013-2014 ARM Limited.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited.
|
||||
//
|
||||
// Filename : $RCSfile: maia_cx_crypt2.v $
|
||||
// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $
|
||||
// Revision : $Revision: 70482 $
|
||||
// Release Information : Cortex-A72-r1p0-00rel0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// Verilog-2001 (IEEE Std 1364-2001)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
//#
|
||||
//# Overview
|
||||
//# ========
|
||||
//#
|
||||
|
||||
// This block does the following operations:
|
||||
// - AES encrypt and decrypt operations: aesd, aese, aesmc, aesimc
|
||||
// - SHA single-cycle operations: sha1h, sha1su1, sha256su0
|
||||
|
||||
//#
|
||||
//# Module Declaration
|
||||
//# ==================
|
||||
//#
|
||||
|
||||
`include "maia_header.v"
|
||||
|
||||
module maia_cx_crypt2 (
|
||||
|
||||
//#
|
||||
//# Interface Signals
|
||||
//# =================
|
||||
//#
|
||||
|
||||
// Global inputs
|
||||
ck_gclkcx_crypt,
|
||||
cx_reset3,
|
||||
|
||||
// Control inputs
|
||||
ival_e1_q,
|
||||
aesd_e1_q,
|
||||
aese_e1_q,
|
||||
aesmc_e1_q,
|
||||
aesimc_e1_q,
|
||||
aesdimc_e1_q,
|
||||
aesemc_e1_q,
|
||||
pmull_e1_q,
|
||||
sha1h_e1_q,
|
||||
sha1su1_e1_q,
|
||||
sha256su0_e1_q,
|
||||
|
||||
|
||||
// Data inputs
|
||||
qd,
|
||||
qn,
|
||||
|
||||
|
||||
// Outputs
|
||||
crypt2_out_e3_q,
|
||||
crypt2_active
|
||||
);
|
||||
|
||||
|
||||
//#
|
||||
//# Interface Signals
|
||||
//# =================
|
||||
//#
|
||||
|
||||
// Global inputs
|
||||
input ck_gclkcx_crypt;
|
||||
input cx_reset3;
|
||||
|
||||
// Control inputs
|
||||
input ival_e1_q;
|
||||
input aesd_e1_q; // aes encode
|
||||
input aese_e1_q; // aes decode
|
||||
input aesmc_e1_q; // ae smix columns
|
||||
input aesimc_e1_q; // aes inverse mix columns
|
||||
input aesdimc_e1_q; // aes decode superop
|
||||
input aesemc_e1_q; // aes encode superop
|
||||
input pmull_e1_q; // polynomial multiplication
|
||||
input sha1h_e1_q; // sha1 fixed rotate
|
||||
input sha1su1_e1_q; // sha1 schedule update 1
|
||||
input sha256su0_e1_q; // sha256 schedule update 0
|
||||
|
||||
|
||||
// Data inputs
|
||||
input [127:0] qd;
|
||||
input [127:0] qn;
|
||||
|
||||
|
||||
// Outputs
|
||||
output [127:0] crypt2_out_e3_q;
|
||||
output crypt2_active;
|
||||
|
||||
//#
|
||||
//# Internal Signals - Automatic Declarations
|
||||
//# =========================================
|
||||
//#
|
||||
wire [ 15: 0] aes_shf_e1;
|
||||
reg [ 15: 0] aes_shf_e2_q;
|
||||
wire [127: 0] aesd_e1;
|
||||
reg aesd_e2_q;
|
||||
wire aesd_or_e_e1;
|
||||
wire [127: 0] aesd_out;
|
||||
wire [ 15: 0] aesd_shf_e1;
|
||||
reg aesdimc_e2_q;
|
||||
wire [127: 0] aesdimc_out;
|
||||
wire [127: 0] aese_e1;
|
||||
reg aese_e2_q;
|
||||
wire [127: 0] aese_out;
|
||||
wire [ 15: 0] aese_shf_e1;
|
||||
reg aesemc_e2_q;
|
||||
wire [127: 0] aesemc_out;
|
||||
reg aesimc_e2_q;
|
||||
wire [127: 0] aesimc_in;
|
||||
wire [127: 0] aesimc_out;
|
||||
reg aesmc_e2_q;
|
||||
wire [127: 0] aesmc_in;
|
||||
wire [127: 0] aesmc_out;
|
||||
wire [127: 0] crypt2_d_e1;
|
||||
reg [127: 0] crypt2_d_e2_q;
|
||||
wire [127: 0] crypt2_out_e2;
|
||||
reg [127: 0] crypt2_out_e3_q;
|
||||
reg ival_e2_q;
|
||||
reg pmull_e2_q;
|
||||
wire [127: 0] pmull_out;
|
||||
wire [127: 0] qx_e1;
|
||||
wire [ 31: 0] sha1h_in_e1;
|
||||
wire [ 31: 0] sha1h_out_e1;
|
||||
wire [127: 0] sha1su1_out_e1;
|
||||
wire [127: 0] sha1su1_qdin_e1;
|
||||
wire [127: 0] sha1su1_qnin_e1;
|
||||
wire [127: 0] sha256su0_out_e1;
|
||||
wire sha_inst_e1;
|
||||
reg sha_inst_e2_q;
|
||||
|
||||
//#
|
||||
//# Main Code
|
||||
//# =========
|
||||
//#
|
||||
//
|
||||
|
||||
// aes functions are all in the same block because of limited result bus bandwidth.
|
||||
// Mais CX has 3x64-bit result buses, and each of these instructions produces
|
||||
// a 128-bit result. Two instructions could be issued in a cycle, but there is
|
||||
// no value in doing this because they could not both write results.
|
||||
//
|
||||
// The single-cycle 2-input SHA instructions are in the same block because they have the same inputs
|
||||
// and latency as the aes instructions.
|
||||
//
|
||||
// Originally, all functions in this block had single-cycle latency, but CX is unable to make use
|
||||
// of single-cycle latency. To reduce area, functionality is spread across E1 and E2
|
||||
// In particular, the AES SBOX and ISBOX functions are split into LUT(mult inverse) -> affine transform
|
||||
// & affine inverse transform -> LUT(mult inverse), so that they can share the same LUT.
|
||||
|
||||
// E1
|
||||
// 38% of this cycle is used up to drive qd and qn from the issq block. Therefore, the relatively
|
||||
// shallow SHA operations are performed in this cycle, along with some preliminary processing for AESE and AESD
|
||||
|
||||
assign qx_e1[127:0] = {128{aesd_or_e_e1}} & (qd[127:0] ^ qn[127:0]);
|
||||
|
||||
maia_cx_aese1 uaese1(
|
||||
.q (qx_e1[127:0]),
|
||||
.aese_out (aese_e1[127:0]),
|
||||
.aese_shf (aese_shf_e1[15:0])
|
||||
);
|
||||
|
||||
maia_cx_aesd1 uaesd1(
|
||||
.q (qx_e1[127:0]),
|
||||
.aesd_out (aesd_e1[127:0]),
|
||||
.aesd_shf (aesd_shf_e1[15:0])
|
||||
);
|
||||
|
||||
assign aesd_or_e_e1 = aesd_e1_q | aese_e1_q;
|
||||
|
||||
// Perform sha functions in E1 to save pipeline flops
|
||||
// and reduce complexity of multiplexer in E2
|
||||
|
||||
assign sha1h_in_e1[31:0] = {32{sha1h_e1_q}} & qn[31:0];
|
||||
|
||||
maia_cx_sha1h usha1h(
|
||||
.qn (sha1h_in_e1[31:0]),
|
||||
.d (sha1h_out_e1[31:0])
|
||||
);
|
||||
|
||||
assign sha1su1_qdin_e1[127:0] = {128{sha1su1_e1_q}} & qd[127:0];
|
||||
assign sha1su1_qnin_e1[127:0] = {128{sha1su1_e1_q}} & qn[127:0];
|
||||
|
||||
maia_cx_sha1su1 usha1su1(
|
||||
.qd (sha1su1_qdin_e1[127:0]),
|
||||
.qn (sha1su1_qnin_e1[127:0]),
|
||||
.d (sha1su1_out_e1[127:0])
|
||||
);
|
||||
|
||||
|
||||
maia_cx_sha256su0 usha256su0(
|
||||
.qd (qd[127:0]),
|
||||
.qn (qn[127:0]),
|
||||
.d (sha256su0_out_e1[127:0])
|
||||
);
|
||||
|
||||
assign sha_inst_e1 = sha1h_e1_q | sha1su1_e1_q | sha256su0_e1_q;
|
||||
|
||||
assign crypt2_d_e1[127:0] = ({128{sha1h_e1_q}} & {{96{1'b0}}, sha1h_out_e1[31:0]})
|
||||
| ({128{sha1su1_e1_q}} & sha1su1_out_e1[127:0])
|
||||
| ({128{sha256su0_e1_q}} & sha256su0_out_e1[127:0])
|
||||
| ({128{aese_e1_q}} & aese_e1[127:0])
|
||||
| ({128{aesd_e1_q}} & aesd_e1[127:0])
|
||||
| ({128{~(aesd_or_e_e1 | sha_inst_e1)}} & qn[127:0]);
|
||||
|
||||
assign aes_shf_e1[15:0] = {16{aese_e1_q}} & aese_shf_e1[15:0] |
|
||||
{16{aesd_e1_q}} & aesd_shf_e1[15:0];
|
||||
|
||||
// reset flop(s) since feeds into active signal used for RCG
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
|
||||
begin: uival_e2_q
|
||||
if (cx_reset3 == 1'b1)
|
||||
ival_e2_q <= `MAIA_DFF_DELAY {1{1'b0}};
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if (cx_reset3==1'b0)
|
||||
ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q;
|
||||
else
|
||||
ival_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else
|
||||
ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q;
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: ucrypt2_e2
|
||||
if (ival_e1_q==1'b1) begin
|
||||
crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY crypt2_d_e1[127:0];
|
||||
aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY aes_shf_e1[15:0];
|
||||
aesd_e2_q <= `MAIA_DFF_DELAY aesd_e1_q;
|
||||
aese_e2_q <= `MAIA_DFF_DELAY aese_e1_q;
|
||||
aesmc_e2_q <= `MAIA_DFF_DELAY aesmc_e1_q;
|
||||
aesimc_e2_q <= `MAIA_DFF_DELAY aesimc_e1_q;
|
||||
aesemc_e2_q <= `MAIA_DFF_DELAY aesemc_e1_q;
|
||||
aesdimc_e2_q <= `MAIA_DFF_DELAY aesdimc_e1_q;
|
||||
pmull_e2_q <= `MAIA_DFF_DELAY pmull_e1_q;
|
||||
sha_inst_e2_q <= `MAIA_DFF_DELAY sha_inst_e1;
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e1_q==1'b0));
|
||||
else begin
|
||||
crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY {16{1'bx}};
|
||||
aesd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
aese_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
aesmc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
aesimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
aesemc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
aesdimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
pmull_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha_inst_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// Enable data inputs for selected operation (glitch suppression in unused datapaths)
|
||||
assign aesmc_in[127:0] = {128{aesmc_e2_q }} & crypt2_d_e2_q[127:0];
|
||||
assign aesimc_in[127:0] = {128{aesimc_e2_q}} & crypt2_d_e2_q[127:0];
|
||||
|
||||
maia_cx_aesed2 uaesed2(
|
||||
.aes_din (crypt2_d_e2_q[127:0]),
|
||||
.aes_shf (aes_shf_e2_q[15:0]),
|
||||
.aesd_out (aesd_out[127:0]),
|
||||
.aese_out (aese_out[127:0]),
|
||||
.aesemc_out (aesemc_out[127:0]),
|
||||
.aesdimc_out (aesdimc_out[127:0])
|
||||
);
|
||||
|
||||
maia_cx_aesmc uaesmc(
|
||||
.d_in (aesmc_in[127:0]),
|
||||
.mc (aesmc_out[127:0])
|
||||
);
|
||||
|
||||
maia_cx_aesimc uaesimc(
|
||||
.d_in (aesimc_in[127:0]),
|
||||
.imc (aesimc_out[127:0])
|
||||
);
|
||||
|
||||
maia_cx_pmull upmull(
|
||||
.a_in (crypt2_d_e2_q[63:0]),
|
||||
.b_in (crypt2_d_e2_q[127:64]),
|
||||
.p_out (pmull_out[127:0])
|
||||
);
|
||||
|
||||
assign crypt2_out_e2[127:0] = ({128{aesd_e2_q & ~aesdimc_e2_q}} & aesd_out[127:0])
|
||||
| ({128{aese_e2_q & ~aesemc_e2_q}} & aese_out[127:0])
|
||||
| ({128{aesmc_e2_q}} & aesmc_out[127:0])
|
||||
| ({128{aesemc_e2_q}} & aesemc_out[127:0])
|
||||
| ({128{aesimc_e2_q}} & aesimc_out[127:0])
|
||||
| ({128{aesdimc_e2_q}} & aesdimc_out[127:0])
|
||||
| ({128{sha_inst_e2_q}} & crypt2_d_e2_q[127:0])
|
||||
| ({128{pmull_e2_q}} & pmull_out[127:0]);
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: ucrypt2_e3
|
||||
if (ival_e2_q==1'b1) begin
|
||||
crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY crypt2_out_e2[127:0];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e2_q==1'b0));
|
||||
else begin
|
||||
crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// regional clock gating (RCG) terms
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
assign crypt2_active = (ival_e1_q | ival_e2_q);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
//ARMAUTO UNDEF START
|
||||
`define MAIA_UNDEFINE
|
||||
`include "maia_header.v"
|
||||
`undef MAIA_UNDEFINE
|
||||
//ARMAUTO UNDEF END
|
||||
@ -1,713 +0,0 @@
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited.
|
||||
//
|
||||
// (C) COPYRIGHT 2013-2014 ARM Limited.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited.
|
||||
//
|
||||
// Filename : $RCSfile: maia_cx_crypt3.v $
|
||||
// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $
|
||||
// Revision : $Revision: 70482 $
|
||||
// Release Information : Cortex-A72-r1p0-00rel0
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// Verilog-2001 (IEEE Std 1364-2001)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
//#
|
||||
//# Overview
|
||||
//# ========
|
||||
//#
|
||||
|
||||
// This block does the following operations:
|
||||
// - SHA 3-input operations: sha1cpm, sha1su0, sha256h, sha256h2, sha256su1
|
||||
|
||||
//#
|
||||
//# Module Declaration
|
||||
//# ==================
|
||||
//#
|
||||
|
||||
`include "maia_header.v"
|
||||
|
||||
module maia_cx_crypt3 (
|
||||
|
||||
//#
|
||||
//# Interface Signals
|
||||
//# =================
|
||||
//#
|
||||
|
||||
// Global inputs
|
||||
ck_gclkcx_crypt,
|
||||
cx_reset3,
|
||||
|
||||
// Control inputs
|
||||
//
|
||||
// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to
|
||||
// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q,
|
||||
// which allows the operands to be stored in flops. We also get inputs indicating which
|
||||
// instruction is to be computed.
|
||||
//
|
||||
// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that
|
||||
// we should begin the computation.
|
||||
//
|
||||
// There are 4 execution stages, E2-E5.
|
||||
ival_e1_q,
|
||||
sha1c_e1_q,
|
||||
sha1p_e1_q,
|
||||
sha1m_e1_q,
|
||||
sha256h_e1_q,
|
||||
sha256h2_e1_q,
|
||||
sha256su1_e1_q,
|
||||
ival_e2_q,
|
||||
// Data inputs
|
||||
qn_e1_q,
|
||||
qm_e1_q,
|
||||
qd_e2_q,
|
||||
// Outputs
|
||||
crypt3_out_e6_q,
|
||||
crypt3_active
|
||||
);
|
||||
|
||||
|
||||
//#
|
||||
//# Interface Signals
|
||||
//# =================
|
||||
//#
|
||||
|
||||
// Global inputs
|
||||
input ck_gclkcx_crypt;
|
||||
input cx_reset3;
|
||||
|
||||
// Control inputs
|
||||
//
|
||||
// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to
|
||||
// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q,
|
||||
// which allows the operands to be stored in flops. We also get inputs indicating which
|
||||
// instruction is to be computed.
|
||||
//
|
||||
// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that
|
||||
// we should begin the computation.
|
||||
//
|
||||
// There are 4 execution stages, E2-E5.
|
||||
input ival_e1_q;
|
||||
input sha1c_e1_q; // sha hash update (choose)
|
||||
input sha1p_e1_q; // sha hash update (parity)
|
||||
input sha1m_e1_q; // sha hash update (majority)
|
||||
input sha256h_e1_q; // sha256 hash update
|
||||
input sha256h2_e1_q; // sha256 hash update 2
|
||||
input sha256su1_e1_q; // sha256 schedule update 1
|
||||
input ival_e2_q;
|
||||
// Data inputs
|
||||
input [127:0] qn_e1_q; // qn arrives with first uop on {srcb,srca}
|
||||
input [127:0] qm_e1_q; // qm arrives with first uop on {srcd,srcc}
|
||||
input [127:0] qd_e2_q; // qd arrives with second uop on {srcb,srca}
|
||||
// Outputs
|
||||
output [127:0] crypt3_out_e6_q;
|
||||
output crypt3_active;
|
||||
|
||||
//#
|
||||
//# Internal Signals - Automatic Declarations
|
||||
//# =========================================
|
||||
//#
|
||||
wire [127: 0] crypt3_out_e5;
|
||||
reg [127: 0] crypt3_out_e6_q;
|
||||
wire firstop_recvd_e1;
|
||||
reg firstop_recvd_e2_q;
|
||||
reg ival_e3_q;
|
||||
reg ival_e4_q;
|
||||
reg ival_e5_q;
|
||||
wire [127: 0] newx_e2;
|
||||
wire [127: 0] newx_e3;
|
||||
wire [127: 0] newx_e4;
|
||||
wire [127: 0] newy_e2;
|
||||
wire [127: 0] newy_e3;
|
||||
wire [127: 0] newy_e4;
|
||||
reg [127: 0] qm_e2_q;
|
||||
reg [127: 0] qn_e2_q;
|
||||
wire [127: 0] sha1_xin_e2;
|
||||
wire [ 31: 0] sha1_yin_e2;
|
||||
wire [ 31: 0] sha1_zin_e2;
|
||||
wire sha1c_e2;
|
||||
reg sha1c_e2_q;
|
||||
reg sha1c_e3_q;
|
||||
reg sha1c_e4_q;
|
||||
reg sha1c_e5_q;
|
||||
wire sha1cpm_e2;
|
||||
wire sha1cpm_e3;
|
||||
wire sha1cpm_e4;
|
||||
wire sha1cpm_e5;
|
||||
wire [127: 0] sha1cpm_x_e2;
|
||||
wire [127: 0] sha1cpm_x_e3;
|
||||
wire [127: 0] sha1cpm_x_e4;
|
||||
wire [127: 0] sha1cpm_x_e5;
|
||||
wire [127: 0] sha1cpm_y_e2;
|
||||
wire [127: 0] sha1cpm_y_e3;
|
||||
wire [127: 0] sha1cpm_y_e4;
|
||||
// verilint unused_sigs off
|
||||
wire [ 31: 0] sha1cpm_y_e5;
|
||||
// verilint unused_sigs on
|
||||
wire sha1m_e2;
|
||||
reg sha1m_e2_q;
|
||||
reg sha1m_e3_q;
|
||||
reg sha1m_e4_q;
|
||||
reg sha1m_e5_q;
|
||||
wire sha1p_e2;
|
||||
reg sha1p_e2_q;
|
||||
reg sha1p_e3_q;
|
||||
reg sha1p_e4_q;
|
||||
reg sha1p_e5_q;
|
||||
wire [127: 0] sha256_xin_e2;
|
||||
wire [127: 0] sha256_yin_e2;
|
||||
wire [ 31: 0] sha256_zin_e2;
|
||||
wire sha256h2_e2;
|
||||
reg sha256h2_e2_q;
|
||||
reg sha256h2_e3_q;
|
||||
reg sha256h2_e4_q;
|
||||
reg sha256h2_e5_q;
|
||||
wire sha256h_e2;
|
||||
reg sha256h_e2_q;
|
||||
reg sha256h_e3_q;
|
||||
reg sha256h_e4_q;
|
||||
reg sha256h_e5_q;
|
||||
wire [127: 0] sha256h_x_e2;
|
||||
wire [127: 0] sha256h_x_e3;
|
||||
wire [127: 0] sha256h_x_e4;
|
||||
wire [127: 0] sha256h_x_e5;
|
||||
wire [127: 0] sha256h_y_e2;
|
||||
wire [127: 0] sha256h_y_e3;
|
||||
wire [127: 0] sha256h_y_e4;
|
||||
wire [127: 0] sha256h_y_e5;
|
||||
wire sha256hh2_e2;
|
||||
wire sha256hh2_e3;
|
||||
wire sha256hh2_e4;
|
||||
wire sha256su1_e2;
|
||||
reg sha256su1_e2_q;
|
||||
reg sha256su1_e3_q;
|
||||
reg sha256su1_e4_q;
|
||||
reg sha256su1_e5_q;
|
||||
wire [ 63: 0] sha256su1_x_e3;
|
||||
wire [ 63: 0] sha256su1_x_e4;
|
||||
wire [127: 0] x_e2;
|
||||
wire [127: 0] x_e3;
|
||||
reg [127: 0] x_e3_q;
|
||||
wire [127: 0] x_e4;
|
||||
reg [127: 0] x_e4_q;
|
||||
wire [127: 0] x_e5;
|
||||
reg [127: 0] x_e5_q;
|
||||
wire [127: 0] y_e2;
|
||||
wire [127: 0] y_e3;
|
||||
reg [127: 0] y_e3_q;
|
||||
wire [127: 0] y_e4;
|
||||
reg [127: 0] y_e4_q;
|
||||
wire [127: 0] y_e5;
|
||||
reg [127: 0] y_e5_q;
|
||||
wire [127: 0] z_e2;
|
||||
wire [ 95: 0] z_e3;
|
||||
reg [ 95: 0] z_e3_q;
|
||||
wire [ 63: 0] z_e4;
|
||||
reg [ 63: 0] z_e4_q;
|
||||
wire [ 31: 0] z_e5;
|
||||
reg [ 31: 0] z_e5_q;
|
||||
|
||||
//#
|
||||
//# Main Code
|
||||
//# =========
|
||||
//#
|
||||
//
|
||||
|
||||
// set when ival_e1_q first received, and held until the 2nd uop (ival_e2_q) is received
|
||||
assign firstop_recvd_e1 = (ival_e1_q | (firstop_recvd_e2_q & ~ival_e2_q));
|
||||
|
||||
// ival and instruction flops
|
||||
|
||||
// reset flop since 1st uop of crypto pair can be flushed due to SWDW nuke, thus might
|
||||
// have received ival_e2_q without ever receiving ival_e1_q (since it was flushed). thus
|
||||
// want firstop_recvd_e2_q to be 0 (not X) to stop X-prop
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
|
||||
begin: ufirstop_recvd_e2_q
|
||||
if (cx_reset3 == 1'b1)
|
||||
firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'b0}};
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if (cx_reset3==1'b0)
|
||||
firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1;
|
||||
else
|
||||
firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else
|
||||
firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1;
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// reset flop(s) since feeds into active signal used for RCG
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
|
||||
begin: uival_e3_q
|
||||
if (cx_reset3 == 1'b1)
|
||||
ival_e3_q <= `MAIA_DFF_DELAY {1{1'b0}};
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if (cx_reset3==1'b0)
|
||||
ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q;
|
||||
else
|
||||
ival_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else
|
||||
ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q;
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
|
||||
begin: uival_e4_q
|
||||
if (cx_reset3 == 1'b1)
|
||||
ival_e4_q <= `MAIA_DFF_DELAY {1{1'b0}};
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if (cx_reset3==1'b0)
|
||||
ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q;
|
||||
else
|
||||
ival_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else
|
||||
ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q;
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
|
||||
begin: uival_e5_q
|
||||
if (cx_reset3 == 1'b1)
|
||||
ival_e5_q <= `MAIA_DFF_DELAY {1{1'b0}};
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if (cx_reset3==1'b0)
|
||||
ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q;
|
||||
else
|
||||
ival_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
`else
|
||||
else
|
||||
ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q;
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uinst_e2
|
||||
if (ival_e1_q==1'b1) begin
|
||||
sha1c_e2_q <= `MAIA_DFF_DELAY sha1c_e1_q;
|
||||
sha1p_e2_q <= `MAIA_DFF_DELAY sha1p_e1_q;
|
||||
sha1m_e2_q <= `MAIA_DFF_DELAY sha1m_e1_q;
|
||||
sha256h_e2_q <= `MAIA_DFF_DELAY sha256h_e1_q;
|
||||
sha256h2_e2_q <= `MAIA_DFF_DELAY sha256h2_e1_q;
|
||||
sha256su1_e2_q <= `MAIA_DFF_DELAY sha256su1_e1_q;
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e1_q==1'b0));
|
||||
else begin
|
||||
sha1c_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1p_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1m_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// stop X-prop if 1st uop was nuked due to swdw_nuke and 2nd was issued
|
||||
|
||||
assign sha1c_e2 = firstop_recvd_e2_q & sha1c_e2_q;
|
||||
assign sha1p_e2 = firstop_recvd_e2_q & sha1p_e2_q;
|
||||
assign sha1m_e2 = firstop_recvd_e2_q & sha1m_e2_q;
|
||||
assign sha256h_e2 = firstop_recvd_e2_q & sha256h_e2_q;
|
||||
assign sha256h2_e2 = firstop_recvd_e2_q & sha256h2_e2_q;
|
||||
assign sha256su1_e2 = firstop_recvd_e2_q & sha256su1_e2_q;
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uinst_e3
|
||||
if (ival_e2_q==1'b1) begin
|
||||
sha1c_e3_q <= `MAIA_DFF_DELAY sha1c_e2;
|
||||
sha1p_e3_q <= `MAIA_DFF_DELAY sha1p_e2;
|
||||
sha1m_e3_q <= `MAIA_DFF_DELAY sha1m_e2;
|
||||
sha256h_e3_q <= `MAIA_DFF_DELAY sha256h_e2;
|
||||
sha256h2_e3_q <= `MAIA_DFF_DELAY sha256h2_e2;
|
||||
sha256su1_e3_q <= `MAIA_DFF_DELAY sha256su1_e2;
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e2_q==1'b0));
|
||||
else begin
|
||||
sha1c_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1p_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1m_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uinst_e4
|
||||
if (ival_e3_q==1'b1) begin
|
||||
sha1c_e4_q <= `MAIA_DFF_DELAY sha1c_e3_q;
|
||||
sha1p_e4_q <= `MAIA_DFF_DELAY sha1p_e3_q;
|
||||
sha1m_e4_q <= `MAIA_DFF_DELAY sha1m_e3_q;
|
||||
sha256h_e4_q <= `MAIA_DFF_DELAY sha256h_e3_q;
|
||||
sha256h2_e4_q <= `MAIA_DFF_DELAY sha256h2_e3_q;
|
||||
sha256su1_e4_q <= `MAIA_DFF_DELAY sha256su1_e3_q;
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e3_q==1'b0));
|
||||
else begin
|
||||
sha1c_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1p_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1m_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uinst_e5
|
||||
if (ival_e4_q==1'b1) begin
|
||||
sha1c_e5_q <= `MAIA_DFF_DELAY sha1c_e4_q;
|
||||
sha1p_e5_q <= `MAIA_DFF_DELAY sha1p_e4_q;
|
||||
sha1m_e5_q <= `MAIA_DFF_DELAY sha1m_e4_q;
|
||||
sha256h_e5_q <= `MAIA_DFF_DELAY sha256h_e4_q;
|
||||
sha256h2_e5_q <= `MAIA_DFF_DELAY sha256h2_e4_q;
|
||||
sha256su1_e5_q <= `MAIA_DFF_DELAY sha256su1_e4_q;
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e4_q==1'b0));
|
||||
else begin
|
||||
sha1c_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1p_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha1m_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256h2_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
sha256su1_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// E1
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uops_e2
|
||||
if (ival_e1_q==1'b1) begin
|
||||
qm_e2_q[127:0] <= `MAIA_DFF_DELAY qm_e1_q[127:0];
|
||||
qn_e2_q[127:0] <= `MAIA_DFF_DELAY qn_e1_q[127:0];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e1_q==1'b0));
|
||||
else begin
|
||||
qm_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
qn_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// E2
|
||||
assign x_e2[127:0] = qd_e2_q[127:0];
|
||||
assign y_e2[127:0] = qn_e2_q[127:0];
|
||||
assign z_e2[127:0] = qm_e2_q[127:0];
|
||||
|
||||
assign sha1_xin_e2[127:0] = {128{sha1cpm_e2}} & x_e2[127:0];
|
||||
assign sha1_yin_e2[ 31:0] = { 32{sha1cpm_e2}} & y_e2[ 31:0];
|
||||
assign sha1_zin_e2[ 31:0] = { 32{sha1cpm_e2}} & z_e2[ 31:0];
|
||||
|
||||
// sha1 hash update
|
||||
maia_cx_sha1cpm usha1cpm_e2(
|
||||
.choose (sha1c_e2_q),
|
||||
.parity (sha1p_e2_q),
|
||||
.majority (sha1m_e2_q),
|
||||
.x (sha1_xin_e2[127:0]),
|
||||
.y (sha1_yin_e2[31:0]),
|
||||
.z (sha1_zin_e2[31:0]),
|
||||
.newx (sha1cpm_x_e2[127:0]),
|
||||
.newy (sha1cpm_y_e2[31:0])
|
||||
);
|
||||
assign sha1cpm_y_e2[127:32] = {96{sha1cpm_e2}} & y_e2[127:32];
|
||||
|
||||
assign sha256_xin_e2[127:0] = {128{sha256hh2_e2}} & x_e2[127:0];
|
||||
assign sha256_yin_e2[127:0] = {128{sha256hh2_e2}} & y_e2[127:0];
|
||||
assign sha256_zin_e2[ 31:0] = { 32{sha256hh2_e2}} & z_e2[ 31:0];
|
||||
|
||||
// sha256 hash update (1 and 2)
|
||||
maia_cx_sha256h32 usha256h32_e2(
|
||||
.x (sha256_xin_e2[127:0]),
|
||||
.y (sha256_yin_e2[127:0]),
|
||||
.z (sha256_zin_e2[31:0]),
|
||||
.newx (sha256h_x_e2[127:0]),
|
||||
.newy (sha256h_y_e2[127:0])
|
||||
);
|
||||
|
||||
// mux results
|
||||
assign sha1cpm_e2 = sha1c_e2 | sha1p_e2 | sha1m_e2;
|
||||
assign sha256hh2_e2 = sha256h_e2 | sha256h2_e2;
|
||||
assign newx_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_x_e2[127:0])
|
||||
| ({128{sha256hh2_e2}} & sha256h_x_e2[127:0])
|
||||
| ({128{sha256su1_e2}} & x_e2[127:0]);
|
||||
assign newy_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_y_e2[127:0])
|
||||
| ({128{sha256hh2_e2}} & sha256h_y_e2[127:0])
|
||||
| ({128{sha256su1_e2}} & {z_e2[31:0], y_e2[127:32]});
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uops_e3
|
||||
if (ival_e2_q==1'b1) begin
|
||||
x_e3_q[127:0] <= `MAIA_DFF_DELAY newx_e2[127:0];
|
||||
y_e3_q[127:0] <= `MAIA_DFF_DELAY newy_e2[127:0];
|
||||
z_e3_q[95:0] <= `MAIA_DFF_DELAY z_e2[127:32];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e2_q==1'b0));
|
||||
else begin
|
||||
x_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
y_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
z_e3_q[95:0] <= `MAIA_DFF_DELAY {96{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// E3
|
||||
assign x_e3[127:0] = x_e3_q[127:0];
|
||||
assign y_e3[127:0] = y_e3_q[127:0];
|
||||
assign z_e3[95:0] = z_e3_q[95:0];
|
||||
|
||||
// sha1 hash update
|
||||
maia_cx_sha1cpm usha1cpm_e3(
|
||||
.choose (sha1c_e3_q),
|
||||
.parity (sha1p_e3_q),
|
||||
.majority (sha1m_e3_q),
|
||||
.x (x_e3[127:0]),
|
||||
.y (y_e3[31:0]),
|
||||
.z (z_e3[31:0]),
|
||||
.newx (sha1cpm_x_e3[127:0]),
|
||||
.newy (sha1cpm_y_e3[31:0])
|
||||
);
|
||||
assign sha1cpm_y_e3[127:32] = y_e3[127:32];
|
||||
|
||||
// sha256 hash update (1 and 2)
|
||||
maia_cx_sha256h32 usha256h32_e3(
|
||||
.x (x_e3[127:0]),
|
||||
.y (y_e3[127:0]),
|
||||
.z (z_e3[31:0]),
|
||||
.newx (sha256h_x_e3[127:0]),
|
||||
.newy (sha256h_y_e3[127:0])
|
||||
);
|
||||
|
||||
// sha256 schedule update 1, cycle 1
|
||||
maia_cx_sha256su1 usha256su1_e3(
|
||||
.sha256su1_op (sha256su1_e3_q),
|
||||
.x (x_e3[63:0]), // qd[63:0]
|
||||
.y (y_e3[63:0]), // qn[95:32]
|
||||
.z (z_e3[95:32]), // qm[127:64]
|
||||
.newx (sha256su1_x_e3[63:0])
|
||||
);
|
||||
|
||||
// mux results
|
||||
assign sha1cpm_e3 = sha1c_e3_q | sha1p_e3_q | sha1m_e3_q;
|
||||
assign sha256hh2_e3 = sha256h_e3_q | sha256h2_e3_q;
|
||||
assign newx_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_x_e3[127:0])
|
||||
| ({128{sha256hh2_e3 }} & sha256h_x_e3[127:0])
|
||||
| ({128{sha256su1_e3_q}} & {x_e3[127:64], sha256su1_x_e3[63:0]});
|
||||
assign newy_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_y_e3[127:0])
|
||||
| ({128{sha256hh2_e3 }} & sha256h_y_e3[127:0])
|
||||
| ({128{sha256su1_e3_q}} & {y_e3[127:0]});
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uops_e4
|
||||
if (ival_e3_q==1'b1) begin
|
||||
x_e4_q[127:0] <= `MAIA_DFF_DELAY newx_e3[127:0];
|
||||
y_e4_q[127:0] <= `MAIA_DFF_DELAY newy_e3[127:0];
|
||||
z_e4_q[63:0] <= `MAIA_DFF_DELAY z_e3[95:32];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e3_q==1'b0));
|
||||
else begin
|
||||
x_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
y_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
z_e4_q[63:0] <= `MAIA_DFF_DELAY {64{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// E4
|
||||
assign x_e4[127:0] = x_e4_q[127:0];
|
||||
assign y_e4[127:0] = y_e4_q[127:0];
|
||||
assign z_e4[63:0] = z_e4_q[63:0];
|
||||
|
||||
// sha1 hash update
|
||||
maia_cx_sha1cpm usha1cpm_e4(
|
||||
.choose (sha1c_e4_q),
|
||||
.parity (sha1p_e4_q),
|
||||
.majority (sha1m_e4_q),
|
||||
.x (x_e4[127:0]),
|
||||
.y (y_e4[31:0]),
|
||||
.z (z_e4[31:0]),
|
||||
.newx (sha1cpm_x_e4[127:0]),
|
||||
.newy (sha1cpm_y_e4[31:0])
|
||||
);
|
||||
assign sha1cpm_y_e4[127:32] = y_e4[127:32];
|
||||
|
||||
// sha256 hash update (1 and 2)
|
||||
maia_cx_sha256h32 usha256h32_e4(
|
||||
.x (x_e4[127:0]),
|
||||
.y (y_e4[127:0]),
|
||||
.z (z_e4[31:0]),
|
||||
.newx (sha256h_x_e4[127:0]),
|
||||
.newy (sha256h_y_e4[127:0])
|
||||
);
|
||||
|
||||
// sha256 schedule update 1, cycle 2
|
||||
maia_cx_sha256su1 usha256su1_e4(
|
||||
.sha256su1_op (sha256su1_e4_q),
|
||||
.x (x_e4[127:64]), // qd[127:64]
|
||||
.y (y_e4[127:64]), // {qm[31:0], qn[127:96]}
|
||||
.z (x_e4[63:0]), // sha256su1_x_e3[63:0]
|
||||
.newx (sha256su1_x_e4[63:0])
|
||||
);
|
||||
|
||||
// mux results
|
||||
assign sha1cpm_e4 = sha1c_e4_q | sha1p_e4_q | sha1m_e4_q;
|
||||
assign sha256hh2_e4 = sha256h_e4_q | sha256h2_e4_q;
|
||||
assign newx_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_x_e4[127:0])
|
||||
| ({128{sha256hh2_e4 }} & sha256h_x_e4[127:0])
|
||||
| ({128{sha256su1_e4_q}} & {sha256su1_x_e4[63:0], x_e4[63:0]});
|
||||
assign newy_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_y_e4[127:0])
|
||||
| ({128{sha256hh2_e4 }} & sha256h_y_e4[127:0]);
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: uops_e5
|
||||
if (ival_e4_q==1'b1) begin
|
||||
x_e5_q[127:0] <= `MAIA_DFF_DELAY newx_e4[127:0];
|
||||
y_e5_q[127:0] <= `MAIA_DFF_DELAY newy_e4[127:0];
|
||||
z_e5_q[31:0] <= `MAIA_DFF_DELAY z_e4[63:32];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e4_q==1'b0));
|
||||
else begin
|
||||
x_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
y_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
z_e5_q[31:0] <= `MAIA_DFF_DELAY {32{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
// E5
|
||||
assign x_e5[127:0] = x_e5_q[127:0];
|
||||
assign y_e5[127:0] = y_e5_q[127:0];
|
||||
assign z_e5[31:0] = z_e5_q[31:0];
|
||||
|
||||
// sha1 hash update
|
||||
maia_cx_sha1cpm usha1cpm_e5(
|
||||
.choose (sha1c_e5_q),
|
||||
.parity (sha1p_e5_q),
|
||||
.majority (sha1m_e5_q),
|
||||
.x (x_e5[127:0]),
|
||||
.y (y_e5[31:0]),
|
||||
.z (z_e5[31:0]),
|
||||
.newx (sha1cpm_x_e5[127:0]),
|
||||
.newy (sha1cpm_y_e5[31:0])
|
||||
);
|
||||
|
||||
// sha256 hash update (1 and 2)
|
||||
maia_cx_sha256h32 usha256h32_e5(
|
||||
.x (x_e5[127:0]),
|
||||
.y (y_e5[127:0]),
|
||||
.z (z_e5[31:0]),
|
||||
.newx (sha256h_x_e5[127:0]),
|
||||
.newy (sha256h_y_e5[127:0])
|
||||
);
|
||||
|
||||
// mux results
|
||||
assign sha1cpm_e5 = sha1c_e5_q | sha1p_e5_q | sha1m_e5_q;
|
||||
assign crypt3_out_e5[127:0] = ({128{sha1cpm_e5}} & sha1cpm_x_e5[127:0])
|
||||
| ({128{sha256h_e5_q}} & sha256h_x_e5[127:0])
|
||||
| ({128{sha256h2_e5_q}} & sha256h_y_e5[127:0])
|
||||
| ({128{sha256su1_e5_q}} & x_e5[127:0]);
|
||||
|
||||
// Macro DFF called
|
||||
// verilint flop_checks off
|
||||
always @(posedge ck_gclkcx_crypt)
|
||||
begin: ures_e6
|
||||
if (ival_e5_q==1'b1) begin
|
||||
crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY crypt3_out_e5[127:0];
|
||||
end
|
||||
`ifdef MAIA_XPROP_FLOP
|
||||
else if ((ival_e5_q==1'b0));
|
||||
else begin
|
||||
crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
|
||||
end
|
||||
`endif
|
||||
end
|
||||
// verilint flop_checks on
|
||||
// end of Macro DFF
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// regional clock gating (RCG) terms
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
assign crypt3_active = (ival_e1_q |
|
||||
ival_e2_q |
|
||||
ival_e3_q |
|
||||
ival_e4_q |
|
||||
ival_e5_q
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
//ARMAUTO UNDEF START
|
||||
`define MAIA_UNDEFINE
|
||||
`include "maia_header.v"
|
||||
`undef MAIA_UNDEFINE
|
||||
//ARMAUTO UNDEF END
|
||||
@ -1,67 +0,0 @@
|
||||
#-----------------------------------------------------------------------------
|
||||
# The confidential and proprietary information contained in this file may
|
||||
# only be used by a person authorised under and to the extent permitted
|
||||
# by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
#
|
||||
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
|
||||
# ALL RIGHTS RESERVED
|
||||
#
|
||||
# This entire notice must be reproduced on all copies of this file
|
||||
# and copies of this file may only be made by a person if such person is
|
||||
# permitted to do so under the terms of a subsisting license agreement
|
||||
# from ARM Limited or its affiliates.
|
||||
#
|
||||
# Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
#
|
||||
#-----------------------------------------------------------------------------
|
||||
# Makefile include file for AArch32 crypto. This must be included from the
|
||||
# top-level Makefile; it is not a standalone Makefile.
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# Note these variables must only be used in places where Make reads their
|
||||
# immediate values rather than their deferred values. This is because all
|
||||
# the include files use the same variables and the deferred evaluation will
|
||||
# yeild the last values set by the last include file. They can be used in the
|
||||
# target and prerequisite sections of rule definitions, which are evaluated
|
||||
# immediately, but not in the recipe, where evaluation is deferred.
|
||||
srcdir := aarch32/crypto
|
||||
common_srcdir := common/crypto
|
||||
libdir := common/shared
|
||||
dstdir := aarch32/crypto
|
||||
target := $(dstdir)/crypto.elf
|
||||
csrcs := $(wildcard $(common_srcdir)/*.c)
|
||||
asmsrcs := $(wildcard $(srcdir)/*.s)
|
||||
libsrcs := $(wildcard $(libdir)/*.c)
|
||||
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
|
||||
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
|
||||
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
|
||||
|
||||
# Find common C files (the source files are not in the build target directory)
|
||||
vpath %.c $(common_srcdir) $(libdir)
|
||||
|
||||
# Change the CPU target to include crypto for all files that need compiling
|
||||
$(asmobjs): ARCH = armv8-a+crypto
|
||||
|
||||
$(asmobjs): %.o: %.s
|
||||
@echo " [ASM ] $<"
|
||||
@$(ASM32) $(ASM_OPTS_AARCH32) $< -o $@
|
||||
|
||||
$(cobjs): $(dstdir)/%.o: %.c
|
||||
@echo " [CC $(CC32) ] $<"
|
||||
ifeq ($(strip $(GCC)), yes)
|
||||
@$(CC32) $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -mword-relocations -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
|
||||
else
|
||||
@$(CC32) -mfpu=none $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
|
||||
endif
|
||||
|
||||
# Link. For C-based tests this is done through GCC to make sure that all
|
||||
# standard libraries are set up correctly.
|
||||
$(target): $(asmobjs) $(cobjs) $(aarch32_bootobj) $(aarch32_c_bootobj)
|
||||
@echo " [LINK] $<"
|
||||
ifeq ($(strip $(GCC)), yes)
|
||||
@$(CC32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
|
||||
else
|
||||
@$(LD32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
|
||||
endif
|
||||
|
||||
# ex: syntax=make:
|
||||
Binary file not shown.
Binary file not shown.
@ -1,212 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
// This file defines assembler functions that are called from C in the main
|
||||
// crypto test
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.section testcode, "ax", %progbits
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Macros
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.macro aes128_key_expand_step rcon
|
||||
VTBL.8 d26, {d22, d23}, d28
|
||||
VTBL.8 d27, {d22, d23}, d29
|
||||
AESE.8 q13, q12
|
||||
VMOV.I32 q15, #\rcon
|
||||
VEOR q13, q13, q15
|
||||
VEXT.8 q15, q12, q11, #12
|
||||
VEOR q11, q11, q15
|
||||
VEXT.8 q15, q12, q15, #12
|
||||
VEOR q11, q11, q15
|
||||
VEXT.8 q15, q12, q15, #12
|
||||
VEOR q11, q11, q15
|
||||
VEOR q11, q11, q13
|
||||
.endm
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Function: aes128_key_expand
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.global aes128_key_expand
|
||||
.type aes128_key_expand, %function
|
||||
|
||||
aes128_key_expand:
|
||||
// C arguments:
|
||||
// r0: const unsigned char *key_in
|
||||
// r1: unsigned char *key_out
|
||||
// Return: void
|
||||
VLD1.8 {d22-d23}, [r0]
|
||||
MOV r2, #0
|
||||
VDUP.8 q12, r2
|
||||
LDR r2, =0x0c0f0e0d
|
||||
VDUP.32 q14, r2
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x01
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x02
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x04
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x08
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x10
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x20
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x40
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x80
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x1B
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
aes128_key_expand_step 0x36
|
||||
VST1.8 {d22}, [r1]
|
||||
ADD r1, r1, #8
|
||||
VST1.8 {d23}, [r1]
|
||||
ADD r1, r1, #8
|
||||
|
||||
BX lr
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Function: aes128_ecb_encrypt
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.global aes128_ecb_encrypt
|
||||
.type aes128_ecb_encrypt, %function
|
||||
|
||||
aes128_ecb_encrypt:
|
||||
// C arguments:
|
||||
// r0: const unsigned char *key
|
||||
// r1: const unsigned char *in_data
|
||||
// r2: unsigned char *out_data
|
||||
// r3: unsigned int size
|
||||
// Return: void
|
||||
VLD1.8 {d10-d13}, [r0]
|
||||
ADD r0, r0, #32
|
||||
VLD1.8 {d14-d17}, [r0]
|
||||
ADD r0, r0, #32
|
||||
VLD1.8 {d18-d21}, [r0]
|
||||
ADD r0, r0, #32
|
||||
VLD1.8 {d22-d25}, [r0]
|
||||
ADD r0, r0, #32
|
||||
VLD1.8 {d26-d29}, [r0]
|
||||
ADD r0, r0, #32
|
||||
VLD1.8 {d30-d31}, [r0]
|
||||
|
||||
aes128_ecb_enc_loop:
|
||||
// Load data
|
||||
VLD1.8 {d0-d3}, [r1]
|
||||
ADD r1, r1, #32
|
||||
// Round 1
|
||||
AESE.8 q0, q5
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q5
|
||||
AESMC.8 q1, q1
|
||||
// Round 2
|
||||
AESE.8 q0, q6
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q6
|
||||
AESMC.8 q1, q1
|
||||
// Round 3
|
||||
AESE.8 q0, q7
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q7
|
||||
AESMC.8 q1, q1
|
||||
// Round 4
|
||||
AESE.8 q0, q8
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q8
|
||||
AESMC.8 q1, q1
|
||||
// Round 5
|
||||
AESE.8 q0, q9
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q9
|
||||
AESMC.8 q1, q1
|
||||
// Round 6
|
||||
AESE.8 q0, q10
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q10
|
||||
AESMC.8 q1, q1
|
||||
// Round 7
|
||||
AESE.8 q0, q11
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q11
|
||||
AESMC.8 q1, q1
|
||||
// Round 8
|
||||
AESE.8 q0, q12
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q12
|
||||
AESMC.8 q1, q1
|
||||
// Round 9
|
||||
AESE.8 q0, q13
|
||||
AESMC.8 q0, q0
|
||||
AESE.8 q1, q13
|
||||
AESMC.8 q1, q1
|
||||
|
||||
// Round 10
|
||||
AESE.8 q0, q14
|
||||
PLD [r1, #64]
|
||||
AESE.8 q1, q14
|
||||
VEOR q0, q0, q15
|
||||
SUBS r3, r3, #16
|
||||
VST1.8 {d0-d1}, [r2]
|
||||
ADD r2, r2, #16
|
||||
BEQ aes128_ecb_enc_exit
|
||||
|
||||
VEOR q1, q1, q15
|
||||
SUBS r3, r3, #16
|
||||
VST1.8 {d2-d3}, [r2]
|
||||
ADD r2, r2, #16
|
||||
BGT aes128_ecb_enc_loop
|
||||
|
||||
aes128_ecb_enc_exit:
|
||||
BX lr
|
||||
|
||||
@ -1,63 +0,0 @@
|
||||
#-------------------------------------------------------------------------------
|
||||
# The confidential and proprietary information contained in this file may
|
||||
# only be used by a person authorised under and to the extent permitted
|
||||
# by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
#
|
||||
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
|
||||
# ALL RIGHTS RESERVED
|
||||
#
|
||||
# This entire notice must be reproduced on all copies of this file
|
||||
# and copies of this file may only be made by a person if such person is
|
||||
# permitted to do so under the terms of a subsisting license agreement
|
||||
# from ARM Limited or its affiliates.
|
||||
#
|
||||
# Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
#
|
||||
#-------------------------------------------------------------------------------
|
||||
# Makefile include file for AArch64 crypto. This must be included from the
|
||||
# top-level Makefile; it is not a standalone Makefile.
|
||||
#-------------------------------------------------------------------------------
|
||||
|
||||
# Note these variables must only be used in places where Make reads their
|
||||
# immediate values rather than their deferred values. This is because all
|
||||
# the include files use the same variables and the deferred evaluation will
|
||||
# yield the last values set by the last include file. They can be used in the
|
||||
# target and prerequisite sections of rule definitions, which are evaluated
|
||||
# immediately, but not in the recipe, where evaluation is deferred.
|
||||
srcdir := aarch64/crypto
|
||||
common_srcdir := common/crypto
|
||||
libdir := common/shared
|
||||
dstdir := aarch64/crypto
|
||||
target := $(dstdir)/crypto.elf
|
||||
asmsrcs := $(wildcard $(srcdir)/*.s)
|
||||
csrcs := $(wildcard $(common_srcdir)/*.c)
|
||||
libsrcs := $(wildcard $(libdir)/*.c)
|
||||
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
|
||||
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
|
||||
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
|
||||
|
||||
# Find common C files (the source files are not in the build target directory)
|
||||
vpath %.c $(common_srcdir) $(libdir)
|
||||
|
||||
# Change the CPU target to include crypto for all files that need compiling
|
||||
$(cobjs) $(asmobjs): ARCH = armv8-a+crypto
|
||||
|
||||
$(asmobjs): %.o: %.s
|
||||
@echo " [ASM ] $<"
|
||||
@$(ASM64) $(ASM_OPTS_AARCH64) $< -o $@
|
||||
|
||||
$(cobjs): $(dstdir)/%.o: %.c
|
||||
@echo " [CC ] $<"
|
||||
@$(CC64) $(CC_OPTS_AARCH64) -I$(common_shared) $< -o $@
|
||||
|
||||
# Link. For C-based tests this is done through GCC to make sure that all
|
||||
# standard libraries are set up correctly.
|
||||
$(target): $(asmobjs) $(cobjs) $(aarch64_bootobj)
|
||||
@echo " [LINK] $<"
|
||||
ifeq ($(strip $(GCC)), yes)
|
||||
@$(CC64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
|
||||
else
|
||||
@$(LD64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
|
||||
endif
|
||||
|
||||
# ex: syntax=make:
|
||||
Binary file not shown.
@ -1,166 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
// This file defines assembler functions that are called from C in the main
|
||||
// crypto test
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.section .text, "ax", %progbits
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Macros
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.macro aes128_key_expand_step rcon
|
||||
TBL v18.16B, {v16.16B}, v19.16B
|
||||
AESE v18.16B, v17.16B
|
||||
MOVI v20.4S, #\rcon
|
||||
EOR v18.16B, v18.16B, v20.16B
|
||||
EXT v20.16B, v17.16B, v16.16B, #12
|
||||
EOR v16.16B, v16.16B, v20.16B
|
||||
EXT v20.16B, v17.16B, v20.16B, #12
|
||||
EOR v16.16B, v16.16B, v20.16B
|
||||
EXT v20.16B, v17.16B, v20.16B, #12
|
||||
EOR v16.16B, v16.16B, v20.16B
|
||||
EOR v16.16B, v16.16B, v18.16B
|
||||
.endm
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Function: aes128_key_expand
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.global aes128_key_expand
|
||||
.type aes128_key_expand, %function
|
||||
|
||||
aes128_key_expand:
|
||||
// C arguments:
|
||||
// r0: const unsigned char *key_in
|
||||
// r1: unsigned char *key_out
|
||||
// Return: void
|
||||
LD1 {v16.16B}, [x0]
|
||||
MOVZ w2, #0x0e0d
|
||||
DUP v17.16B, wzr
|
||||
movk w2, #0xc0f, lsl #16
|
||||
DUP v19.4S, w2
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x01
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x02
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x04
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x08
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x10
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x20
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x40
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x80
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x1B
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
aes128_key_expand_step 0x36
|
||||
ST1 {v16.16B}, [x1]
|
||||
RET
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Function: aes128_ecb_encrypt
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
.global aes128_ecb_encrypt
|
||||
.type aes128_ecb_encrypt, %function
|
||||
|
||||
aes128_ecb_encrypt:
|
||||
// C arguments:
|
||||
// r0: const unsigned char *key
|
||||
// r1: const unsigned char *in_data
|
||||
// r2: unsigned char *out_data
|
||||
// r3: unsigned int size
|
||||
// Return: void
|
||||
LD1 {v16.16B-v19.16B}, [x0], #64
|
||||
LD1 {v20.16B-v23.16B}, [x0], #64
|
||||
LD1 {v24.16B-v26.16B}, [x0]
|
||||
|
||||
aes128_ecb_enc_loop:
|
||||
// Load data
|
||||
LD1 {v0.16B-v1.16B}, [x1], #32
|
||||
// Round 1
|
||||
AESE v0.16B, v16.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v16.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 2
|
||||
AESE v0.16B, v17.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v17.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 3
|
||||
AESE v0.16B, v18.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v18.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 4
|
||||
AESE v0.16B, v19.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v19.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 5
|
||||
AESE v0.16B, v20.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v20.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 6
|
||||
AESE v0.16B, v21.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v21.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 7
|
||||
AESE v0.16B, v22.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v22.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 8
|
||||
AESE v0.16B, v23.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v23.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 9
|
||||
AESE v0.16B, v24.16B
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, v24.16B
|
||||
AESMC v1.16B, v1.16B
|
||||
// Round 10
|
||||
AESE v0.16B, v25.16B
|
||||
PRFM PLDL1KEEP, [x1, #64]
|
||||
AESE v1.16B, v25.16B
|
||||
EOR v0.16B, v0.16B, v26.16B
|
||||
SUBS x3, x3, #16
|
||||
ST1 {v0.16B}, [x2], #16
|
||||
B.EQ aes128_ecb_enc_exit
|
||||
|
||||
EOR v1.16B, v1.16B, v26.16B
|
||||
SUBS x3, x3, #16
|
||||
ST1 {v1.16B}, [x2], #16
|
||||
B.GT aes128_ecb_enc_loop
|
||||
|
||||
aes128_ecb_enc_exit:
|
||||
RET
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,72 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited or its affiliates.
|
||||
//
|
||||
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited or its affiliates.
|
||||
//
|
||||
// Release Information : HERCULESAE-MP106-r0p1-00eac0
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "benchmark.h"
|
||||
|
||||
static const uint8_t key[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
|
||||
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff};
|
||||
|
||||
extern const uint8_t aes128_ecb_encrypt_input[][4096];
|
||||
extern const uint8_t aes128_ecb_encrypt_ref_output[][4096];
|
||||
extern uint8_t aes128_ecb_encrypt_output[][4096];
|
||||
|
||||
// Function prototypes for asm functions
|
||||
extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out);
|
||||
extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size);
|
||||
|
||||
extern uint32_t have_crypto;
|
||||
|
||||
int main()
|
||||
{
|
||||
int bs;
|
||||
int i;
|
||||
int fail = 0;
|
||||
|
||||
uint8_t kv[176];
|
||||
|
||||
started();
|
||||
|
||||
if ( !have_crypto ) {
|
||||
printf("Cryptographic extension not available on this PE.\n");
|
||||
exit(144); // something gross
|
||||
}
|
||||
|
||||
aes128_key_expand(key, kv);
|
||||
|
||||
for (i = 0, bs = 16; bs <= 4096; i++, bs*=2) {
|
||||
uint32_t cmpres;
|
||||
|
||||
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
|
||||
|
||||
cmpres = (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
|
||||
|
||||
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
|
||||
|
||||
cmpres |= (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
|
||||
|
||||
if (cmpres != 0)
|
||||
fail = 1;
|
||||
}
|
||||
|
||||
return fail;
|
||||
}
|
||||
|
||||
@ -1,41 +0,0 @@
|
||||
###############################################################################
|
||||
# The confidential and proprietary information contained in this file may
|
||||
# only be used by a person authorised under and to the extent permitted
|
||||
# by a subsisting licensing agreement from ARM Limited.
|
||||
#
|
||||
# (C) COPYRIGHT 2011-2013 ARM Limited.
|
||||
# ALL RIGHTS RESERVED
|
||||
#
|
||||
# This entire notice must be reproduced on all copies of this file
|
||||
# and copies of this file may only be made by a person if such person is
|
||||
# permitted to do so under the terms of a subsisting license agreement
|
||||
# from ARM Limited.
|
||||
#
|
||||
###############################################################################
|
||||
# Makefile.inc for crypto64
|
||||
# setup source paths (crypto64)
|
||||
|
||||
crypto64_base = crypto64
|
||||
crypto64_src = $(crypto64_base)/src
|
||||
crypto64_obj = $(crypto64_base)/obj
|
||||
crypto64_elf = $(crypto64_base)/elf
|
||||
|
||||
#rules for crypto64
|
||||
|
||||
crypto64_asm_obj = $(incl_obj)/benchmark_boot_a64.o $(incl_obj)/vectors.o $(incl_obj)/num_cpus_a64.o $(crypto64_obj)/cryptolib_asm64.o
|
||||
crypto64_c_obj = $(incl_obj)/sys_a64.o $(incl_obj)/stackheap_a64.o $(crypto64_obj)/cryptodata.o $(crypto64_obj)/crypto_test.o
|
||||
|
||||
crypto64: clean_crypto64 $(crypto64_elf)/crypto64.elf
|
||||
|
||||
$(crypto64_obj)/%.o: $(crypto64_src)/%.c
|
||||
$(CC_A64) $(CC_A64_OPTS) $< -o $@
|
||||
|
||||
$(crypto64_obj)/%.o: $(crypto64_src)/%.s
|
||||
$(AS_A64) $(AS_A64_OPTS) $< -o $@
|
||||
|
||||
$(crypto64_elf)/crypto64.elf: $(crypto64_asm_obj) $(crypto64_c_obj)
|
||||
$(LINK_A64) $(LINK_A64_OPTS) $(crypto64_asm_obj) $(crypto64_c_obj) -o $@
|
||||
|
||||
clean_crypto64:
|
||||
\rm -f $(crypto64_asm_obj) $(crypto64_c_obj) $(crypto64_elf)/crypto64.elf
|
||||
|
||||
Binary file not shown.
@ -1,80 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited.
|
||||
//
|
||||
// (C) COPYRIGHT 2012-2013 ARM Limited.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited.
|
||||
//
|
||||
// SVN Information
|
||||
//
|
||||
// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
|
||||
//
|
||||
// Revision : $Revision: 241584 $
|
||||
//
|
||||
// Release Information :
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "cryptolib.h"
|
||||
#include "cryptodata.h"
|
||||
#include "benchmark.h"
|
||||
|
||||
#ifndef BLOCK_SIZE
|
||||
#define BLOCK_SIZE 1024
|
||||
#endif
|
||||
|
||||
#ifndef ITERATIONS
|
||||
#define ITERATIONS 10
|
||||
#endif
|
||||
|
||||
uint8_t get_aes_index( int block_size)
|
||||
{
|
||||
uint8_t index = 0;
|
||||
uint8_t i;
|
||||
for (i=4; i<13; i++)
|
||||
{
|
||||
if ((block_size >> i) & 0x1)
|
||||
{
|
||||
index = i-4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return index;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
uint32_t block_size;
|
||||
uint8_t index;
|
||||
uint32_t cmpres = 0;
|
||||
uint8_t i;
|
||||
|
||||
block_size = BLOCK_SIZE;
|
||||
|
||||
uint8_t kv[176];
|
||||
printf("AES128-ECB encryption\n");
|
||||
index = get_aes_index(block_size);
|
||||
BENCHSTART
|
||||
for ( i = 0; i < ITERATIONS; i++)
|
||||
{
|
||||
aes128_key_expand(aes128_ecb_encrypt_key[index], kv);
|
||||
LOOPSTART
|
||||
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[index], aes128_ecb_encrypt_output[index], block_size);
|
||||
LOOPEND
|
||||
}
|
||||
cmpres |= memcmp(aes128_ecb_encrypt_output[index], aes128_ecb_encrypt_ref_output[index], block_size);
|
||||
if (cmpres)
|
||||
printf("AES128-ECB encryption failed\n");
|
||||
BENCHFINISHED
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +0,0 @@
|
||||
extern const unsigned char aes128_ecb_encrypt_key[][16];
|
||||
extern const unsigned char aes128_ecb_encrypt_input[][4096];
|
||||
extern const unsigned char aes128_ecb_encrypt_ref_output[][4096];
|
||||
extern unsigned char aes128_ecb_encrypt_output[][4096];
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// The confidential and proprietary information contained in this file may
|
||||
// only be used by a person authorised under and to the extent permitted
|
||||
// by a subsisting licensing agreement from ARM Limited.
|
||||
//
|
||||
// (C) COPYRIGHT 2012-2013 ARM Limited.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// This entire notice must be reproduced on all copies of this file
|
||||
// and copies of this file may only be made by a person if such person is
|
||||
// permitted to do so under the terms of a subsisting license agreement
|
||||
// from ARM Limited.
|
||||
//
|
||||
// SVN Information
|
||||
//
|
||||
// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
|
||||
//
|
||||
// Revision : $Revision: 241584 $
|
||||
//
|
||||
// Release Information :
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out);
|
||||
extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size);
|
||||
|
||||
@ -1,138 +0,0 @@
|
||||
;#-----------------------------------------------------------------------------
|
||||
;# The confidential and proprietary information contained in this file may
|
||||
;# only be used by a person authorised under and to the extent permitted
|
||||
;# by a subsisting licensing agreement from ARM Limited.
|
||||
;#
|
||||
;# (C) COPYRIGHT 2012-2013 ARM Limited.
|
||||
;# ALL RIGHTS RESERVED
|
||||
;#
|
||||
;# This entire notice must be reproduced on all copies of this file
|
||||
;# and copies of this file may only be made by a person if such person is
|
||||
;# permitted to do so under the terms of a subsisting license agreement
|
||||
;# from ARM Limited.
|
||||
;#
|
||||
;# SVN Information
|
||||
;#
|
||||
;# Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
|
||||
;#
|
||||
;# Revision : $Revision: 241584 $
|
||||
;#
|
||||
;# Release Information :
|
||||
;#
|
||||
;#-----------------------------------------------------------------------------
|
||||
|
||||
.section aes_code, "ax"
|
||||
|
||||
.global aes128_key_expand
|
||||
.global aes128_ecb_encrypt
|
||||
|
||||
.align 6
|
||||
rcon_array:
|
||||
.word 0x00000001
|
||||
.word 0x00000002
|
||||
.word 0x00000004
|
||||
.word 0x00000008
|
||||
.word 0x00000010
|
||||
.word 0x00000020
|
||||
.word 0x00000040
|
||||
.word 0x00000080
|
||||
.word 0x0000001b
|
||||
.word 0x00000036
|
||||
|
||||
.align 6
|
||||
;# void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out)
|
||||
.type aes128_key_expand STT_FUNC
|
||||
aes128_key_expand:
|
||||
LD1 {v16.16B}, [x0]
|
||||
MOVZ w2, #0x0e0d
|
||||
DUP v17.16B, wzr
|
||||
MOVK w2, #0x0c0f, lsl #16
|
||||
DUP v19.4S, w2
|
||||
ADR x3, rcon_array
|
||||
MOV w4, #10
|
||||
exp:
|
||||
TBL v18.16B, {v16.16B}, v19.16B
|
||||
LD1R {v21.4S}, [x3], #4
|
||||
AESE v18.16B, v17.16B
|
||||
EXT v20.16B, v17.16B, v16.16B, #12
|
||||
SHA1SU0 v21.4S, v18.4S, v17.4S
|
||||
EOR v22.16B, v16.16B, v20.16B
|
||||
ST1 {v16.16B}, [x1], #16
|
||||
SHA1SU0 v21.4S, v22.4S, v22.4S
|
||||
|
||||
TBL v18.16B, {v21.16B}, v19.16B
|
||||
LD1R {v16.4S}, [x3], #4
|
||||
AESE v18.16B, v17.16B
|
||||
EXT v20.16B, v17.16B, v21.16B, #12
|
||||
SHA1SU0 v16.4S, v18.4S, v17.4S
|
||||
EOR v22.16B, v21.16B, v20.16B
|
||||
ST1 {v21.16B}, [x1], #16
|
||||
SUBS w4, w4, #2
|
||||
SHA1SU0 v16.4S, v22.4S, v22.4S
|
||||
|
||||
B.NE exp
|
||||
ST1 {v16.16B}, [x1]
|
||||
RET
|
||||
|
||||
.macro aes_enc_round keyreg
|
||||
AESE v0.16B, \keyreg
|
||||
AESMC v0.16B, v0.16B
|
||||
AESE v1.16B, \keyreg
|
||||
AESMC v1.16B, v1.16B
|
||||
AESE v2.16B, \keyreg
|
||||
AESMC v2.16B, v2.16B
|
||||
.endm
|
||||
|
||||
.macro aes_dec_round keyreg
|
||||
AESD v0.16B, \keyreg
|
||||
AESIMC v0.16B, v0.16B
|
||||
AESD v1.16B, \keyreg
|
||||
AESIMC v1.16B, v1.16B
|
||||
AESD v2.16B, \keyreg
|
||||
AESIMC v2.16B, v2.16B
|
||||
.endm
|
||||
|
||||
;# void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size)
|
||||
.type aes128_ecb_encrypt STT_FUNC
|
||||
aes128_ecb_encrypt:
|
||||
;# Load the key
|
||||
LD1 {v16.16B-v19.16B}, [x0], #64
|
||||
LD1 {v20.16B-v23.16B}, [x0], #64
|
||||
LD1 {v24.16B-v26.16B}, [x0]
|
||||
|
||||
load_ip:
|
||||
;# Load data
|
||||
LD1 {v0.16B-v2.16B}, [x1], #48
|
||||
;# Rounds 1-9
|
||||
aes_enc_round v16.16B
|
||||
aes_enc_round v17.16B
|
||||
aes_enc_round v18.16B
|
||||
aes_enc_round v19.16B
|
||||
aes_enc_round v20.16B
|
||||
aes_enc_round v21.16B
|
||||
aes_enc_round v22.16B
|
||||
aes_enc_round v23.16B
|
||||
aes_enc_round v24.16B
|
||||
;# Round 10
|
||||
AESE v0.16B, v25.16B
|
||||
PRFM PLDL1KEEP, [x1, #64]
|
||||
EOR v0.16B, v0.16B, v26.16B
|
||||
SUBS x3, x3, #16
|
||||
ST1 {v0.16B}, [x2], #16
|
||||
B.EQ end_enc
|
||||
|
||||
AESE v1.16B, v25.16B
|
||||
EOR v1.16B, v1.16B, v26.16B
|
||||
SUBS x3, x3, #16
|
||||
ST1 {v1.16B}, [x2], #16
|
||||
B.EQ end_enc
|
||||
|
||||
AESE v2.16B, v25.16B
|
||||
EOR v2.16B, v2.16B, v26.16B
|
||||
SUBS x3, x3, #16
|
||||
ST1 {v2.16B}, [x2], #16
|
||||
B.GT load_ip
|
||||
end_enc:
|
||||
RET
|
||||
|
||||
.end
|
||||
3
arch/.gitignore
vendored
3
arch/.gitignore
vendored
@ -1,3 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
/i386/
|
||||
/x86_64/
|
||||
1329
arch/Kconfig
1329
arch/Kconfig
File diff suppressed because it is too large
Load Diff
@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += kernel/ mm/
|
||||
obj-$(CONFIG_MATHEMU) += math-emu/
|
||||
|
||||
# for cleaning
|
||||
subdir- += boot
|
||||
@ -1,678 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
config ALPHA
|
||||
bool
|
||||
default y
|
||||
select ARCH_32BIT_USTAT_F_TINODE
|
||||
select ARCH_MIGHT_HAVE_PC_PARPORT
|
||||
select ARCH_MIGHT_HAVE_PC_SERIO
|
||||
select ARCH_NO_PREEMPT
|
||||
select ARCH_NO_SG_CHAIN
|
||||
select ARCH_USE_CMPXCHG_LOCKREF
|
||||
select DMA_OPS if PCI
|
||||
select FORCE_PCI if !ALPHA_JENSEN
|
||||
select PCI_DOMAINS if PCI
|
||||
select PCI_SYSCALL if PCI
|
||||
select HAVE_AOUT
|
||||
select HAVE_ASM_MODVERSIONS
|
||||
select HAVE_PCSPKR_PLATFORM
|
||||
select HAVE_PERF_EVENTS
|
||||
select NEED_DMA_MAP_STATE
|
||||
select NEED_SG_DMA_LENGTH
|
||||
select VIRT_TO_BUS
|
||||
select GENERIC_IRQ_PROBE
|
||||
select GENERIC_PCI_IOMAP
|
||||
select AUTO_IRQ_AFFINITY if SMP
|
||||
select GENERIC_IRQ_SHOW
|
||||
select ARCH_WANT_IPC_PARSE_VERSION
|
||||
select ARCH_HAVE_NMI_SAFE_CMPXCHG
|
||||
select AUDIT_ARCH
|
||||
select GENERIC_CPU_VULNERABILITIES
|
||||
select GENERIC_SMP_IDLE_THREAD
|
||||
select HAVE_ARCH_AUDITSYSCALL
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select MODULES_USE_ELF_RELA
|
||||
select ODD_RT_SIGACTION
|
||||
select OLD_SIGSUSPEND
|
||||
select CPU_NO_EFFICIENT_FFS if !ALPHA_EV67
|
||||
select MMU_GATHER_NO_RANGE
|
||||
select SET_FS
|
||||
select SPARSEMEM_EXTREME if SPARSEMEM
|
||||
select ZONE_DMA
|
||||
help
|
||||
The Alpha is a 64-bit general-purpose processor designed and
|
||||
marketed by the Digital Equipment Corporation of blessed memory,
|
||||
now Hewlett-Packard. The Alpha Linux project has a home page at
|
||||
<http://www.alphalinux.org/>.
|
||||
|
||||
config 64BIT
|
||||
def_bool y
|
||||
|
||||
config MMU
|
||||
bool
|
||||
default y
|
||||
|
||||
config ARCH_HAS_ILOG2_U32
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_HAS_ILOG2_U64
|
||||
bool
|
||||
default n
|
||||
|
||||
config GENERIC_CALIBRATE_DELAY
|
||||
bool
|
||||
default y
|
||||
|
||||
config GENERIC_ISA_DMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config PGTABLE_LEVELS
|
||||
int
|
||||
default 3
|
||||
|
||||
config AUDIT_ARCH
|
||||
bool
|
||||
|
||||
menu "System setup"
|
||||
|
||||
choice
|
||||
prompt "Alpha system type"
|
||||
default ALPHA_GENERIC
|
||||
help
|
||||
This is the system type of your hardware. A "generic" kernel will
|
||||
run on any supported Alpha system. However, if you configure a
|
||||
kernel for your specific system, it will be faster and smaller.
|
||||
|
||||
To find out what type of Alpha system you have, you may want to
|
||||
check out the Linux/Alpha FAQ, accessible on the WWW from
|
||||
<http://www.alphalinux.org/>. In summary:
|
||||
|
||||
Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
|
||||
Alpha-XL XL-233, XL-266
|
||||
AlphaBook1 Alpha laptop
|
||||
Avanti AS 200, AS 205, AS 250, AS 255, AS 300, AS 400
|
||||
Cabriolet AlphaPC64, AlphaPCI64
|
||||
DP264 DP264 / DS20 / ES40 / DS10 / DS10L
|
||||
EB164 EB164 21164 evaluation board
|
||||
EB64+ EB64+ 21064 evaluation board
|
||||
EB66 EB66 21066 evaluation board
|
||||
EB66+ EB66+ 21066 evaluation board
|
||||
Jensen DECpc 150, DEC 2000 models 300, 500
|
||||
LX164 AlphaPC164-LX
|
||||
Lynx AS 2100A
|
||||
Miata Personal Workstation 433/500/600 a/au
|
||||
Marvel AlphaServer ES47 / ES80 / GS1280
|
||||
Mikasa AS 1000
|
||||
Noname AXPpci33, UDB (Multia)
|
||||
Noritake AS 1000A, AS 600A, AS 800
|
||||
PC164 AlphaPC164
|
||||
Rawhide AS 1200, AS 4000, AS 4100
|
||||
Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
|
||||
SX164 AlphaPC164-SX
|
||||
Sable AS 2000, AS 2100
|
||||
Shark DS 20L
|
||||
Takara Takara (OEM)
|
||||
Titan AlphaServer ES45 / DS25 / DS15
|
||||
Wildfire AlphaServer GS 40/80/160/320
|
||||
|
||||
If you don't know what to do, choose "generic".
|
||||
|
||||
config ALPHA_GENERIC
|
||||
bool "Generic"
|
||||
depends on TTY
|
||||
select HAVE_EISA
|
||||
help
|
||||
A generic kernel will run on all supported Alpha hardware.
|
||||
|
||||
config ALPHA_ALCOR
|
||||
bool "Alcor/Alpha-XLT"
|
||||
select HAVE_EISA
|
||||
help
|
||||
For systems using the Digital ALCOR chipset: 5 chips (4, 64-bit data
|
||||
slices (Data Switch, DSW) - 208-pin PQFP and 1 control (Control, I/O
|
||||
Address, CIA) - a 383 pin plastic PGA). It provides a DRAM
|
||||
controller (256-bit memory bus) and a PCI interface. It also does
|
||||
all the work required to support an external Bcache and to maintain
|
||||
memory coherence when a PCI device DMAs into (or out of) memory.
|
||||
|
||||
config ALPHA_XL
|
||||
bool "Alpha-XL"
|
||||
help
|
||||
XL-233 and XL-266-based Alpha systems.
|
||||
|
||||
config ALPHA_BOOK1
|
||||
bool "AlphaBook1"
|
||||
help
|
||||
Dec AlphaBook1/Burns Alpha-based laptops.
|
||||
|
||||
config ALPHA_AVANTI_CH
|
||||
bool "Avanti"
|
||||
|
||||
config ALPHA_CABRIOLET
|
||||
bool "Cabriolet"
|
||||
help
|
||||
Cabriolet AlphaPC64, AlphaPCI64 systems. Derived from EB64+ but now
|
||||
baby-AT with Flash boot ROM, no on-board SCSI or Ethernet. 3 ISA
|
||||
slots, 4 PCI slots (one pair are on a shared slot), uses plug-in
|
||||
Bcache SIMMs. Requires power supply with 3.3V output.
|
||||
|
||||
config ALPHA_DP264
|
||||
bool "DP264"
|
||||
help
|
||||
Various 21264 systems with the tsunami core logic chipset.
|
||||
API Networks: 264DP, UP2000(+), CS20;
|
||||
Compaq: DS10(E,L), XP900, XP1000, DS20(E), ES40.
|
||||
|
||||
config ALPHA_EB164
|
||||
bool "EB164"
|
||||
help
|
||||
EB164 21164 evaluation board from DEC. Uses 21164 and ALCOR. Has
|
||||
ISA and PCI expansion (3 ISA slots, 2 64-bit PCI slots (one is
|
||||
shared with an ISA slot) and 2 32-bit PCI slots. Uses plus-in
|
||||
Bcache SIMMs. I/O sub-system provides SuperI/O (2S, 1P, FD), KBD,
|
||||
MOUSE (PS2 style), RTC/NVRAM. Boot ROM is Flash. PC-AT-sized
|
||||
motherboard. Requires power supply with 3.3V output.
|
||||
|
||||
config ALPHA_EB64P_CH
|
||||
bool "EB64+"
|
||||
|
||||
config ALPHA_EB66
|
||||
bool "EB66"
|
||||
help
|
||||
A Digital DS group board. Uses 21066 or 21066A. I/O sub-system is
|
||||
identical to EB64+. Baby PC-AT size. Runs from standard PC power
|
||||
supply. The EB66 schematic was published as a marketing poster
|
||||
advertising the 21066 as "the first microprocessor in the world with
|
||||
embedded PCI".
|
||||
|
||||
config ALPHA_EB66P
|
||||
bool "EB66+"
|
||||
help
|
||||
Later variant of the EB66 board.
|
||||
|
||||
config ALPHA_EIGER
|
||||
bool "Eiger"
|
||||
help
|
||||
Apparently an obscure OEM single-board computer based on the
|
||||
Typhoon/Tsunami chipset family. Information on it is scanty.
|
||||
|
||||
config ALPHA_JENSEN
|
||||
bool "Jensen"
|
||||
select HAVE_EISA
|
||||
help
|
||||
DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one
|
||||
of the first-generation Alpha systems. A number of these systems
|
||||
seem to be available on the second- hand market. The Jensen is a
|
||||
floor-standing tower system which originally used a 150MHz 21064 It
|
||||
used programmable logic to interface a 486 EISA I/O bridge to the
|
||||
CPU.
|
||||
|
||||
config ALPHA_LX164
|
||||
bool "LX164"
|
||||
help
|
||||
A technical overview of this board is available at
|
||||
<http://www.unix-ag.org/Linux-Alpha/Architectures/LX164.html>.
|
||||
|
||||
config ALPHA_LYNX
|
||||
bool "Lynx"
|
||||
select HAVE_EISA
|
||||
help
|
||||
AlphaServer 2100A-based systems.
|
||||
|
||||
config ALPHA_MARVEL
|
||||
bool "Marvel"
|
||||
help
|
||||
AlphaServer ES47 / ES80 / GS1280 based on EV7.
|
||||
|
||||
config ALPHA_MIATA
|
||||
bool "Miata"
|
||||
select HAVE_EISA
|
||||
help
|
||||
The Digital PersonalWorkStation (PWS 433a, 433au, 500a, 500au, 600a,
|
||||
or 600au).
|
||||
|
||||
config ALPHA_MIKASA
|
||||
bool "Mikasa"
|
||||
help
|
||||
AlphaServer 1000-based Alpha systems.
|
||||
|
||||
config ALPHA_NAUTILUS
|
||||
bool "Nautilus"
|
||||
help
|
||||
Alpha systems based on the AMD 751 & ALI 1543C chipsets.
|
||||
|
||||
config ALPHA_NONAME_CH
|
||||
bool "Noname"
|
||||
|
||||
config ALPHA_NORITAKE
|
||||
bool "Noritake"
|
||||
select HAVE_EISA
|
||||
help
|
||||
AlphaServer 1000A, AlphaServer 600A, and AlphaServer 800-based
|
||||
systems.
|
||||
|
||||
config ALPHA_PC164
|
||||
bool "PC164"
|
||||
|
||||
config ALPHA_P2K
|
||||
bool "Platform2000"
|
||||
|
||||
config ALPHA_RAWHIDE
|
||||
bool "Rawhide"
|
||||
select HAVE_EISA
|
||||
help
|
||||
AlphaServer 1200, AlphaServer 4000 and AlphaServer 4100 machines.
|
||||
See HOWTO at
|
||||
<http://www.alphalinux.org/docs/rawhide/4100_install.shtml>.
|
||||
|
||||
config ALPHA_RUFFIAN
|
||||
bool "Ruffian"
|
||||
help
|
||||
Samsung APC164UX. There is a page on known problems and workarounds
|
||||
at <http://www.alphalinux.org/faq/FAQ-11.html>.
|
||||
|
||||
config ALPHA_RX164
|
||||
bool "RX164"
|
||||
|
||||
config ALPHA_SX164
|
||||
bool "SX164"
|
||||
|
||||
config ALPHA_SABLE
|
||||
bool "Sable"
|
||||
select HAVE_EISA
|
||||
help
|
||||
Digital AlphaServer 2000 and 2100-based systems.
|
||||
|
||||
config ALPHA_SHARK
|
||||
bool "Shark"
|
||||
|
||||
config ALPHA_TAKARA
|
||||
bool "Takara"
|
||||
help
|
||||
Alpha 11164-based OEM single-board computer.
|
||||
|
||||
config ALPHA_TITAN
|
||||
bool "Titan"
|
||||
help
|
||||
AlphaServer ES45/DS25 SMP based on EV68 and Titan chipset.
|
||||
|
||||
config ALPHA_WILDFIRE
|
||||
bool "Wildfire"
|
||||
help
|
||||
AlphaServer GS 40/80/160/320 SMP based on the EV67 core.
|
||||
|
||||
endchoice
|
||||
|
||||
# clear all implied options (don't want default values for those):
|
||||
# Most of these machines have ISA slots; not exactly sure which don't,
|
||||
# and this doesn't activate hordes of code, so do it always.
|
||||
config ISA
|
||||
bool
|
||||
default y
|
||||
help
|
||||
Find out whether you have ISA slots on your motherboard. ISA is the
|
||||
name of a bus system, i.e. the way the CPU talks to the other stuff
|
||||
inside your box. Other bus systems are PCI, EISA, MicroChannel
|
||||
(MCA) or VESA. ISA is an older system, now being displaced by PCI;
|
||||
newer boards don't support it. If you have ISA, say Y, otherwise N.
|
||||
|
||||
config ISA_DMA_API
|
||||
bool
|
||||
default y
|
||||
|
||||
config ALPHA_NONAME
|
||||
bool
|
||||
depends on ALPHA_BOOK1 || ALPHA_NONAME_CH
|
||||
default y
|
||||
help
|
||||
The AXPpci33 (aka NoName), is based on the EB66 (includes the Multia
|
||||
UDB). This design was produced by Digital's Technical OEM (TOEM)
|
||||
group. It uses the 21066 processor running at 166MHz or 233MHz. It
|
||||
is a baby-AT size, and runs from a standard PC power supply. It has
|
||||
5 ISA slots and 3 PCI slots (one pair are a shared slot). There are
|
||||
2 versions, with either PS/2 or large DIN connectors for the
|
||||
keyboard.
|
||||
|
||||
config ALPHA_EV4
|
||||
bool
|
||||
depends on ALPHA_JENSEN || (ALPHA_SABLE && !ALPHA_GAMMA) || ALPHA_LYNX || ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K
|
||||
default y if !ALPHA_LYNX
|
||||
|
||||
config ALPHA_LCA
|
||||
bool
|
||||
depends on ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K
|
||||
default y
|
||||
|
||||
config ALPHA_APECS
|
||||
bool
|
||||
depends on !ALPHA_PRIMO && (ALPHA_NORITAKE || ALPHA_MIKASA) || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL
|
||||
default y
|
||||
|
||||
config ALPHA_EB64P
|
||||
bool
|
||||
depends on ALPHA_CABRIOLET || ALPHA_EB64P_CH
|
||||
default y
|
||||
help
|
||||
Uses 21064 or 21064A and APECs. Has ISA and PCI expansion (3 ISA,
|
||||
2 PCI, one pair are on a shared slot). Supports 36-bit DRAM SIMs.
|
||||
ISA bus generated by Intel SaturnI/O PCI-ISA bridge. On-board SCSI
|
||||
(NCR 810 on PCI) Ethernet (Digital 21040), KBD, MOUSE (PS2 style),
|
||||
SuperI/O (2S, 1P, FD), RTC/NVRAM. Boot ROM is EPROM. PC-AT size.
|
||||
Runs from standard PC power supply.
|
||||
|
||||
config ALPHA_EV5
|
||||
bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_LYNX
|
||||
default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE && ALPHA_GAMMA || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR
|
||||
|
||||
config ALPHA_EV4
|
||||
bool
|
||||
default y if ALPHA_LYNX && !ALPHA_EV5
|
||||
|
||||
config ALPHA_CIA
|
||||
bool
|
||||
depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR
|
||||
default y
|
||||
|
||||
config ALPHA_EV56
|
||||
bool "EV56 CPU (speed >= 366MHz)?" if ALPHA_ALCOR
|
||||
default y if ALPHA_RX164 || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_PC164 || ALPHA_TAKARA
|
||||
|
||||
config ALPHA_EV56
|
||||
prompt "EV56 CPU (speed >= 333MHz)?"
|
||||
depends on ALPHA_NORITAKE || ALPHA_PRIMO
|
||||
|
||||
config ALPHA_EV56
|
||||
prompt "EV56 CPU (speed >= 400MHz)?"
|
||||
depends on ALPHA_RAWHIDE
|
||||
|
||||
config ALPHA_PRIMO
|
||||
bool "EV5 CPU daughtercard (model 5/xxx)?"
|
||||
depends on ALPHA_NORITAKE || ALPHA_MIKASA
|
||||
help
|
||||
Say Y if you have an AS 1000 5/xxx or an AS 1000A 5/xxx.
|
||||
|
||||
config ALPHA_GAMMA
|
||||
bool "EV5 CPU(s) (model 5/xxx)?"
|
||||
depends on ALPHA_SABLE
|
||||
help
|
||||
Say Y if you have an AS 2000 5/xxx or an AS 2100 5/xxx.
|
||||
|
||||
config ALPHA_GAMMA
|
||||
bool
|
||||
depends on ALPHA_LYNX
|
||||
default y
|
||||
|
||||
config ALPHA_T2
|
||||
bool
|
||||
depends on ALPHA_SABLE || ALPHA_LYNX
|
||||
default y
|
||||
|
||||
config ALPHA_PYXIS
|
||||
bool
|
||||
depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN
|
||||
default y
|
||||
|
||||
config ALPHA_EV6
|
||||
bool
|
||||
depends on ALPHA_NAUTILUS || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_DP264 || ALPHA_EIGER || ALPHA_MARVEL
|
||||
default y
|
||||
|
||||
config ALPHA_TSUNAMI
|
||||
bool
|
||||
depends on ALPHA_SHARK || ALPHA_DP264 || ALPHA_EIGER
|
||||
default y
|
||||
|
||||
config ALPHA_EV67
|
||||
bool "EV67 (or later) CPU (speed > 600MHz)?" if ALPHA_DP264 || ALPHA_EIGER
|
||||
default y if ALPHA_NAUTILUS || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL
|
||||
help
|
||||
Is this a machine based on the EV67 core? If in doubt, select N here
|
||||
and the machine will be treated as an EV6.
|
||||
|
||||
config ALPHA_MCPCIA
|
||||
bool
|
||||
depends on ALPHA_RAWHIDE
|
||||
default y
|
||||
|
||||
config ALPHA_POLARIS
|
||||
bool
|
||||
depends on ALPHA_RX164
|
||||
default y
|
||||
|
||||
config ALPHA_IRONGATE
|
||||
bool
|
||||
depends on ALPHA_NAUTILUS
|
||||
default y
|
||||
|
||||
config GENERIC_HWEIGHT
|
||||
bool
|
||||
default y if !ALPHA_EV67
|
||||
|
||||
config ALPHA_AVANTI
|
||||
bool
|
||||
depends on ALPHA_XL || ALPHA_AVANTI_CH
|
||||
default y
|
||||
help
|
||||
Avanti AS 200, AS 205, AS 250, AS 255, AS 300, and AS 400-based
|
||||
Alphas. Info at
|
||||
<http://www.unix-ag.org/Linux-Alpha/Architectures/Avanti.html>.
|
||||
|
||||
config ALPHA_BROKEN_IRQ_MASK
|
||||
bool
|
||||
depends on ALPHA_GENERIC || ALPHA_PC164
|
||||
default y
|
||||
|
||||
config VGA_HOSE
|
||||
bool
|
||||
depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
|
||||
default y
|
||||
help
|
||||
Support VGA on an arbitrary hose; needed for several platforms
|
||||
which always have multiple hoses, and whose consoles support it.
|
||||
|
||||
|
||||
config ALPHA_QEMU
|
||||
bool "Run under QEMU emulation"
|
||||
depends on !ALPHA_GENERIC
|
||||
help
|
||||
Assume the presence of special features supported by QEMU PALcode
|
||||
that reduce the overhead of system emulation.
|
||||
|
||||
Generic kernels will auto-detect QEMU. But when building a
|
||||
system-specific kernel, the assumption is that we want to
|
||||
eliminate as many runtime tests as possible.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
|
||||
config ALPHA_SRM
|
||||
bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME
|
||||
depends on TTY
|
||||
default y if ALPHA_JENSEN || ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL
|
||||
help
|
||||
There are two different types of booting firmware on Alphas: SRM,
|
||||
which is command line driven, and ARC, which uses menus and arrow
|
||||
keys. Details about the Linux/Alpha booting process are contained in
|
||||
the Linux/Alpha FAQ, accessible on the WWW from
|
||||
<http://www.alphalinux.org/>.
|
||||
|
||||
The usual way to load Linux on an Alpha machine is to use MILO
|
||||
(a bootloader that lets you pass command line parameters to the
|
||||
kernel just like lilo does for the x86 architecture) which can be
|
||||
loaded either from ARC or can be installed directly as a permanent
|
||||
firmware replacement from floppy (which requires changing a certain
|
||||
jumper on the motherboard). If you want to do either of these, say N
|
||||
here. If MILO doesn't work on your system (true for Jensen
|
||||
motherboards), you can bypass it altogether and boot Linux directly
|
||||
from an SRM console; say Y here in order to do that. Note that you
|
||||
won't be able to boot from an IDE disk using SRM.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
config ARCH_MAY_HAVE_PC_FDC
|
||||
def_bool y
|
||||
|
||||
config SMP
|
||||
bool "Symmetric multi-processing support"
|
||||
depends on ALPHA_SABLE || ALPHA_LYNX || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL
|
||||
help
|
||||
This enables support for systems with more than one CPU. If you have
|
||||
a system with only one CPU, say N. If you have a system with more
|
||||
than one CPU, say Y.
|
||||
|
||||
If you say N here, the kernel will run on uni- and multiprocessor
|
||||
machines, but will use only one CPU of a multiprocessor machine. If
|
||||
you say Y here, the kernel will run on many, but not all,
|
||||
uniprocessor machines. On a uniprocessor machine, the kernel
|
||||
will run faster if you say N here.
|
||||
|
||||
See also the SMP-HOWTO available at
|
||||
<https://www.tldp.org/docs.html#howto>.
|
||||
|
||||
If you don't know what to do here, say N.
|
||||
|
||||
config NR_CPUS
|
||||
int "Maximum number of CPUs (2-32)"
|
||||
range 2 32
|
||||
depends on SMP
|
||||
default "32" if ALPHA_GENERIC || ALPHA_MARVEL
|
||||
default "4" if !ALPHA_GENERIC && !ALPHA_MARVEL
|
||||
help
|
||||
MARVEL support can handle a maximum of 32 CPUs, all the others
|
||||
with working support have a maximum of 4 CPUs.
|
||||
|
||||
config ARCH_SPARSEMEM_ENABLE
|
||||
bool "Sparse Memory Support"
|
||||
help
|
||||
Say Y to support efficient handling of discontiguous physical memory,
|
||||
for systems that have huge holes in the physical address space.
|
||||
|
||||
config ALPHA_WTINT
|
||||
bool "Use WTINT" if ALPHA_SRM || ALPHA_GENERIC
|
||||
default y if ALPHA_QEMU
|
||||
default n if ALPHA_EV5 || ALPHA_EV56 || (ALPHA_EV4 && !ALPHA_LCA)
|
||||
default n if !ALPHA_SRM && !ALPHA_GENERIC
|
||||
default y if SMP
|
||||
help
|
||||
The Wait for Interrupt (WTINT) PALcall attempts to place the CPU
|
||||
to sleep until the next interrupt. This may reduce the power
|
||||
consumed, and the heat produced by the computer. However, it has
|
||||
the side effect of making the cycle counter unreliable as a timing
|
||||
device across the sleep.
|
||||
|
||||
For emulation under QEMU, definitely say Y here, as we have other
|
||||
mechanisms for measuring time than the cycle counter.
|
||||
|
||||
For EV4 (but not LCA), EV5 and EV56 systems, or for systems running
|
||||
MILO, sleep mode is not supported so you might as well say N here.
|
||||
|
||||
For SMP systems we cannot use the cycle counter for timing anyway,
|
||||
so you might as well say Y here.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
# LARGE_VMALLOC is racy, if you *really* need it then fix it first
|
||||
config ALPHA_LARGE_VMALLOC
|
||||
bool
|
||||
help
|
||||
Process creation and other aspects of virtual memory management can
|
||||
be streamlined if we restrict the kernel to one PGD for all vmalloc
|
||||
allocations. This equates to about 8GB.
|
||||
|
||||
Under normal circumstances, this is so far and above what is needed
|
||||
as to be laughable. However, there are certain applications (such
|
||||
as benchmark-grade in-kernel web serving) that can make use of as
|
||||
much vmalloc space as is available.
|
||||
|
||||
Say N unless you know you need gobs and gobs of vmalloc space.
|
||||
|
||||
config VERBOSE_MCHECK
|
||||
bool "Verbose Machine Checks"
|
||||
|
||||
config VERBOSE_MCHECK_ON
|
||||
int "Verbose Printing Mode (0=off, 1=on, 2=all)"
|
||||
depends on VERBOSE_MCHECK
|
||||
default 1
|
||||
help
|
||||
This option allows the default printing mode to be set, and then
|
||||
possibly overridden by a boot command argument.
|
||||
|
||||
For example, if one wanted the option of printing verbose
|
||||
machine checks, but wanted the default to be as if verbose
|
||||
machine check printing was turned off, then one would choose
|
||||
the printing mode to be 0. Then, upon reboot, one could add
|
||||
the boot command line "verbose_mcheck=1" to get the normal
|
||||
verbose machine check printing, or "verbose_mcheck=2" to get
|
||||
the maximum information available.
|
||||
|
||||
Take the default (1) unless you want more control or more info.
|
||||
|
||||
choice
|
||||
prompt "Timer interrupt frequency (HZ)?"
|
||||
default HZ_128 if ALPHA_QEMU
|
||||
default HZ_1200 if ALPHA_RAWHIDE
|
||||
default HZ_1024
|
||||
help
|
||||
The frequency at which timer interrupts occur. A high frequency
|
||||
minimizes latency, whereas a low frequency minimizes overhead of
|
||||
process accounting. The later effect is especially significant
|
||||
when being run under QEMU.
|
||||
|
||||
Note that some Alpha hardware cannot change the interrupt frequency
|
||||
of the timer. If unsure, say 1024 (or 1200 for Rawhide).
|
||||
|
||||
config HZ_32
|
||||
bool "32 Hz"
|
||||
config HZ_64
|
||||
bool "64 Hz"
|
||||
config HZ_128
|
||||
bool "128 Hz"
|
||||
config HZ_256
|
||||
bool "256 Hz"
|
||||
config HZ_1024
|
||||
bool "1024 Hz"
|
||||
config HZ_1200
|
||||
bool "1200 Hz"
|
||||
endchoice
|
||||
|
||||
config HZ
|
||||
int
|
||||
default 32 if HZ_32
|
||||
default 64 if HZ_64
|
||||
default 128 if HZ_128
|
||||
default 256 if HZ_256
|
||||
default 1200 if HZ_1200
|
||||
default 1024
|
||||
|
||||
config SRM_ENV
|
||||
tristate "SRM environment through procfs"
|
||||
depends on PROC_FS
|
||||
help
|
||||
If you enable this option, a subdirectory inside /proc called
|
||||
/proc/srm_environment will give you access to the all important
|
||||
SRM environment variables (those which have a name) and also
|
||||
to all others (by their internal number).
|
||||
|
||||
SRM is something like a BIOS for Alpha machines. There are some
|
||||
other such BIOSes, like AlphaBIOS, which this driver cannot
|
||||
support (hey, that's not SRM!).
|
||||
|
||||
Despite the fact that this driver doesn't work on all Alphas (but
|
||||
only on those which have SRM as their firmware), it's save to
|
||||
build it even if your particular machine doesn't know about SRM
|
||||
(or if you intend to compile a generic kernel). It will simply
|
||||
not create those subdirectory in /proc (and give you some warning,
|
||||
of course).
|
||||
|
||||
This driver is also available as a module and will be called
|
||||
srm_env then.
|
||||
|
||||
endmenu
|
||||
|
||||
# DUMMY_CONSOLE may be defined in drivers/video/console/Kconfig
|
||||
# but we also need it if VGA_HOSE is set
|
||||
config DUMMY_CONSOLE
|
||||
bool
|
||||
depends on VGA_HOSE
|
||||
default y
|
||||
@ -1,38 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
config EARLY_PRINTK
|
||||
bool
|
||||
depends on ALPHA_GENERIC || ALPHA_SRM
|
||||
default y
|
||||
|
||||
config ALPHA_LEGACY_START_ADDRESS
|
||||
bool "Legacy kernel start address"
|
||||
depends on ALPHA_GENERIC
|
||||
default n
|
||||
help
|
||||
The 2.4 kernel changed the kernel start address from 0x310000
|
||||
to 0x810000 to make room for the Wildfire's larger SRM console.
|
||||
Recent consoles on Titan and Marvel machines also require the
|
||||
extra room.
|
||||
|
||||
If you're using aboot 0.7 or later, the bootloader will examine the
|
||||
ELF headers to determine where to transfer control. Unfortunately,
|
||||
most older bootloaders -- APB or MILO -- hardcoded the kernel start
|
||||
address rather than examining the ELF headers, and the result is a
|
||||
hard lockup.
|
||||
|
||||
Say Y if you have a broken bootloader. Say N if you do not, or if
|
||||
you wish to run on Wildfire, Titan, or Marvel.
|
||||
|
||||
config ALPHA_LEGACY_START_ADDRESS
|
||||
bool
|
||||
depends on !ALPHA_GENERIC && !ALPHA_TITAN && !ALPHA_MARVEL && !ALPHA_WILDFIRE
|
||||
default y
|
||||
|
||||
config MATHEMU
|
||||
tristate "Kernel FP software completion" if DEBUG_KERNEL && !SMP
|
||||
default y if !DEBUG_KERNEL || SMP
|
||||
help
|
||||
This option is required for IEEE compliant floating point arithmetic
|
||||
on the Alpha. The only time you would ever not say Y is to say M in
|
||||
order to debug the code. Say Y unless you know what you are doing.
|
||||
@ -1,66 +0,0 @@
|
||||
#
|
||||
# alpha/Makefile
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU General Public
|
||||
# License. See the file "COPYING" in the main directory of this archive
|
||||
# for more details.
|
||||
#
|
||||
# Copyright (C) 1994 by Linus Torvalds
|
||||
#
|
||||
|
||||
NM := $(NM) -B
|
||||
|
||||
LDFLAGS_vmlinux := -static -N #-relax
|
||||
CHECKFLAGS += -D__alpha__
|
||||
cflags-y := -pipe -mno-fp-regs -ffixed-8
|
||||
cflags-y += $(call cc-option, -fno-jump-tables)
|
||||
|
||||
cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4
|
||||
cpuflags-$(CONFIG_ALPHA_EV5) := -mcpu=ev5
|
||||
cpuflags-$(CONFIG_ALPHA_EV56) := -mcpu=ev56
|
||||
cpuflags-$(CONFIG_ALPHA_POLARIS) := -mcpu=pca56
|
||||
cpuflags-$(CONFIG_ALPHA_SX164) := -mcpu=pca56
|
||||
cpuflags-$(CONFIG_ALPHA_EV6) := -mcpu=ev6
|
||||
cpuflags-$(CONFIG_ALPHA_EV67) := -mcpu=ev67
|
||||
# If GENERIC, make sure to turn off any instruction set extensions that
|
||||
# the host compiler might have on by default. Given that EV4 and EV5
|
||||
# have the same instruction set, prefer EV5 because an EV5 schedule is
|
||||
# more likely to keep an EV4 processor busy than vice-versa.
|
||||
cpuflags-$(CONFIG_ALPHA_GENERIC) := -mcpu=ev5
|
||||
|
||||
cflags-y += $(cpuflags-y)
|
||||
|
||||
|
||||
# For TSUNAMI, we must have the assembler not emulate our instructions.
|
||||
# The same is true for IRONGATE, POLARIS, PYXIS.
|
||||
# BWX is most important, but we don't really want any emulation ever.
|
||||
KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6
|
||||
|
||||
head-y := arch/alpha/kernel/head.o
|
||||
|
||||
libs-y += arch/alpha/lib/
|
||||
|
||||
# export what is needed by arch/alpha/boot/Makefile
|
||||
LIBS_Y := $(patsubst %/, %/lib.a, $(libs-y))
|
||||
export LIBS_Y
|
||||
|
||||
boot := arch/alpha/boot
|
||||
|
||||
#Default target when executing make with no arguments
|
||||
all boot: $(boot)/vmlinux.gz
|
||||
|
||||
$(boot)/vmlinux.gz: vmlinux
|
||||
$(Q)$(MAKE) $(build)=$(boot) $@
|
||||
|
||||
bootimage bootpfile bootpzfile: vmlinux
|
||||
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
|
||||
|
||||
archheaders:
|
||||
$(Q)$(MAKE) $(build)=arch/alpha/kernel/syscalls all
|
||||
|
||||
define archhelp
|
||||
echo '* boot - Compressed kernel image (arch/alpha/boot/vmlinux.gz)'
|
||||
echo ' bootimage - SRM bootable image (arch/alpha/boot/bootimage)'
|
||||
echo ' bootpfile - BOOTP bootable image (arch/alpha/boot/bootpfile)'
|
||||
echo ' bootpzfile - compressed kernel BOOTP image (arch/alpha/boot/bootpzfile)'
|
||||
endef
|
||||
@ -1,120 +0,0 @@
|
||||
#
|
||||
# arch/alpha/boot/Makefile
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU General Public
|
||||
# License. See the file "COPYING" in the main directory of this archive
|
||||
# for more details.
|
||||
#
|
||||
# Copyright (C) 1994 by Linus Torvalds
|
||||
#
|
||||
|
||||
hostprogs := tools/mkbb tools/objstrip
|
||||
targets := vmlinux.gz vmlinux \
|
||||
vmlinux.nh tools/lxboot tools/bootlx tools/bootph \
|
||||
tools/bootpzh bootloader bootpheader bootpzheader
|
||||
OBJSTRIP := $(obj)/tools/objstrip
|
||||
|
||||
KBUILD_HOSTCFLAGS := -Wall -I$(objtree)/usr/include
|
||||
BOOTCFLAGS += -I$(objtree)/$(obj) -I$(srctree)/$(obj)
|
||||
|
||||
# SRM bootable image. Copy to offset 512 of a partition.
|
||||
$(obj)/bootimage: $(addprefix $(obj)/tools/,mkbb lxboot bootlx) $(obj)/vmlinux.nh
|
||||
( cat $(obj)/tools/lxboot $(obj)/tools/bootlx $(obj)/vmlinux.nh ) > $@
|
||||
$(obj)/tools/mkbb $@ $(obj)/tools/lxboot
|
||||
@echo ' Bootimage $@ is ready'
|
||||
|
||||
# BOOTP bootable image. Define INITRD during make to append initrd image.
|
||||
$(obj)/bootpfile: $(obj)/tools/bootph $(obj)/vmlinux.nh
|
||||
cat $(obj)/tools/bootph $(obj)/vmlinux.nh > $@
|
||||
ifdef INITRD
|
||||
cat $(INITRD) >> $@
|
||||
endif
|
||||
|
||||
# Compressed kernel BOOTP bootable image.
|
||||
# Define INITRD during make to append initrd image.
|
||||
$(obj)/bootpzfile: $(obj)/tools/bootpzh $(obj)/vmlinux.nh.gz
|
||||
cat $(obj)/tools/bootpzh $(obj)/vmlinux.nh.gz > $@
|
||||
ifdef INITRD
|
||||
cat $(INITRD) >> $@
|
||||
endif
|
||||
|
||||
# Compressed kernel image
|
||||
$(obj)/vmlinux.gz: $(obj)/vmlinux FORCE
|
||||
$(call if_changed,gzip)
|
||||
@echo ' Kernel $@ is ready'
|
||||
|
||||
$(obj)/main.o: $(obj)/ksize.h
|
||||
$(obj)/bootp.o: $(obj)/ksize.h
|
||||
$(obj)/bootpz.o: $(obj)/kzsize.h
|
||||
|
||||
$(obj)/ksize.h: $(obj)/vmlinux.nh FORCE
|
||||
echo "#define KERNEL_SIZE `ls -l $(obj)/vmlinux.nh | awk '{print $$5}'`" > $@T
|
||||
ifdef INITRD
|
||||
[ -f $(INITRD) ] || exit 1
|
||||
echo "#define INITRD_IMAGE_SIZE `ls -l $(INITRD) | awk '{print $$5}'`" >> $@T
|
||||
endif
|
||||
cmp -s $@T $@ || mv -f $@T $@
|
||||
rm -f $@T
|
||||
|
||||
$(obj)/kzsize.h: $(obj)/vmlinux.nh.gz FORCE
|
||||
echo "#define KERNEL_SIZE `ls -l $(obj)/vmlinux.nh | awk '{print $$5}'`" > $@T
|
||||
echo "#define KERNEL_Z_SIZE `ls -l $(obj)/vmlinux.nh.gz | awk '{print $$5}'`" >> $@T
|
||||
ifdef INITRD
|
||||
[ -f $(INITRD) ] || exit 1
|
||||
echo "#define INITRD_IMAGE_SIZE `ls -l $(INITRD) | awk '{print $$5}'`" >> $@T
|
||||
endif
|
||||
cmp -s $@T $@ || mv -f $@T $@
|
||||
rm -f $@T
|
||||
|
||||
quiet_cmd_strip = STRIP $@
|
||||
cmd_strip = $(STRIP) -o $@ $<
|
||||
|
||||
$(obj)/vmlinux: vmlinux FORCE
|
||||
$(call if_changed,strip)
|
||||
|
||||
quiet_cmd_objstrip = OBJSTRIP $@
|
||||
cmd_objstrip = $(OBJSTRIP) $(OSFLAGS_$(@F)) $< $@
|
||||
|
||||
OSFLAGS_vmlinux.nh := -v
|
||||
OSFLAGS_lxboot := -p
|
||||
OSFLAGS_bootlx := -vb
|
||||
OSFLAGS_bootph := -vb
|
||||
OSFLAGS_bootpzh := -vb
|
||||
|
||||
$(obj)/vmlinux.nh: vmlinux $(OBJSTRIP) FORCE
|
||||
$(call if_changed,objstrip)
|
||||
|
||||
$(obj)/vmlinux.nh.gz: $(obj)/vmlinux.nh FORCE
|
||||
$(call if_changed,gzip)
|
||||
|
||||
$(obj)/tools/lxboot: $(obj)/bootloader $(OBJSTRIP) FORCE
|
||||
$(call if_changed,objstrip)
|
||||
|
||||
$(obj)/tools/bootlx: $(obj)/bootloader $(OBJSTRIP) FORCE
|
||||
$(call if_changed,objstrip)
|
||||
|
||||
$(obj)/tools/bootph: $(obj)/bootpheader $(OBJSTRIP) FORCE
|
||||
$(call if_changed,objstrip)
|
||||
|
||||
$(obj)/tools/bootpzh: $(obj)/bootpzheader $(OBJSTRIP) FORCE
|
||||
$(call if_changed,objstrip)
|
||||
|
||||
LDFLAGS_bootloader := -static -T # -N -relax
|
||||
LDFLAGS_bootloader := -static -T # -N -relax
|
||||
LDFLAGS_bootpheader := -static -T # -N -relax
|
||||
LDFLAGS_bootpzheader := -static -T # -N -relax
|
||||
|
||||
OBJ_bootlx := $(obj)/head.o $(obj)/stdio.o $(obj)/main.o
|
||||
OBJ_bootph := $(obj)/head.o $(obj)/stdio.o $(obj)/bootp.o
|
||||
OBJ_bootpzh := $(obj)/head.o $(obj)/stdio.o $(obj)/bootpz.o $(obj)/misc.o
|
||||
|
||||
$(obj)/bootloader: $(obj)/bootloader.lds $(OBJ_bootlx) $(LIBS_Y) FORCE
|
||||
$(call if_changed,ld)
|
||||
|
||||
$(obj)/bootpheader: $(obj)/bootloader.lds $(OBJ_bootph) $(LIBS_Y) FORCE
|
||||
$(call if_changed,ld)
|
||||
|
||||
$(obj)/bootpzheader: $(obj)/bootloader.lds $(OBJ_bootpzh) $(LIBS_Y) FORCE
|
||||
$(call if_changed,ld)
|
||||
|
||||
$(obj)/misc.o: lib/inflate.c
|
||||
@ -1,25 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
OUTPUT_FORMAT("elf64-alpha")
|
||||
ENTRY(__start)
|
||||
printk = srm_printk;
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x20000000;
|
||||
.text : { *(.text) }
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata : { *(.rodata) *(.rodata.*) }
|
||||
.data : { *(.data) CONSTRUCTORS }
|
||||
.got : { *(.got) }
|
||||
.sdata : { *(.sdata) }
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
.sbss : { *(.sbss) *(.scommon) }
|
||||
.bss : { *(.bss) *(COMMON) }
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
|
||||
.mdebug 0 : { *(.mdebug) }
|
||||
.note 0 : { *(.note) }
|
||||
.comment 0 : { *(.comment) }
|
||||
}
|
||||
@ -1,214 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/alpha/boot/bootp.c
|
||||
*
|
||||
* Copyright (C) 1997 Jay Estabrook
|
||||
*
|
||||
* This file is used for creating a bootp file for the Linux/AXP kernel
|
||||
*
|
||||
* based significantly on the arch/alpha/boot/main.c of Linus Torvalds
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
#include <generated/utsrelease.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/console.h>
|
||||
#include <asm/hwrpb.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "ksize.h"
|
||||
|
||||
extern unsigned long switch_to_osf_pal(unsigned long nr,
|
||||
struct pcb_struct *pcb_va, struct pcb_struct *pcb_pa,
|
||||
unsigned long *vptb);
|
||||
|
||||
extern void move_stack(unsigned long new_stack);
|
||||
|
||||
struct hwrpb_struct *hwrpb = INIT_HWRPB;
|
||||
static struct pcb_struct pcb_va[1];
|
||||
|
||||
/*
|
||||
* Find a physical address of a virtual object..
|
||||
*
|
||||
* This is easy using the virtual page table address.
|
||||
*/
|
||||
|
||||
static inline void *
|
||||
find_pa(unsigned long *vptb, void *ptr)
|
||||
{
|
||||
unsigned long address = (unsigned long) ptr;
|
||||
unsigned long result;
|
||||
|
||||
result = vptb[address >> 13];
|
||||
result >>= 32;
|
||||
result <<= 13;
|
||||
result |= address & 0x1fff;
|
||||
return (void *) result;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function moves into OSF/1 pal-code, and has a temporary
|
||||
* PCB for that. The kernel proper should replace this PCB with
|
||||
* the real one as soon as possible.
|
||||
*
|
||||
* The page table muckery in here depends on the fact that the boot
|
||||
* code has the L1 page table identity-map itself in the second PTE
|
||||
* in the L1 page table. Thus the L1-page is virtually addressable
|
||||
* itself (through three levels) at virtual address 0x200802000.
|
||||
*/
|
||||
|
||||
#define VPTB ((unsigned long *) 0x200000000)
|
||||
#define L1 ((unsigned long *) 0x200802000)
|
||||
|
||||
void
|
||||
pal_init(void)
|
||||
{
|
||||
unsigned long i, rev;
|
||||
struct percpu_struct * percpu;
|
||||
struct pcb_struct * pcb_pa;
|
||||
|
||||
/* Create the dummy PCB. */
|
||||
pcb_va->ksp = 0;
|
||||
pcb_va->usp = 0;
|
||||
pcb_va->ptbr = L1[1] >> 32;
|
||||
pcb_va->asn = 0;
|
||||
pcb_va->pcc = 0;
|
||||
pcb_va->unique = 0;
|
||||
pcb_va->flags = 1;
|
||||
pcb_va->res1 = 0;
|
||||
pcb_va->res2 = 0;
|
||||
pcb_pa = find_pa(VPTB, pcb_va);
|
||||
|
||||
/*
|
||||
* a0 = 2 (OSF)
|
||||
* a1 = return address, but we give the asm the vaddr of the PCB
|
||||
* a2 = physical addr of PCB
|
||||
* a3 = new virtual page table pointer
|
||||
* a4 = KSP (but the asm sets it)
|
||||
*/
|
||||
srm_printk("Switching to OSF PAL-code .. ");
|
||||
|
||||
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
|
||||
if (i) {
|
||||
srm_printk("failed, code %ld\n", i);
|
||||
__halt();
|
||||
}
|
||||
|
||||
percpu = (struct percpu_struct *)
|
||||
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
|
||||
rev = percpu->pal_revision = percpu->palcode_avail[2];
|
||||
|
||||
srm_printk("Ok (rev %lx)\n", rev);
|
||||
|
||||
tbia(); /* do it directly in case we are SMP */
|
||||
}
|
||||
|
||||
static inline void
|
||||
load(unsigned long dst, unsigned long src, unsigned long count)
|
||||
{
|
||||
memcpy((void *)dst, (void *)src, count);
|
||||
}
|
||||
|
||||
/*
|
||||
* Start the kernel.
|
||||
*/
|
||||
static inline void
|
||||
runkernel(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"bis %0,%0,$27\n\t"
|
||||
"jmp ($27)"
|
||||
: /* no outputs: it doesn't even return */
|
||||
: "r" (START_ADDR));
|
||||
}
|
||||
|
||||
extern char _end;
|
||||
#define KERNEL_ORIGIN \
|
||||
((((unsigned long)&_end) + 511) & ~511)
|
||||
|
||||
void
|
||||
start_kernel(void)
|
||||
{
|
||||
/*
|
||||
* Note that this crufty stuff with static and envval
|
||||
* and envbuf is because:
|
||||
*
|
||||
* 1. Frequently, the stack is short, and we don't want to overrun;
|
||||
* 2. Frequently the stack is where we are going to copy the kernel to;
|
||||
* 3. A certain SRM console required the GET_ENV output to stack.
|
||||
* ??? A comment in the aboot sources indicates that the GET_ENV
|
||||
* destination must be quadword aligned. Might this explain the
|
||||
* behaviour, rather than requiring output to the stack, which
|
||||
* seems rather far-fetched.
|
||||
*/
|
||||
static long nbytes;
|
||||
static char envval[256] __attribute__((aligned(8)));
|
||||
static unsigned long initrd_start;
|
||||
|
||||
srm_printk("Linux/AXP bootp loader for Linux " UTS_RELEASE "\n");
|
||||
if (INIT_HWRPB->pagesize != 8192) {
|
||||
srm_printk("Expected 8kB pages, got %ldkB\n",
|
||||
INIT_HWRPB->pagesize >> 10);
|
||||
return;
|
||||
}
|
||||
if (INIT_HWRPB->vptb != (unsigned long) VPTB) {
|
||||
srm_printk("Expected vptb at %p, got %p\n",
|
||||
VPTB, (void *)INIT_HWRPB->vptb);
|
||||
return;
|
||||
}
|
||||
pal_init();
|
||||
|
||||
/* The initrd must be page-aligned. See below for the
|
||||
cause of the magic number 5. */
|
||||
initrd_start = ((START_ADDR + 5*KERNEL_SIZE + PAGE_SIZE) |
|
||||
(PAGE_SIZE-1)) + 1;
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
srm_printk("Initrd positioned at %#lx\n", initrd_start);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Move the stack to a safe place to ensure it won't be
|
||||
* overwritten by kernel image.
|
||||
*/
|
||||
move_stack(initrd_start - PAGE_SIZE);
|
||||
|
||||
nbytes = callback_getenv(ENV_BOOTED_OSFLAGS, envval, sizeof(envval));
|
||||
if (nbytes < 0 || nbytes >= sizeof(envval)) {
|
||||
nbytes = 0;
|
||||
}
|
||||
envval[nbytes] = '\0';
|
||||
srm_printk("Loading the kernel...'%s'\n", envval);
|
||||
|
||||
/* NOTE: *no* callbacks or printouts from here on out!!! */
|
||||
|
||||
/* This is a hack, as some consoles seem to get virtual 20000000 (ie
|
||||
* where the SRM console puts the kernel bootp image) memory
|
||||
* overlapping physical memory where the kernel wants to be put,
|
||||
* which causes real problems when attempting to copy the former to
|
||||
* the latter... :-(
|
||||
*
|
||||
* So, we first move the kernel virtual-to-physical way above where
|
||||
* we physically want the kernel to end up, then copy it from there
|
||||
* to its final resting place... ;-}
|
||||
*
|
||||
* Sigh... */
|
||||
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
load(initrd_start, KERNEL_ORIGIN+KERNEL_SIZE, INITRD_IMAGE_SIZE);
|
||||
#endif
|
||||
load(START_ADDR+(4*KERNEL_SIZE), KERNEL_ORIGIN, KERNEL_SIZE);
|
||||
load(START_ADDR, START_ADDR+(4*KERNEL_SIZE), KERNEL_SIZE);
|
||||
|
||||
memset((char*)ZERO_PGE, 0, PAGE_SIZE);
|
||||
strcpy((char*)ZERO_PGE, envval);
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
((long *)(ZERO_PGE+256))[0] = initrd_start;
|
||||
((long *)(ZERO_PGE+256))[1] = INITRD_IMAGE_SIZE;
|
||||
#endif
|
||||
|
||||
runkernel();
|
||||
}
|
||||
@ -1,475 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/alpha/boot/bootpz.c
|
||||
*
|
||||
* Copyright (C) 1997 Jay Estabrook
|
||||
*
|
||||
* This file is used for creating a compressed BOOTP file for the
|
||||
* Linux/AXP kernel
|
||||
*
|
||||
* based significantly on the arch/alpha/boot/main.c of Linus Torvalds
|
||||
* and the decompression code from MILO.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
#include <generated/utsrelease.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/console.h>
|
||||
#include <asm/hwrpb.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "kzsize.h"
|
||||
|
||||
/* FIXME FIXME FIXME */
|
||||
#define MALLOC_AREA_SIZE 0x200000 /* 2MB for now */
|
||||
/* FIXME FIXME FIXME */
|
||||
|
||||
|
||||
/*
|
||||
WARNING NOTE
|
||||
|
||||
It is very possible that turning on additional messages may cause
|
||||
kernel image corruption due to stack usage to do the printing.
|
||||
|
||||
*/
|
||||
|
||||
#undef DEBUG_CHECK_RANGE
|
||||
#undef DEBUG_ADDRESSES
|
||||
#undef DEBUG_LAST_STEPS
|
||||
|
||||
extern unsigned long switch_to_osf_pal(unsigned long nr,
|
||||
struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa,
|
||||
unsigned long *vptb);
|
||||
|
||||
extern int decompress_kernel(void* destination, void *source,
|
||||
size_t ksize, size_t kzsize);
|
||||
|
||||
extern void move_stack(unsigned long new_stack);
|
||||
|
||||
struct hwrpb_struct *hwrpb = INIT_HWRPB;
|
||||
static struct pcb_struct pcb_va[1];
|
||||
|
||||
/*
|
||||
* Find a physical address of a virtual object..
|
||||
*
|
||||
* This is easy using the virtual page table address.
|
||||
*/
|
||||
#define VPTB ((unsigned long *) 0x200000000)
|
||||
|
||||
static inline unsigned long
|
||||
find_pa(unsigned long address)
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
result = VPTB[address >> 13];
|
||||
result >>= 32;
|
||||
result <<= 13;
|
||||
result |= address & 0x1fff;
|
||||
return result;
|
||||
}
|
||||
|
||||
int
|
||||
check_range(unsigned long vstart, unsigned long vend,
|
||||
unsigned long kstart, unsigned long kend)
|
||||
{
|
||||
unsigned long vaddr, kaddr;
|
||||
|
||||
#ifdef DEBUG_CHECK_RANGE
|
||||
srm_printk("check_range: V[0x%lx:0x%lx] K[0x%lx:0x%lx]\n",
|
||||
vstart, vend, kstart, kend);
|
||||
#endif
|
||||
/* do some range checking for detecting an overlap... */
|
||||
for (vaddr = vstart; vaddr <= vend; vaddr += PAGE_SIZE)
|
||||
{
|
||||
kaddr = (find_pa(vaddr) | PAGE_OFFSET);
|
||||
if (kaddr >= kstart && kaddr <= kend)
|
||||
{
|
||||
#ifdef DEBUG_CHECK_RANGE
|
||||
srm_printk("OVERLAP: vaddr 0x%lx kaddr 0x%lx"
|
||||
" [0x%lx:0x%lx]\n",
|
||||
vaddr, kaddr, kstart, kend);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function moves into OSF/1 pal-code, and has a temporary
|
||||
* PCB for that. The kernel proper should replace this PCB with
|
||||
* the real one as soon as possible.
|
||||
*
|
||||
* The page table muckery in here depends on the fact that the boot
|
||||
* code has the L1 page table identity-map itself in the second PTE
|
||||
* in the L1 page table. Thus the L1-page is virtually addressable
|
||||
* itself (through three levels) at virtual address 0x200802000.
|
||||
*/
|
||||
|
||||
#define L1 ((unsigned long *) 0x200802000)
|
||||
|
||||
void
|
||||
pal_init(void)
|
||||
{
|
||||
unsigned long i, rev;
|
||||
struct percpu_struct * percpu;
|
||||
struct pcb_struct * pcb_pa;
|
||||
|
||||
/* Create the dummy PCB. */
|
||||
pcb_va->ksp = 0;
|
||||
pcb_va->usp = 0;
|
||||
pcb_va->ptbr = L1[1] >> 32;
|
||||
pcb_va->asn = 0;
|
||||
pcb_va->pcc = 0;
|
||||
pcb_va->unique = 0;
|
||||
pcb_va->flags = 1;
|
||||
pcb_va->res1 = 0;
|
||||
pcb_va->res2 = 0;
|
||||
pcb_pa = (struct pcb_struct *)find_pa((unsigned long)pcb_va);
|
||||
|
||||
/*
|
||||
* a0 = 2 (OSF)
|
||||
* a1 = return address, but we give the asm the vaddr of the PCB
|
||||
* a2 = physical addr of PCB
|
||||
* a3 = new virtual page table pointer
|
||||
* a4 = KSP (but the asm sets it)
|
||||
*/
|
||||
srm_printk("Switching to OSF PAL-code... ");
|
||||
|
||||
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
|
||||
if (i) {
|
||||
srm_printk("failed, code %ld\n", i);
|
||||
__halt();
|
||||
}
|
||||
|
||||
percpu = (struct percpu_struct *)
|
||||
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
|
||||
rev = percpu->pal_revision = percpu->palcode_avail[2];
|
||||
|
||||
srm_printk("OK (rev %lx)\n", rev);
|
||||
|
||||
tbia(); /* do it directly in case we are SMP */
|
||||
}
|
||||
|
||||
/*
|
||||
* Start the kernel.
|
||||
*/
|
||||
static inline void
|
||||
runkernel(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"bis %0,%0,$27\n\t"
|
||||
"jmp ($27)"
|
||||
: /* no outputs: it doesn't even return */
|
||||
: "r" (START_ADDR));
|
||||
}
|
||||
|
||||
/* Must record the SP (it is virtual) on entry, so we can make sure
|
||||
not to overwrite it during movement or decompression. */
|
||||
unsigned long SP_on_entry;
|
||||
|
||||
/* Calculate the kernel image address based on the end of the BOOTP
|
||||
bootstrapper (ie this program).
|
||||
*/
|
||||
extern char _end;
|
||||
#define KERNEL_ORIGIN \
|
||||
((((unsigned long)&_end) + 511) & ~511)
|
||||
|
||||
/* Round address to next higher page boundary. */
|
||||
#define NEXT_PAGE(a) (((a) | (PAGE_SIZE - 1)) + 1)
|
||||
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
# define REAL_INITRD_SIZE INITRD_IMAGE_SIZE
|
||||
#else
|
||||
# define REAL_INITRD_SIZE 0
|
||||
#endif
|
||||
|
||||
/* Defines from include/asm-alpha/system.h
|
||||
|
||||
BOOT_ADDR Virtual address at which the consoles loads
|
||||
the BOOTP image.
|
||||
|
||||
KERNEL_START KSEG address at which the kernel is built to run,
|
||||
which includes some initial data pages before the
|
||||
code.
|
||||
|
||||
START_ADDR KSEG address of the entry point of kernel code.
|
||||
|
||||
ZERO_PGE KSEG address of page full of zeroes, but
|
||||
upon entry to kernel, it can be expected
|
||||
to hold the parameter list and possible
|
||||
INTRD information.
|
||||
|
||||
These are used in the local defines below.
|
||||
*/
|
||||
|
||||
|
||||
/* Virtual addresses for the BOOTP image. Note that this includes the
|
||||
bootstrapper code as well as the compressed kernel image, and
|
||||
possibly the INITRD image.
|
||||
|
||||
Oh, and do NOT forget the STACK, which appears to be placed virtually
|
||||
beyond the end of the loaded image.
|
||||
*/
|
||||
#define V_BOOT_IMAGE_START BOOT_ADDR
|
||||
#define V_BOOT_IMAGE_END SP_on_entry
|
||||
|
||||
/* Virtual addresses for just the bootstrapper part of the BOOTP image. */
|
||||
#define V_BOOTSTRAPPER_START BOOT_ADDR
|
||||
#define V_BOOTSTRAPPER_END KERNEL_ORIGIN
|
||||
|
||||
/* Virtual addresses for just the data part of the BOOTP
|
||||
image. This may also include the INITRD image, but always
|
||||
includes the STACK.
|
||||
*/
|
||||
#define V_DATA_START KERNEL_ORIGIN
|
||||
#define V_INITRD_START (KERNEL_ORIGIN + KERNEL_Z_SIZE)
|
||||
#define V_INTRD_END (V_INITRD_START + REAL_INITRD_SIZE)
|
||||
#define V_DATA_END V_BOOT_IMAGE_END
|
||||
|
||||
/* KSEG addresses for the uncompressed kernel.
|
||||
|
||||
Note that the end address includes workspace for the decompression.
|
||||
Note also that the DATA_START address is ZERO_PGE, to which we write
|
||||
just before jumping to the kernel image at START_ADDR.
|
||||
*/
|
||||
#define K_KERNEL_DATA_START ZERO_PGE
|
||||
#define K_KERNEL_IMAGE_START START_ADDR
|
||||
#define K_KERNEL_IMAGE_END (START_ADDR + KERNEL_SIZE)
|
||||
|
||||
/* Define to where we may have to decompress the kernel image, before
|
||||
we move it to the final position, in case of overlap. This will be
|
||||
above the final position of the kernel.
|
||||
|
||||
Regardless of overlap, we move the INITRD image to the end of this
|
||||
copy area, because there needs to be a buffer area after the kernel
|
||||
for "bootmem" anyway.
|
||||
*/
|
||||
#define K_COPY_IMAGE_START NEXT_PAGE(K_KERNEL_IMAGE_END)
|
||||
/* Reserve one page below INITRD for the new stack. */
|
||||
#define K_INITRD_START \
|
||||
NEXT_PAGE(K_COPY_IMAGE_START + KERNEL_SIZE + PAGE_SIZE)
|
||||
#define K_COPY_IMAGE_END \
|
||||
(K_INITRD_START + REAL_INITRD_SIZE + MALLOC_AREA_SIZE)
|
||||
#define K_COPY_IMAGE_SIZE \
|
||||
NEXT_PAGE(K_COPY_IMAGE_END - K_COPY_IMAGE_START)
|
||||
|
||||
void
|
||||
start_kernel(void)
|
||||
{
|
||||
int must_move = 0;
|
||||
|
||||
/* Initialize these for the decompression-in-place situation,
|
||||
which is the smallest amount of work and most likely to
|
||||
occur when using the normal START_ADDR of the kernel
|
||||
(currently set to 16MB, to clear all console code.
|
||||
*/
|
||||
unsigned long uncompressed_image_start = K_KERNEL_IMAGE_START;
|
||||
unsigned long uncompressed_image_end = K_KERNEL_IMAGE_END;
|
||||
|
||||
unsigned long initrd_image_start = K_INITRD_START;
|
||||
|
||||
/*
|
||||
* Note that this crufty stuff with static and envval
|
||||
* and envbuf is because:
|
||||
*
|
||||
* 1. Frequently, the stack is short, and we don't want to overrun;
|
||||
* 2. Frequently the stack is where we are going to copy the kernel to;
|
||||
* 3. A certain SRM console required the GET_ENV output to stack.
|
||||
* ??? A comment in the aboot sources indicates that the GET_ENV
|
||||
* destination must be quadword aligned. Might this explain the
|
||||
* behaviour, rather than requiring output to the stack, which
|
||||
* seems rather far-fetched.
|
||||
*/
|
||||
static long nbytes;
|
||||
static char envval[256] __attribute__((aligned(8)));
|
||||
register unsigned long asm_sp asm("30");
|
||||
|
||||
SP_on_entry = asm_sp;
|
||||
|
||||
srm_printk("Linux/Alpha BOOTPZ Loader for Linux " UTS_RELEASE "\n");
|
||||
|
||||
/* Validity check the HWRPB. */
|
||||
if (INIT_HWRPB->pagesize != 8192) {
|
||||
srm_printk("Expected 8kB pages, got %ldkB\n",
|
||||
INIT_HWRPB->pagesize >> 10);
|
||||
return;
|
||||
}
|
||||
if (INIT_HWRPB->vptb != (unsigned long) VPTB) {
|
||||
srm_printk("Expected vptb at %p, got %p\n",
|
||||
VPTB, (void *)INIT_HWRPB->vptb);
|
||||
return;
|
||||
}
|
||||
|
||||
/* PALcode (re)initialization. */
|
||||
pal_init();
|
||||
|
||||
/* Get the parameter list from the console environment variable. */
|
||||
nbytes = callback_getenv(ENV_BOOTED_OSFLAGS, envval, sizeof(envval));
|
||||
if (nbytes < 0 || nbytes >= sizeof(envval)) {
|
||||
nbytes = 0;
|
||||
}
|
||||
envval[nbytes] = '\0';
|
||||
|
||||
#ifdef DEBUG_ADDRESSES
|
||||
srm_printk("START_ADDR 0x%lx\n", START_ADDR);
|
||||
srm_printk("KERNEL_ORIGIN 0x%lx\n", KERNEL_ORIGIN);
|
||||
srm_printk("KERNEL_SIZE 0x%x\n", KERNEL_SIZE);
|
||||
srm_printk("KERNEL_Z_SIZE 0x%x\n", KERNEL_Z_SIZE);
|
||||
#endif
|
||||
|
||||
/* Since all the SRM consoles load the BOOTP image at virtual
|
||||
* 0x20000000, we have to ensure that the physical memory
|
||||
* pages occupied by that image do NOT overlap the physical
|
||||
* address range where the kernel wants to be run. This
|
||||
* causes real problems when attempting to cdecompress the
|
||||
* former into the latter... :-(
|
||||
*
|
||||
* So, we may have to decompress/move the kernel/INITRD image
|
||||
* virtual-to-physical someplace else first before moving
|
||||
* kernel /INITRD to their final resting places... ;-}
|
||||
*
|
||||
* Sigh...
|
||||
*/
|
||||
|
||||
/* First, check to see if the range of addresses occupied by
|
||||
the bootstrapper part of the BOOTP image include any of the
|
||||
physical pages into which the kernel will be placed for
|
||||
execution.
|
||||
|
||||
We only need check on the final kernel image range, since we
|
||||
will put the INITRD someplace that we can be sure is not
|
||||
in conflict.
|
||||
*/
|
||||
if (check_range(V_BOOTSTRAPPER_START, V_BOOTSTRAPPER_END,
|
||||
K_KERNEL_DATA_START, K_KERNEL_IMAGE_END))
|
||||
{
|
||||
srm_printk("FATAL ERROR: overlap of bootstrapper code\n");
|
||||
__halt();
|
||||
}
|
||||
|
||||
/* Next, check to see if the range of addresses occupied by
|
||||
the compressed kernel/INITRD/stack portion of the BOOTP
|
||||
image include any of the physical pages into which the
|
||||
decompressed kernel or the INITRD will be placed for
|
||||
execution.
|
||||
*/
|
||||
if (check_range(V_DATA_START, V_DATA_END,
|
||||
K_KERNEL_IMAGE_START, K_COPY_IMAGE_END))
|
||||
{
|
||||
#ifdef DEBUG_ADDRESSES
|
||||
srm_printk("OVERLAP: cannot decompress in place\n");
|
||||
#endif
|
||||
uncompressed_image_start = K_COPY_IMAGE_START;
|
||||
uncompressed_image_end = K_COPY_IMAGE_END;
|
||||
must_move = 1;
|
||||
|
||||
/* Finally, check to see if the range of addresses
|
||||
occupied by the compressed kernel/INITRD part of
|
||||
the BOOTP image include any of the physical pages
|
||||
into which that part is to be copied for
|
||||
decompression.
|
||||
*/
|
||||
while (check_range(V_DATA_START, V_DATA_END,
|
||||
uncompressed_image_start,
|
||||
uncompressed_image_end))
|
||||
{
|
||||
#if 0
|
||||
uncompressed_image_start += K_COPY_IMAGE_SIZE;
|
||||
uncompressed_image_end += K_COPY_IMAGE_SIZE;
|
||||
initrd_image_start += K_COPY_IMAGE_SIZE;
|
||||
#else
|
||||
/* Keep as close as possible to end of BOOTP image. */
|
||||
uncompressed_image_start += PAGE_SIZE;
|
||||
uncompressed_image_end += PAGE_SIZE;
|
||||
initrd_image_start += PAGE_SIZE;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
srm_printk("Starting to load the kernel with args '%s'\n", envval);
|
||||
|
||||
#ifdef DEBUG_ADDRESSES
|
||||
srm_printk("Decompressing the kernel...\n"
|
||||
"...from 0x%lx to 0x%lx size 0x%x\n",
|
||||
V_DATA_START,
|
||||
uncompressed_image_start,
|
||||
KERNEL_SIZE);
|
||||
#endif
|
||||
decompress_kernel((void *)uncompressed_image_start,
|
||||
(void *)V_DATA_START,
|
||||
KERNEL_SIZE, KERNEL_Z_SIZE);
|
||||
|
||||
/*
|
||||
* Now, move things to their final positions, if/as required.
|
||||
*/
|
||||
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
|
||||
/* First, we always move the INITRD image, if present. */
|
||||
#ifdef DEBUG_ADDRESSES
|
||||
srm_printk("Moving the INITRD image...\n"
|
||||
" from 0x%lx to 0x%lx size 0x%x\n",
|
||||
V_INITRD_START,
|
||||
initrd_image_start,
|
||||
INITRD_IMAGE_SIZE);
|
||||
#endif
|
||||
memcpy((void *)initrd_image_start, (void *)V_INITRD_START,
|
||||
INITRD_IMAGE_SIZE);
|
||||
|
||||
#endif /* INITRD_IMAGE_SIZE */
|
||||
|
||||
/* Next, we may have to move the uncompressed kernel to the
|
||||
final destination.
|
||||
*/
|
||||
if (must_move) {
|
||||
#ifdef DEBUG_ADDRESSES
|
||||
srm_printk("Moving the uncompressed kernel...\n"
|
||||
"...from 0x%lx to 0x%lx size 0x%x\n",
|
||||
uncompressed_image_start,
|
||||
K_KERNEL_IMAGE_START,
|
||||
(unsigned)KERNEL_SIZE);
|
||||
#endif
|
||||
/*
|
||||
* Move the stack to a safe place to ensure it won't be
|
||||
* overwritten by kernel image.
|
||||
*/
|
||||
move_stack(initrd_image_start - PAGE_SIZE);
|
||||
|
||||
memcpy((void *)K_KERNEL_IMAGE_START,
|
||||
(void *)uncompressed_image_start, KERNEL_SIZE);
|
||||
}
|
||||
|
||||
/* Clear the zero page, then move the argument list in. */
|
||||
#ifdef DEBUG_LAST_STEPS
|
||||
srm_printk("Preparing ZERO_PGE...\n");
|
||||
#endif
|
||||
memset((char*)ZERO_PGE, 0, PAGE_SIZE);
|
||||
strcpy((char*)ZERO_PGE, envval);
|
||||
|
||||
#ifdef INITRD_IMAGE_SIZE
|
||||
|
||||
#ifdef DEBUG_LAST_STEPS
|
||||
srm_printk("Preparing INITRD info...\n");
|
||||
#endif
|
||||
/* Finally, set the INITRD paramenters for the kernel. */
|
||||
((long *)(ZERO_PGE+256))[0] = initrd_image_start;
|
||||
((long *)(ZERO_PGE+256))[1] = INITRD_IMAGE_SIZE;
|
||||
|
||||
#endif /* INITRD_IMAGE_SIZE */
|
||||
|
||||
#ifdef DEBUG_LAST_STEPS
|
||||
srm_printk("Doing 'runkernel()'...\n");
|
||||
#endif
|
||||
runkernel();
|
||||
}
|
||||
|
||||
/* dummy function, should never be called. */
|
||||
void *__kmalloc(size_t size, gfp_t flags)
|
||||
{
|
||||
return (void *)NULL;
|
||||
}
|
||||
@ -1,124 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* arch/alpha/boot/head.S
|
||||
*
|
||||
* initial bootloader stuff..
|
||||
*/
|
||||
|
||||
#include <asm/pal.h>
|
||||
|
||||
.set noreorder
|
||||
.globl __start
|
||||
.ent __start
|
||||
__start:
|
||||
br $29,2f
|
||||
2: ldgp $29,0($29)
|
||||
jsr $26,start_kernel
|
||||
call_pal PAL_halt
|
||||
.end __start
|
||||
|
||||
.align 5
|
||||
.globl wrent
|
||||
.ent wrent
|
||||
wrent:
|
||||
.prologue 0
|
||||
call_pal PAL_wrent
|
||||
ret ($26)
|
||||
.end wrent
|
||||
|
||||
.align 5
|
||||
.globl wrkgp
|
||||
.ent wrkgp
|
||||
wrkgp:
|
||||
.prologue 0
|
||||
call_pal PAL_wrkgp
|
||||
ret ($26)
|
||||
.end wrkgp
|
||||
|
||||
.align 5
|
||||
.globl switch_to_osf_pal
|
||||
.ent switch_to_osf_pal
|
||||
switch_to_osf_pal:
|
||||
subq $30,128,$30
|
||||
.frame $30,128,$26
|
||||
stq $26,0($30)
|
||||
stq $1,8($30)
|
||||
stq $2,16($30)
|
||||
stq $3,24($30)
|
||||
stq $4,32($30)
|
||||
stq $5,40($30)
|
||||
stq $6,48($30)
|
||||
stq $7,56($30)
|
||||
stq $8,64($30)
|
||||
stq $9,72($30)
|
||||
stq $10,80($30)
|
||||
stq $11,88($30)
|
||||
stq $12,96($30)
|
||||
stq $13,104($30)
|
||||
stq $14,112($30)
|
||||
stq $15,120($30)
|
||||
.prologue 0
|
||||
|
||||
stq $30,0($17) /* save KSP in PCB */
|
||||
|
||||
bis $30,$30,$20 /* a4 = KSP */
|
||||
br $17,1f
|
||||
|
||||
ldq $26,0($30)
|
||||
ldq $1,8($30)
|
||||
ldq $2,16($30)
|
||||
ldq $3,24($30)
|
||||
ldq $4,32($30)
|
||||
ldq $5,40($30)
|
||||
ldq $6,48($30)
|
||||
ldq $7,56($30)
|
||||
ldq $8,64($30)
|
||||
ldq $9,72($30)
|
||||
ldq $10,80($30)
|
||||
ldq $11,88($30)
|
||||
ldq $12,96($30)
|
||||
ldq $13,104($30)
|
||||
ldq $14,112($30)
|
||||
ldq $15,120($30)
|
||||
addq $30,128,$30
|
||||
ret ($26)
|
||||
1: call_pal PAL_swppal
|
||||
.end switch_to_osf_pal
|
||||
|
||||
.align 3
|
||||
.globl tbi
|
||||
.ent tbi
|
||||
tbi:
|
||||
.prologue 0
|
||||
call_pal PAL_tbi
|
||||
ret ($26)
|
||||
.end tbi
|
||||
|
||||
.align 3
|
||||
.globl halt
|
||||
.ent halt
|
||||
halt:
|
||||
.prologue 0
|
||||
call_pal PAL_halt
|
||||
.end halt
|
||||
|
||||
/* $16 - new stack page */
|
||||
.align 3
|
||||
.globl move_stack
|
||||
.ent move_stack
|
||||
move_stack:
|
||||
.prologue 0
|
||||
lda $0, 0x1fff($31)
|
||||
and $0, $30, $1 /* Stack offset */
|
||||
or $1, $16, $16 /* New stack pointer */
|
||||
mov $30, $1
|
||||
mov $16, $2
|
||||
1: ldq $3, 0($1) /* Move the stack */
|
||||
addq $1, 8, $1
|
||||
stq $3, 0($2)
|
||||
and $0, $1, $4
|
||||
addq $2, 8, $2
|
||||
bne $4, 1b
|
||||
mov $16, $30
|
||||
ret ($26)
|
||||
.end move_stack
|
||||
@ -1,190 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/alpha/boot/main.c
|
||||
*
|
||||
* Copyright (C) 1994, 1995 Linus Torvalds
|
||||
*
|
||||
* This file is the bootloader for the Linux/AXP kernel
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
#include <generated/utsrelease.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/console.h>
|
||||
#include <asm/hwrpb.h>
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "ksize.h"
|
||||
|
||||
extern unsigned long switch_to_osf_pal(unsigned long nr,
|
||||
struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa,
|
||||
unsigned long *vptb);
|
||||
struct hwrpb_struct *hwrpb = INIT_HWRPB;
|
||||
static struct pcb_struct pcb_va[1];
|
||||
|
||||
/*
|
||||
* Find a physical address of a virtual object..
|
||||
*
|
||||
* This is easy using the virtual page table address.
|
||||
*/
|
||||
|
||||
static inline void *
|
||||
find_pa(unsigned long *vptb, void *ptr)
|
||||
{
|
||||
unsigned long address = (unsigned long) ptr;
|
||||
unsigned long result;
|
||||
|
||||
result = vptb[address >> 13];
|
||||
result >>= 32;
|
||||
result <<= 13;
|
||||
result |= address & 0x1fff;
|
||||
return (void *) result;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function moves into OSF/1 pal-code, and has a temporary
|
||||
* PCB for that. The kernel proper should replace this PCB with
|
||||
* the real one as soon as possible.
|
||||
*
|
||||
* The page table muckery in here depends on the fact that the boot
|
||||
* code has the L1 page table identity-map itself in the second PTE
|
||||
* in the L1 page table. Thus the L1-page is virtually addressable
|
||||
* itself (through three levels) at virtual address 0x200802000.
|
||||
*/
|
||||
|
||||
#define VPTB ((unsigned long *) 0x200000000)
|
||||
#define L1 ((unsigned long *) 0x200802000)
|
||||
|
||||
void
|
||||
pal_init(void)
|
||||
{
|
||||
unsigned long i, rev;
|
||||
struct percpu_struct * percpu;
|
||||
struct pcb_struct * pcb_pa;
|
||||
|
||||
/* Create the dummy PCB. */
|
||||
pcb_va->ksp = 0;
|
||||
pcb_va->usp = 0;
|
||||
pcb_va->ptbr = L1[1] >> 32;
|
||||
pcb_va->asn = 0;
|
||||
pcb_va->pcc = 0;
|
||||
pcb_va->unique = 0;
|
||||
pcb_va->flags = 1;
|
||||
pcb_va->res1 = 0;
|
||||
pcb_va->res2 = 0;
|
||||
pcb_pa = find_pa(VPTB, pcb_va);
|
||||
|
||||
/*
|
||||
* a0 = 2 (OSF)
|
||||
* a1 = return address, but we give the asm the vaddr of the PCB
|
||||
* a2 = physical addr of PCB
|
||||
* a3 = new virtual page table pointer
|
||||
* a4 = KSP (but the asm sets it)
|
||||
*/
|
||||
srm_printk("Switching to OSF PAL-code .. ");
|
||||
|
||||
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
|
||||
if (i) {
|
||||
srm_printk("failed, code %ld\n", i);
|
||||
__halt();
|
||||
}
|
||||
|
||||
percpu = (struct percpu_struct *)
|
||||
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
|
||||
rev = percpu->pal_revision = percpu->palcode_avail[2];
|
||||
|
||||
srm_printk("Ok (rev %lx)\n", rev);
|
||||
|
||||
tbia(); /* do it directly in case we are SMP */
|
||||
}
|
||||
|
||||
static inline long openboot(void)
|
||||
{
|
||||
char bootdev[256];
|
||||
long result;
|
||||
|
||||
result = callback_getenv(ENV_BOOTED_DEV, bootdev, 255);
|
||||
if (result < 0)
|
||||
return result;
|
||||
return callback_open(bootdev, result & 255);
|
||||
}
|
||||
|
||||
static inline long close(long dev)
|
||||
{
|
||||
return callback_close(dev);
|
||||
}
|
||||
|
||||
static inline long load(long dev, unsigned long addr, unsigned long count)
|
||||
{
|
||||
char bootfile[256];
|
||||
extern char _end;
|
||||
long result, boot_size = &_end - (char *) BOOT_ADDR;
|
||||
|
||||
result = callback_getenv(ENV_BOOTED_FILE, bootfile, 255);
|
||||
if (result < 0)
|
||||
return result;
|
||||
result &= 255;
|
||||
bootfile[result] = '\0';
|
||||
if (result)
|
||||
srm_printk("Boot file specification (%s) not implemented\n",
|
||||
bootfile);
|
||||
return callback_read(dev, count, (void *)addr, boot_size/512 + 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Start the kernel.
|
||||
*/
|
||||
static void runkernel(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"bis %1,%1,$30\n\t"
|
||||
"bis %0,%0,$26\n\t"
|
||||
"ret ($26)"
|
||||
: /* no outputs: it doesn't even return */
|
||||
: "r" (START_ADDR),
|
||||
"r" (PAGE_SIZE + INIT_STACK));
|
||||
}
|
||||
|
||||
void start_kernel(void)
|
||||
{
|
||||
long i;
|
||||
long dev;
|
||||
int nbytes;
|
||||
char envval[256];
|
||||
|
||||
srm_printk("Linux/AXP bootloader for Linux " UTS_RELEASE "\n");
|
||||
if (INIT_HWRPB->pagesize != 8192) {
|
||||
srm_printk("Expected 8kB pages, got %ldkB\n", INIT_HWRPB->pagesize >> 10);
|
||||
return;
|
||||
}
|
||||
pal_init();
|
||||
dev = openboot();
|
||||
if (dev < 0) {
|
||||
srm_printk("Unable to open boot device: %016lx\n", dev);
|
||||
return;
|
||||
}
|
||||
dev &= 0xffffffff;
|
||||
srm_printk("Loading vmlinux ...");
|
||||
i = load(dev, START_ADDR, KERNEL_SIZE);
|
||||
close(dev);
|
||||
if (i != KERNEL_SIZE) {
|
||||
srm_printk("Failed (%lx)\n", i);
|
||||
return;
|
||||
}
|
||||
|
||||
nbytes = callback_getenv(ENV_BOOTED_OSFLAGS, envval, sizeof(envval));
|
||||
if (nbytes < 0) {
|
||||
nbytes = 0;
|
||||
}
|
||||
envval[nbytes] = '\0';
|
||||
strcpy((char*)ZERO_PGE, envval);
|
||||
|
||||
srm_printk(" Ok\nNow booting the kernel\n");
|
||||
runkernel();
|
||||
for (i = 0 ; i < 0x100000000 ; i++)
|
||||
/* nothing */;
|
||||
__halt();
|
||||
}
|
||||
@ -1,174 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* misc.c
|
||||
*
|
||||
* This is a collection of several routines from gzip-1.0.3
|
||||
* adapted for Linux.
|
||||
*
|
||||
* malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
|
||||
*
|
||||
* Modified for ARM Linux by Russell King
|
||||
*
|
||||
* Nicolas Pitre <nico@visuaide.com> 1999/04/14 :
|
||||
* For this code to run directly from Flash, all constant variables must
|
||||
* be marked with 'const' and all other variables initialized at run-time
|
||||
* only. This way all non constant variables will end up in the bss segment,
|
||||
* which should point to addresses in RAM and cleared to 0 on start.
|
||||
* This allows for a much quicker boot time.
|
||||
*
|
||||
* Modified for Alpha, from the ARM version, by Jay Estabrook 2003.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#define memzero(s,n) memset ((s),0,(n))
|
||||
#define puts srm_printk
|
||||
extern long srm_printk(const char *, ...)
|
||||
__attribute__ ((format (printf, 1, 2)));
|
||||
|
||||
/*
|
||||
* gzip declarations
|
||||
*/
|
||||
#define OF(args) args
|
||||
#define STATIC static
|
||||
|
||||
typedef unsigned char uch;
|
||||
typedef unsigned short ush;
|
||||
typedef unsigned long ulg;
|
||||
|
||||
#define WSIZE 0x8000 /* Window size must be at least 32k, */
|
||||
/* and a power of two */
|
||||
|
||||
static uch *inbuf; /* input buffer */
|
||||
static uch *window; /* Sliding window buffer */
|
||||
|
||||
static unsigned insize; /* valid bytes in inbuf */
|
||||
static unsigned inptr; /* index of next byte to be processed in inbuf */
|
||||
static unsigned outcnt; /* bytes in output buffer */
|
||||
|
||||
/* gzip flag byte */
|
||||
#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */
|
||||
#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
|
||||
#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
|
||||
#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
|
||||
#define COMMENT 0x10 /* bit 4 set: file comment present */
|
||||
#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
|
||||
#define RESERVED 0xC0 /* bit 6,7: reserved */
|
||||
|
||||
#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
|
||||
|
||||
/* Diagnostic functions */
|
||||
#ifdef DEBUG
|
||||
# define Assert(cond,msg) {if(!(cond)) error(msg);}
|
||||
# define Trace(x) fprintf x
|
||||
# define Tracev(x) {if (verbose) fprintf x ;}
|
||||
# define Tracevv(x) {if (verbose>1) fprintf x ;}
|
||||
# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
|
||||
# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
|
||||
#else
|
||||
# define Assert(cond,msg)
|
||||
# define Trace(x)
|
||||
# define Tracev(x)
|
||||
# define Tracevv(x)
|
||||
# define Tracec(c,x)
|
||||
# define Tracecv(c,x)
|
||||
#endif
|
||||
|
||||
static int fill_inbuf(void);
|
||||
static void flush_window(void);
|
||||
static void error(char *m);
|
||||
|
||||
static char *input_data;
|
||||
static int input_data_size;
|
||||
|
||||
static uch *output_data;
|
||||
static ulg output_ptr;
|
||||
static ulg bytes_out;
|
||||
|
||||
static void error(char *m);
|
||||
static void gzip_mark(void **);
|
||||
static void gzip_release(void **);
|
||||
|
||||
extern int end;
|
||||
static ulg free_mem_ptr;
|
||||
static ulg free_mem_end_ptr;
|
||||
|
||||
#define HEAP_SIZE 0x3000
|
||||
|
||||
#include "../../../lib/inflate.c"
|
||||
|
||||
/* ===========================================================================
|
||||
* Fill the input buffer. This is called only when the buffer is empty
|
||||
* and at least one byte is really needed.
|
||||
*/
|
||||
int fill_inbuf(void)
|
||||
{
|
||||
if (insize != 0)
|
||||
error("ran out of input data");
|
||||
|
||||
inbuf = input_data;
|
||||
insize = input_data_size;
|
||||
|
||||
inptr = 1;
|
||||
return inbuf[0];
|
||||
}
|
||||
|
||||
/* ===========================================================================
|
||||
* Write the output window window[0..outcnt-1] and update crc and bytes_out.
|
||||
* (Used for the decompressed data only.)
|
||||
*/
|
||||
void flush_window(void)
|
||||
{
|
||||
ulg c = crc;
|
||||
unsigned n;
|
||||
uch *in, *out, ch;
|
||||
|
||||
in = window;
|
||||
out = &output_data[output_ptr];
|
||||
for (n = 0; n < outcnt; n++) {
|
||||
ch = *out++ = *in++;
|
||||
c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
|
||||
}
|
||||
crc = c;
|
||||
bytes_out += (ulg)outcnt;
|
||||
output_ptr += (ulg)outcnt;
|
||||
outcnt = 0;
|
||||
/* puts("."); */
|
||||
}
|
||||
|
||||
static void error(char *x)
|
||||
{
|
||||
puts("\n\n");
|
||||
puts(x);
|
||||
puts("\n\n -- System halted");
|
||||
|
||||
while(1); /* Halt */
|
||||
}
|
||||
|
||||
unsigned int
|
||||
decompress_kernel(void *output_start,
|
||||
void *input_start,
|
||||
size_t ksize,
|
||||
size_t kzsize)
|
||||
{
|
||||
output_data = (uch *)output_start;
|
||||
input_data = (uch *)input_start;
|
||||
input_data_size = kzsize; /* use compressed size */
|
||||
|
||||
/* FIXME FIXME FIXME */
|
||||
free_mem_ptr = (ulg)output_start + ksize;
|
||||
free_mem_end_ptr = (ulg)output_start + ksize + 0x200000;
|
||||
/* FIXME FIXME FIXME */
|
||||
|
||||
/* put in temp area to reduce initial footprint */
|
||||
window = malloc(WSIZE);
|
||||
|
||||
makecrc();
|
||||
/* puts("Uncompressing Linux..."); */
|
||||
gunzip();
|
||||
/* puts(" done, booting the kernel.\n"); */
|
||||
return output_ptr;
|
||||
}
|
||||
@ -1,302 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) Paul Mackerras 1997.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
|
||||
size_t strnlen(const char * s, size_t count)
|
||||
{
|
||||
const char *sc;
|
||||
|
||||
for (sc = s; count-- && *sc != '\0'; ++sc)
|
||||
/* nothing */;
|
||||
return sc - s;
|
||||
}
|
||||
|
||||
# define do_div(n, base) ({ \
|
||||
unsigned int __base = (base); \
|
||||
unsigned int __rem; \
|
||||
__rem = ((unsigned long long)(n)) % __base; \
|
||||
(n) = ((unsigned long long)(n)) / __base; \
|
||||
__rem; \
|
||||
})
|
||||
|
||||
|
||||
static int skip_atoi(const char **s)
|
||||
{
|
||||
int i, c;
|
||||
|
||||
for (i = 0; '0' <= (c = **s) && c <= '9'; ++*s)
|
||||
i = i*10 + c - '0';
|
||||
return i;
|
||||
}
|
||||
|
||||
#define ZEROPAD 1 /* pad with zero */
|
||||
#define SIGN 2 /* unsigned/signed long */
|
||||
#define PLUS 4 /* show plus */
|
||||
#define SPACE 8 /* space if plus */
|
||||
#define LEFT 16 /* left justified */
|
||||
#define SPECIAL 32 /* 0x */
|
||||
#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */
|
||||
|
||||
static char * number(char * str, unsigned long long num, int base, int size, int precision, int type)
|
||||
{
|
||||
char c,sign,tmp[66];
|
||||
const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
|
||||
int i;
|
||||
|
||||
if (type & LARGE)
|
||||
digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
|
||||
if (type & LEFT)
|
||||
type &= ~ZEROPAD;
|
||||
if (base < 2 || base > 36)
|
||||
return 0;
|
||||
c = (type & ZEROPAD) ? '0' : ' ';
|
||||
sign = 0;
|
||||
if (type & SIGN) {
|
||||
if ((signed long long)num < 0) {
|
||||
sign = '-';
|
||||
num = - (signed long long)num;
|
||||
size--;
|
||||
} else if (type & PLUS) {
|
||||
sign = '+';
|
||||
size--;
|
||||
} else if (type & SPACE) {
|
||||
sign = ' ';
|
||||
size--;
|
||||
}
|
||||
}
|
||||
if (type & SPECIAL) {
|
||||
if (base == 16)
|
||||
size -= 2;
|
||||
else if (base == 8)
|
||||
size--;
|
||||
}
|
||||
i = 0;
|
||||
if (num == 0)
|
||||
tmp[i++]='0';
|
||||
else while (num != 0) {
|
||||
tmp[i++] = digits[do_div(num, base)];
|
||||
}
|
||||
if (i > precision)
|
||||
precision = i;
|
||||
size -= precision;
|
||||
if (!(type&(ZEROPAD+LEFT)))
|
||||
while(size-->0)
|
||||
*str++ = ' ';
|
||||
if (sign)
|
||||
*str++ = sign;
|
||||
if (type & SPECIAL) {
|
||||
if (base==8)
|
||||
*str++ = '0';
|
||||
else if (base==16) {
|
||||
*str++ = '0';
|
||||
*str++ = digits[33];
|
||||
}
|
||||
}
|
||||
if (!(type & LEFT))
|
||||
while (size-- > 0)
|
||||
*str++ = c;
|
||||
while (i < precision--)
|
||||
*str++ = '0';
|
||||
while (i-- > 0)
|
||||
*str++ = tmp[i];
|
||||
while (size-- > 0)
|
||||
*str++ = ' ';
|
||||
return str;
|
||||
}
|
||||
|
||||
int vsprintf(char *buf, const char *fmt, va_list args)
|
||||
{
|
||||
int len;
|
||||
unsigned long long num;
|
||||
int i, base;
|
||||
char * str;
|
||||
const char *s;
|
||||
|
||||
int flags; /* flags to number() */
|
||||
|
||||
int field_width; /* width of output field */
|
||||
int precision; /* min. # of digits for integers; max
|
||||
number of chars for from string */
|
||||
int qualifier; /* 'h', 'l', or 'L' for integer fields */
|
||||
/* 'z' support added 23/7/1999 S.H. */
|
||||
/* 'z' changed to 'Z' --davidm 1/25/99 */
|
||||
|
||||
|
||||
for (str=buf ; *fmt ; ++fmt) {
|
||||
if (*fmt != '%') {
|
||||
*str++ = *fmt;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* process flags */
|
||||
flags = 0;
|
||||
repeat:
|
||||
++fmt; /* this also skips first '%' */
|
||||
switch (*fmt) {
|
||||
case '-': flags |= LEFT; goto repeat;
|
||||
case '+': flags |= PLUS; goto repeat;
|
||||
case ' ': flags |= SPACE; goto repeat;
|
||||
case '#': flags |= SPECIAL; goto repeat;
|
||||
case '0': flags |= ZEROPAD; goto repeat;
|
||||
}
|
||||
|
||||
/* get field width */
|
||||
field_width = -1;
|
||||
if ('0' <= *fmt && *fmt <= '9')
|
||||
field_width = skip_atoi(&fmt);
|
||||
else if (*fmt == '*') {
|
||||
++fmt;
|
||||
/* it's the next argument */
|
||||
field_width = va_arg(args, int);
|
||||
if (field_width < 0) {
|
||||
field_width = -field_width;
|
||||
flags |= LEFT;
|
||||
}
|
||||
}
|
||||
|
||||
/* get the precision */
|
||||
precision = -1;
|
||||
if (*fmt == '.') {
|
||||
++fmt;
|
||||
if ('0' <= *fmt && *fmt <= '9')
|
||||
precision = skip_atoi(&fmt);
|
||||
else if (*fmt == '*') {
|
||||
++fmt;
|
||||
/* it's the next argument */
|
||||
precision = va_arg(args, int);
|
||||
}
|
||||
if (precision < 0)
|
||||
precision = 0;
|
||||
}
|
||||
|
||||
/* get the conversion qualifier */
|
||||
qualifier = -1;
|
||||
if (*fmt == 'l' && *(fmt + 1) == 'l') {
|
||||
qualifier = 'q';
|
||||
fmt += 2;
|
||||
} else if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L'
|
||||
|| *fmt == 'Z') {
|
||||
qualifier = *fmt;
|
||||
++fmt;
|
||||
}
|
||||
|
||||
/* default base */
|
||||
base = 10;
|
||||
|
||||
switch (*fmt) {
|
||||
case 'c':
|
||||
if (!(flags & LEFT))
|
||||
while (--field_width > 0)
|
||||
*str++ = ' ';
|
||||
*str++ = (unsigned char) va_arg(args, int);
|
||||
while (--field_width > 0)
|
||||
*str++ = ' ';
|
||||
continue;
|
||||
|
||||
case 's':
|
||||
s = va_arg(args, char *);
|
||||
if (!s)
|
||||
s = "<NULL>";
|
||||
|
||||
len = strnlen(s, precision);
|
||||
|
||||
if (!(flags & LEFT))
|
||||
while (len < field_width--)
|
||||
*str++ = ' ';
|
||||
for (i = 0; i < len; ++i)
|
||||
*str++ = *s++;
|
||||
while (len < field_width--)
|
||||
*str++ = ' ';
|
||||
continue;
|
||||
|
||||
case 'p':
|
||||
if (field_width == -1) {
|
||||
field_width = 2*sizeof(void *);
|
||||
flags |= ZEROPAD;
|
||||
}
|
||||
str = number(str,
|
||||
(unsigned long) va_arg(args, void *), 16,
|
||||
field_width, precision, flags);
|
||||
continue;
|
||||
|
||||
|
||||
case 'n':
|
||||
if (qualifier == 'l') {
|
||||
long * ip = va_arg(args, long *);
|
||||
*ip = (str - buf);
|
||||
} else if (qualifier == 'Z') {
|
||||
size_t * ip = va_arg(args, size_t *);
|
||||
*ip = (str - buf);
|
||||
} else {
|
||||
int * ip = va_arg(args, int *);
|
||||
*ip = (str - buf);
|
||||
}
|
||||
continue;
|
||||
|
||||
case '%':
|
||||
*str++ = '%';
|
||||
continue;
|
||||
|
||||
/* integer number formats - set up the flags and "break" */
|
||||
case 'o':
|
||||
base = 8;
|
||||
break;
|
||||
|
||||
case 'X':
|
||||
flags |= LARGE;
|
||||
case 'x':
|
||||
base = 16;
|
||||
break;
|
||||
|
||||
case 'd':
|
||||
case 'i':
|
||||
flags |= SIGN;
|
||||
case 'u':
|
||||
break;
|
||||
|
||||
default:
|
||||
*str++ = '%';
|
||||
if (*fmt)
|
||||
*str++ = *fmt;
|
||||
else
|
||||
--fmt;
|
||||
continue;
|
||||
}
|
||||
if (qualifier == 'l') {
|
||||
num = va_arg(args, unsigned long);
|
||||
if (flags & SIGN)
|
||||
num = (signed long) num;
|
||||
} else if (qualifier == 'q') {
|
||||
num = va_arg(args, unsigned long long);
|
||||
if (flags & SIGN)
|
||||
num = (signed long long) num;
|
||||
} else if (qualifier == 'Z') {
|
||||
num = va_arg(args, size_t);
|
||||
} else if (qualifier == 'h') {
|
||||
num = (unsigned short) va_arg(args, int);
|
||||
if (flags & SIGN)
|
||||
num = (signed short) num;
|
||||
} else {
|
||||
num = va_arg(args, unsigned int);
|
||||
if (flags & SIGN)
|
||||
num = (signed int) num;
|
||||
}
|
||||
str = number(str, num, base, field_width, precision, flags);
|
||||
}
|
||||
*str = '\0';
|
||||
return str-buf;
|
||||
}
|
||||
|
||||
int sprintf(char * buf, const char *fmt, ...)
|
||||
{
|
||||
va_list args;
|
||||
int i;
|
||||
|
||||
va_start(args, fmt);
|
||||
i=vsprintf(buf,fmt,args);
|
||||
va_end(args);
|
||||
return i;
|
||||
}
|
||||
@ -1,153 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* This utility makes a bootblock suitable for the SRM console/miniloader */
|
||||
|
||||
/* Usage:
|
||||
* mkbb <device> <lxboot>
|
||||
*
|
||||
* Where <device> is the name of the device to install the bootblock on,
|
||||
* and <lxboot> is the name of a bootblock to merge in. This bootblock
|
||||
* contains the offset and size of the bootloader. It must be exactly
|
||||
* 512 bytes long.
|
||||
*/
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <unistd.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
/* Minimal definition of disklabel, so we don't have to include
|
||||
* asm/disklabel.h (confuses make)
|
||||
*/
|
||||
#ifndef MAXPARTITIONS
|
||||
#define MAXPARTITIONS 8 /* max. # of partitions */
|
||||
#endif
|
||||
|
||||
#ifndef u8
|
||||
#define u8 unsigned char
|
||||
#endif
|
||||
|
||||
#ifndef u16
|
||||
#define u16 unsigned short
|
||||
#endif
|
||||
|
||||
#ifndef u32
|
||||
#define u32 unsigned int
|
||||
#endif
|
||||
|
||||
struct disklabel {
|
||||
u32 d_magic; /* must be DISKLABELMAGIC */
|
||||
u16 d_type, d_subtype;
|
||||
u8 d_typename[16];
|
||||
u8 d_packname[16];
|
||||
u32 d_secsize;
|
||||
u32 d_nsectors;
|
||||
u32 d_ntracks;
|
||||
u32 d_ncylinders;
|
||||
u32 d_secpercyl;
|
||||
u32 d_secprtunit;
|
||||
u16 d_sparespertrack;
|
||||
u16 d_sparespercyl;
|
||||
u32 d_acylinders;
|
||||
u16 d_rpm, d_interleave, d_trackskew, d_cylskew;
|
||||
u32 d_headswitch, d_trkseek, d_flags;
|
||||
u32 d_drivedata[5];
|
||||
u32 d_spare[5];
|
||||
u32 d_magic2; /* must be DISKLABELMAGIC */
|
||||
u16 d_checksum;
|
||||
u16 d_npartitions;
|
||||
u32 d_bbsize, d_sbsize;
|
||||
struct d_partition {
|
||||
u32 p_size;
|
||||
u32 p_offset;
|
||||
u32 p_fsize;
|
||||
u8 p_fstype;
|
||||
u8 p_frag;
|
||||
u16 p_cpg;
|
||||
} d_partitions[MAXPARTITIONS];
|
||||
};
|
||||
|
||||
|
||||
typedef union __bootblock {
|
||||
struct {
|
||||
char __pad1[64];
|
||||
struct disklabel __label;
|
||||
} __u1;
|
||||
struct {
|
||||
unsigned long __pad2[63];
|
||||
unsigned long __checksum;
|
||||
} __u2;
|
||||
char bootblock_bytes[512];
|
||||
unsigned long bootblock_quadwords[64];
|
||||
} bootblock;
|
||||
|
||||
#define bootblock_label __u1.__label
|
||||
#define bootblock_checksum __u2.__checksum
|
||||
|
||||
int main(int argc, char ** argv)
|
||||
{
|
||||
bootblock bootblock_from_disk;
|
||||
bootblock bootloader_image;
|
||||
int dev, fd;
|
||||
int i;
|
||||
int nread;
|
||||
|
||||
/* Make sure of the arg count */
|
||||
if(argc != 3) {
|
||||
fprintf(stderr, "Usage: %s device lxboot\n", argv[0]);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
/* First, open the device and make sure it's accessible */
|
||||
dev = open(argv[1], O_RDWR);
|
||||
if(dev < 0) {
|
||||
perror(argv[1]);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
/* Now open the lxboot and make sure it's reasonable */
|
||||
fd = open(argv[2], O_RDONLY);
|
||||
if(fd < 0) {
|
||||
perror(argv[2]);
|
||||
close(dev);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
/* Read in the lxboot */
|
||||
nread = read(fd, &bootloader_image, sizeof(bootblock));
|
||||
if(nread != sizeof(bootblock)) {
|
||||
perror("lxboot read");
|
||||
fprintf(stderr, "expected %zd, got %d\n", sizeof(bootblock), nread);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
/* Read in the bootblock from disk. */
|
||||
nread = read(dev, &bootblock_from_disk, sizeof(bootblock));
|
||||
if(nread != sizeof(bootblock)) {
|
||||
perror("bootblock read");
|
||||
fprintf(stderr, "expected %zd, got %d\n", sizeof(bootblock), nread);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
/* Swap the bootblock's disklabel into the bootloader */
|
||||
bootloader_image.bootblock_label = bootblock_from_disk.bootblock_label;
|
||||
|
||||
/* Calculate the bootblock checksum */
|
||||
bootloader_image.bootblock_checksum = 0;
|
||||
for(i = 0; i < 63; i++) {
|
||||
bootloader_image.bootblock_checksum +=
|
||||
bootloader_image.bootblock_quadwords[i];
|
||||
}
|
||||
|
||||
/* Write the whole thing out! */
|
||||
lseek(dev, 0L, SEEK_SET);
|
||||
if(write(dev, &bootloader_image, sizeof(bootblock)) != sizeof(bootblock)) {
|
||||
perror("bootblock write");
|
||||
exit(0);
|
||||
}
|
||||
|
||||
close(fd);
|
||||
close(dev);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
||||
@ -1,284 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/alpha/boot/tools/objstrip.c
|
||||
*
|
||||
* Strip the object file headers/trailers from an executable (ELF or ECOFF).
|
||||
*
|
||||
* Copyright (C) 1996 David Mosberger-Tang.
|
||||
*/
|
||||
/*
|
||||
* Converts an ECOFF or ELF object file into a bootable file. The
|
||||
* object file must be a OMAGIC file (i.e., data and bss follow immediately
|
||||
* behind the text). See DEC "Assembly Language Programmer's Guide"
|
||||
* documentation for details. The SRM boot process is documented in
|
||||
* the Alpha AXP Architecture Reference Manual, Second Edition by
|
||||
* Richard L. Sites and Richard T. Witek.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <sys/fcntl.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <linux/a.out.h>
|
||||
#include <linux/coff.h>
|
||||
#include <linux/param.h>
|
||||
#ifdef __ELF__
|
||||
# include <linux/elf.h>
|
||||
# define elfhdr elf64_hdr
|
||||
# define elf_phdr elf64_phdr
|
||||
# define elf_check_arch(x) ((x)->e_machine == EM_ALPHA)
|
||||
#endif
|
||||
|
||||
/* bootfile size must be multiple of BLOCK_SIZE: */
|
||||
#define BLOCK_SIZE 512
|
||||
|
||||
const char * prog_name;
|
||||
|
||||
|
||||
static void
|
||||
usage (void)
|
||||
{
|
||||
fprintf(stderr,
|
||||
"usage: %s [-v] -p file primary\n"
|
||||
" %s [-vb] file [secondary]\n", prog_name, prog_name);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
main (int argc, char *argv[])
|
||||
{
|
||||
size_t nwritten, tocopy, n, mem_size, fil_size, pad = 0;
|
||||
int fd, ofd, i, j, verbose = 0, primary = 0;
|
||||
char buf[8192], *inname;
|
||||
struct exec * aout; /* includes file & aout header */
|
||||
long offset;
|
||||
#ifdef __ELF__
|
||||
struct elfhdr *elf;
|
||||
struct elf_phdr *elf_phdr; /* program header */
|
||||
unsigned long long e_entry;
|
||||
#endif
|
||||
|
||||
prog_name = argv[0];
|
||||
|
||||
for (i = 1; i < argc && argv[i][0] == '-'; ++i) {
|
||||
for (j = 1; argv[i][j]; ++j) {
|
||||
switch (argv[i][j]) {
|
||||
case 'v':
|
||||
verbose = ~verbose;
|
||||
break;
|
||||
|
||||
case 'b':
|
||||
pad = BLOCK_SIZE;
|
||||
break;
|
||||
|
||||
case 'p':
|
||||
primary = 1; /* make primary bootblock */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= argc) {
|
||||
usage();
|
||||
}
|
||||
inname = argv[i++];
|
||||
|
||||
fd = open(inname, O_RDONLY);
|
||||
if (fd == -1) {
|
||||
perror("open");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
ofd = 1;
|
||||
if (i < argc) {
|
||||
ofd = open(argv[i++], O_WRONLY | O_CREAT | O_TRUNC, 0666);
|
||||
if (ofd == -1) {
|
||||
perror("open");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
if (primary) {
|
||||
/* generate bootblock for primary loader */
|
||||
|
||||
unsigned long bb[64], sum = 0;
|
||||
struct stat st;
|
||||
off_t size;
|
||||
int i;
|
||||
|
||||
if (ofd == 1) {
|
||||
usage();
|
||||
}
|
||||
|
||||
if (fstat(fd, &st) == -1) {
|
||||
perror("fstat");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
size = (st.st_size + BLOCK_SIZE - 1) & ~(BLOCK_SIZE - 1);
|
||||
memset(bb, 0, sizeof(bb));
|
||||
strcpy((char *) bb, "Linux SRM bootblock");
|
||||
bb[60] = size / BLOCK_SIZE; /* count */
|
||||
bb[61] = 1; /* starting sector # */
|
||||
bb[62] = 0; /* flags---must be 0 */
|
||||
for (i = 0; i < 63; ++i) {
|
||||
sum += bb[i];
|
||||
}
|
||||
bb[63] = sum;
|
||||
if (write(ofd, bb, sizeof(bb)) != sizeof(bb)) {
|
||||
perror("boot-block write");
|
||||
exit(1);
|
||||
}
|
||||
printf("%lu\n", size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* read and inspect exec header: */
|
||||
|
||||
if (read(fd, buf, sizeof(buf)) < 0) {
|
||||
perror("read");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
#ifdef __ELF__
|
||||
elf = (struct elfhdr *) buf;
|
||||
|
||||
if (elf->e_ident[0] == 0x7f && str_has_prefix((char *)elf->e_ident + 1, "ELF")) {
|
||||
if (elf->e_type != ET_EXEC) {
|
||||
fprintf(stderr, "%s: %s is not an ELF executable\n",
|
||||
prog_name, inname);
|
||||
exit(1);
|
||||
}
|
||||
if (!elf_check_arch(elf)) {
|
||||
fprintf(stderr, "%s: is not for this processor (e_machine=%d)\n",
|
||||
prog_name, elf->e_machine);
|
||||
exit(1);
|
||||
}
|
||||
if (elf->e_phnum != 1) {
|
||||
fprintf(stderr,
|
||||
"%s: %d program headers (forgot to link with -N?)\n",
|
||||
prog_name, elf->e_phnum);
|
||||
}
|
||||
|
||||
e_entry = elf->e_entry;
|
||||
|
||||
lseek(fd, elf->e_phoff, SEEK_SET);
|
||||
if (read(fd, buf, sizeof(*elf_phdr)) != sizeof(*elf_phdr)) {
|
||||
perror("read");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
elf_phdr = (struct elf_phdr *) buf;
|
||||
offset = elf_phdr->p_offset;
|
||||
mem_size = elf_phdr->p_memsz;
|
||||
fil_size = elf_phdr->p_filesz;
|
||||
|
||||
/* work around ELF bug: */
|
||||
if (elf_phdr->p_vaddr < e_entry) {
|
||||
unsigned long delta = e_entry - elf_phdr->p_vaddr;
|
||||
offset += delta;
|
||||
mem_size -= delta;
|
||||
fil_size -= delta;
|
||||
elf_phdr->p_vaddr += delta;
|
||||
}
|
||||
|
||||
if (verbose) {
|
||||
fprintf(stderr, "%s: extracting %#016lx-%#016lx (at %lx)\n",
|
||||
prog_name, (long) elf_phdr->p_vaddr,
|
||||
elf_phdr->p_vaddr + fil_size, offset);
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
aout = (struct exec *) buf;
|
||||
|
||||
if (!(aout->fh.f_flags & COFF_F_EXEC)) {
|
||||
fprintf(stderr, "%s: %s is not in executable format\n",
|
||||
prog_name, inname);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (aout->fh.f_opthdr != sizeof(aout->ah)) {
|
||||
fprintf(stderr, "%s: %s has unexpected optional header size\n",
|
||||
prog_name, inname);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (N_MAGIC(*aout) != OMAGIC) {
|
||||
fprintf(stderr, "%s: %s is not an OMAGIC file\n",
|
||||
prog_name, inname);
|
||||
exit(1);
|
||||
}
|
||||
offset = N_TXTOFF(*aout);
|
||||
fil_size = aout->ah.tsize + aout->ah.dsize;
|
||||
mem_size = fil_size + aout->ah.bsize;
|
||||
|
||||
if (verbose) {
|
||||
fprintf(stderr, "%s: extracting %#016lx-%#016lx (at %lx)\n",
|
||||
prog_name, aout->ah.text_start,
|
||||
aout->ah.text_start + fil_size, offset);
|
||||
}
|
||||
}
|
||||
|
||||
if (lseek(fd, offset, SEEK_SET) != offset) {
|
||||
perror("lseek");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (verbose) {
|
||||
fprintf(stderr, "%s: copying %lu byte from %s\n",
|
||||
prog_name, (unsigned long) fil_size, inname);
|
||||
}
|
||||
|
||||
tocopy = fil_size;
|
||||
while (tocopy > 0) {
|
||||
n = tocopy;
|
||||
if (n > sizeof(buf)) {
|
||||
n = sizeof(buf);
|
||||
}
|
||||
tocopy -= n;
|
||||
if ((size_t) read(fd, buf, n) != n) {
|
||||
perror("read");
|
||||
exit(1);
|
||||
}
|
||||
do {
|
||||
nwritten = write(ofd, buf, n);
|
||||
if ((ssize_t) nwritten == -1) {
|
||||
perror("write");
|
||||
exit(1);
|
||||
}
|
||||
n -= nwritten;
|
||||
} while (n > 0);
|
||||
}
|
||||
|
||||
if (pad) {
|
||||
mem_size = ((mem_size + pad - 1) / pad) * pad;
|
||||
}
|
||||
|
||||
tocopy = mem_size - fil_size;
|
||||
if (tocopy > 0) {
|
||||
fprintf(stderr,
|
||||
"%s: zero-filling bss and aligning to %lu with %lu bytes\n",
|
||||
prog_name, pad, (unsigned long) tocopy);
|
||||
|
||||
memset(buf, 0x00, sizeof(buf));
|
||||
do {
|
||||
n = tocopy;
|
||||
if (n > sizeof(buf)) {
|
||||
n = sizeof(buf);
|
||||
}
|
||||
nwritten = write(ofd, buf, n);
|
||||
if ((ssize_t) nwritten == -1) {
|
||||
perror("write");
|
||||
exit(1);
|
||||
}
|
||||
tocopy -= nwritten;
|
||||
} while (tocopy > 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -1,73 +0,0 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_VERBOSE_MCHECK=y
|
||||
CONFIG_SRM_ENV=m
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_PNP=y
|
||||
CONFIG_ISAPNP=y
|
||||
CONFIG_BLK_DEV_FD=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_SCSI_AIC7XXX=m
|
||||
CONFIG_AIC7XXX_CMDS_PER_DEVICE=253
|
||||
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
|
||||
CONFIG_ATA=y
|
||||
# CONFIG_SATA_PMP is not set
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_PATA_CMD64X=y
|
||||
CONFIG_PATA_CYPRESS=y
|
||||
CONFIG_ATA_GENERIC=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_VENDOR_3COM=y
|
||||
CONFIG_VORTEX=y
|
||||
CONFIG_NET_TULIP=y
|
||||
CONFIG_DE2104X=m
|
||||
CONFIG_TULIP=y
|
||||
CONFIG_TULIP_MMIO=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_YELLOWFIN=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_REISERFS_FS=m
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_NFSD_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_ALPHA_LEGACY_START_ADDRESS=y
|
||||
CONFIG_MATHEMU=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
generated-y += syscall_table.h
|
||||
generic-y += export.h
|
||||
generic-y += kvm_para.h
|
||||
generic-y += mcs_spinlock.h
|
||||
@ -1,16 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_A_OUT_H__
|
||||
#define __ALPHA_A_OUT_H__
|
||||
|
||||
#include <uapi/asm/a.out.h>
|
||||
|
||||
|
||||
/* Assume that start addresses below 4G belong to a TASO application.
|
||||
Unfortunately, there is no proper bit in the exec header to check.
|
||||
Worse, we have to notice the start address before swapping to use
|
||||
/sbin/loader, which of course is _not_ a TASO application. */
|
||||
#define SET_AOUT_PERSONALITY(BFPM, EX) \
|
||||
set_personality (((BFPM->taso || EX.ah.entry < 0x100000000L \
|
||||
? ADDR_LIMIT_32BIT : 0) | PER_OSF4))
|
||||
|
||||
#endif /* __A_OUT_GNU_H__ */
|
||||
@ -1,19 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef AGP_H
|
||||
#define AGP_H 1
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
/* dummy for now */
|
||||
|
||||
#define map_page_into_agp(page) do { } while (0)
|
||||
#define unmap_page_from_agp(page) do { } while (0)
|
||||
#define flush_agp_cache() mb()
|
||||
|
||||
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
|
||||
#define alloc_gatt_pages(order) \
|
||||
((char *)__get_free_pages(GFP_KERNEL, (order)))
|
||||
#define free_gatt_pages(table, order) \
|
||||
free_pages((unsigned long)(table), (order))
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_AGP_BACKEND_H
|
||||
#define _ALPHA_AGP_BACKEND_H 1
|
||||
|
||||
typedef union _alpha_agp_mode {
|
||||
struct {
|
||||
u32 rate : 3;
|
||||
u32 reserved0 : 1;
|
||||
u32 fw : 1;
|
||||
u32 fourgb : 1;
|
||||
u32 reserved1 : 2;
|
||||
u32 enable : 1;
|
||||
u32 sba : 1;
|
||||
u32 reserved2 : 14;
|
||||
u32 rq : 8;
|
||||
} bits;
|
||||
u32 lw;
|
||||
} alpha_agp_mode;
|
||||
|
||||
typedef struct _alpha_agp_info {
|
||||
struct pci_controller *hose;
|
||||
struct {
|
||||
dma_addr_t bus_base;
|
||||
unsigned long size;
|
||||
void *sysdata;
|
||||
} aperture;
|
||||
alpha_agp_mode capability;
|
||||
alpha_agp_mode mode;
|
||||
void *private;
|
||||
struct alpha_agp_ops *ops;
|
||||
} alpha_agp_info;
|
||||
|
||||
struct alpha_agp_ops {
|
||||
int (*setup)(alpha_agp_info *);
|
||||
void (*cleanup)(alpha_agp_info *);
|
||||
int (*configure)(alpha_agp_info *);
|
||||
int (*bind)(alpha_agp_info *, off_t, struct agp_memory *);
|
||||
int (*unbind)(alpha_agp_info *, off_t, struct agp_memory *);
|
||||
unsigned long (*translate)(alpha_agp_info *, dma_addr_t);
|
||||
};
|
||||
|
||||
|
||||
#endif /* _ALPHA_AGP_BACKEND_H */
|
||||
@ -1 +0,0 @@
|
||||
#include <generated/asm-offsets.h>
|
||||
@ -1,19 +0,0 @@
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/checksum.h>
|
||||
#include <asm/console.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/string.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm-generic/asm-prototypes.h>
|
||||
|
||||
extern void __divl(void);
|
||||
extern void __reml(void);
|
||||
extern void __divq(void);
|
||||
extern void __remq(void);
|
||||
extern void __divlu(void);
|
||||
extern void __remlu(void);
|
||||
extern void __divqu(void);
|
||||
extern void __remqu(void);
|
||||
extern unsigned long __udiv_qrnnd(unsigned long *, unsigned long, unsigned long , unsigned long);
|
||||
@ -1,306 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_ATOMIC_H
|
||||
#define _ALPHA_ATOMIC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/cmpxchg.h>
|
||||
|
||||
/*
|
||||
* Atomic operations that C can't guarantee us. Useful for
|
||||
* resource counting etc...
|
||||
*
|
||||
* But use these as seldom as possible since they are much slower
|
||||
* than regular operations.
|
||||
*/
|
||||
|
||||
/*
|
||||
* To ensure dependency ordering is preserved for the _relaxed and
|
||||
* _release atomics, an smp_mb() is unconditionally inserted into the
|
||||
* _relaxed variants, which are used to build the barriered versions.
|
||||
* Avoid redundant back-to-back fences in the _acquire and _fence
|
||||
* versions.
|
||||
*/
|
||||
#define __atomic_acquire_fence()
|
||||
#define __atomic_post_full_fence()
|
||||
|
||||
#define ATOMIC64_INIT(i) { (i) }
|
||||
|
||||
#define arch_atomic_read(v) READ_ONCE((v)->counter)
|
||||
#define arch_atomic64_read(v) READ_ONCE((v)->counter)
|
||||
|
||||
#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
|
||||
#define arch_atomic64_set(v,i) WRITE_ONCE((v)->counter, (i))
|
||||
|
||||
/*
|
||||
* To get proper branch prediction for the main line, we must branch
|
||||
* forward to code at the end of this object's .text section, then
|
||||
* branch back to restart the operation.
|
||||
*/
|
||||
|
||||
#define ATOMIC_OP(op, asm_op) \
|
||||
static __inline__ void arch_atomic_##op(int i, atomic_t * v) \
|
||||
{ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldl_l %0,%1\n" \
|
||||
" " #asm_op " %0,%2,%0\n" \
|
||||
" stl_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter) \
|
||||
:"Ir" (i), "m" (v->counter)); \
|
||||
} \
|
||||
|
||||
#define ATOMIC_OP_RETURN(op, asm_op) \
|
||||
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
|
||||
{ \
|
||||
long temp, result; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldl_l %0,%1\n" \
|
||||
" " #asm_op " %0,%3,%2\n" \
|
||||
" " #asm_op " %0,%3,%0\n" \
|
||||
" stl_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
|
||||
:"Ir" (i), "m" (v->counter) : "memory"); \
|
||||
smp_mb(); \
|
||||
return result; \
|
||||
}
|
||||
|
||||
#define ATOMIC_FETCH_OP(op, asm_op) \
|
||||
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
|
||||
{ \
|
||||
long temp, result; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldl_l %2,%1\n" \
|
||||
" " #asm_op " %2,%3,%0\n" \
|
||||
" stl_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
|
||||
:"Ir" (i), "m" (v->counter) : "memory"); \
|
||||
smp_mb(); \
|
||||
return result; \
|
||||
}
|
||||
|
||||
#define ATOMIC64_OP(op, asm_op) \
|
||||
static __inline__ void arch_atomic64_##op(s64 i, atomic64_t * v) \
|
||||
{ \
|
||||
s64 temp; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldq_l %0,%1\n" \
|
||||
" " #asm_op " %0,%2,%0\n" \
|
||||
" stq_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter) \
|
||||
:"Ir" (i), "m" (v->counter)); \
|
||||
} \
|
||||
|
||||
#define ATOMIC64_OP_RETURN(op, asm_op) \
|
||||
static __inline__ s64 \
|
||||
arch_atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
|
||||
{ \
|
||||
s64 temp, result; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldq_l %0,%1\n" \
|
||||
" " #asm_op " %0,%3,%2\n" \
|
||||
" " #asm_op " %0,%3,%0\n" \
|
||||
" stq_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
|
||||
:"Ir" (i), "m" (v->counter) : "memory"); \
|
||||
smp_mb(); \
|
||||
return result; \
|
||||
}
|
||||
|
||||
#define ATOMIC64_FETCH_OP(op, asm_op) \
|
||||
static __inline__ s64 \
|
||||
arch_atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
|
||||
{ \
|
||||
s64 temp, result; \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldq_l %2,%1\n" \
|
||||
" " #asm_op " %2,%3,%0\n" \
|
||||
" stq_c %0,%1\n" \
|
||||
" beq %0,2f\n" \
|
||||
".subsection 2\n" \
|
||||
"2: br 1b\n" \
|
||||
".previous" \
|
||||
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
|
||||
:"Ir" (i), "m" (v->counter) : "memory"); \
|
||||
smp_mb(); \
|
||||
return result; \
|
||||
}
|
||||
|
||||
#define ATOMIC_OPS(op) \
|
||||
ATOMIC_OP(op, op##l) \
|
||||
ATOMIC_OP_RETURN(op, op##l) \
|
||||
ATOMIC_FETCH_OP(op, op##l) \
|
||||
ATOMIC64_OP(op, op##q) \
|
||||
ATOMIC64_OP_RETURN(op, op##q) \
|
||||
ATOMIC64_FETCH_OP(op, op##q)
|
||||
|
||||
ATOMIC_OPS(add)
|
||||
ATOMIC_OPS(sub)
|
||||
|
||||
#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
|
||||
#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
|
||||
#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
|
||||
#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
|
||||
|
||||
#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
|
||||
#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
|
||||
#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
|
||||
#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
|
||||
|
||||
#define arch_atomic_andnot arch_atomic_andnot
|
||||
#define arch_atomic64_andnot arch_atomic64_andnot
|
||||
|
||||
#undef ATOMIC_OPS
|
||||
#define ATOMIC_OPS(op, asm) \
|
||||
ATOMIC_OP(op, asm) \
|
||||
ATOMIC_FETCH_OP(op, asm) \
|
||||
ATOMIC64_OP(op, asm) \
|
||||
ATOMIC64_FETCH_OP(op, asm)
|
||||
|
||||
ATOMIC_OPS(and, and)
|
||||
ATOMIC_OPS(andnot, bic)
|
||||
ATOMIC_OPS(or, bis)
|
||||
ATOMIC_OPS(xor, xor)
|
||||
|
||||
#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
|
||||
#define arch_atomic_fetch_andnot_relaxed arch_atomic_fetch_andnot_relaxed
|
||||
#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
|
||||
#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
|
||||
|
||||
#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
|
||||
#define arch_atomic64_fetch_andnot_relaxed arch_atomic64_fetch_andnot_relaxed
|
||||
#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
|
||||
#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
|
||||
|
||||
#undef ATOMIC_OPS
|
||||
#undef ATOMIC64_FETCH_OP
|
||||
#undef ATOMIC64_OP_RETURN
|
||||
#undef ATOMIC64_OP
|
||||
#undef ATOMIC_FETCH_OP
|
||||
#undef ATOMIC_OP_RETURN
|
||||
#undef ATOMIC_OP
|
||||
|
||||
#define arch_atomic64_cmpxchg(v, old, new) \
|
||||
(arch_cmpxchg(&((v)->counter), old, new))
|
||||
#define arch_atomic64_xchg(v, new) \
|
||||
(arch_xchg(&((v)->counter), new))
|
||||
|
||||
#define arch_atomic_cmpxchg(v, old, new) \
|
||||
(arch_cmpxchg(&((v)->counter), old, new))
|
||||
#define arch_atomic_xchg(v, new) \
|
||||
(arch_xchg(&((v)->counter), new))
|
||||
|
||||
/**
|
||||
* arch_atomic_fetch_add_unless - add unless the number is a given value
|
||||
* @v: pointer of type atomic_t
|
||||
* @a: the amount to add to v...
|
||||
* @u: ...unless v is equal to u.
|
||||
*
|
||||
* Atomically adds @a to @v, so long as it was not @u.
|
||||
* Returns the old value of @v.
|
||||
*/
|
||||
static __inline__ int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
|
||||
{
|
||||
int c, new, old;
|
||||
smp_mb();
|
||||
__asm__ __volatile__(
|
||||
"1: ldl_l %[old],%[mem]\n"
|
||||
" cmpeq %[old],%[u],%[c]\n"
|
||||
" addl %[old],%[a],%[new]\n"
|
||||
" bne %[c],2f\n"
|
||||
" stl_c %[new],%[mem]\n"
|
||||
" beq %[new],3f\n"
|
||||
"2:\n"
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
|
||||
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u)
|
||||
: "memory");
|
||||
smp_mb();
|
||||
return old;
|
||||
}
|
||||
#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
|
||||
|
||||
/**
|
||||
* arch_atomic64_fetch_add_unless - add unless the number is a given value
|
||||
* @v: pointer of type atomic64_t
|
||||
* @a: the amount to add to v...
|
||||
* @u: ...unless v is equal to u.
|
||||
*
|
||||
* Atomically adds @a to @v, so long as it was not @u.
|
||||
* Returns the old value of @v.
|
||||
*/
|
||||
static __inline__ s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
|
||||
{
|
||||
s64 c, new, old;
|
||||
smp_mb();
|
||||
__asm__ __volatile__(
|
||||
"1: ldq_l %[old],%[mem]\n"
|
||||
" cmpeq %[old],%[u],%[c]\n"
|
||||
" addq %[old],%[a],%[new]\n"
|
||||
" bne %[c],2f\n"
|
||||
" stq_c %[new],%[mem]\n"
|
||||
" beq %[new],3f\n"
|
||||
"2:\n"
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
|
||||
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u)
|
||||
: "memory");
|
||||
smp_mb();
|
||||
return old;
|
||||
}
|
||||
#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless
|
||||
|
||||
/*
|
||||
* arch_atomic64_dec_if_positive - decrement by 1 if old value positive
|
||||
* @v: pointer of type atomic_t
|
||||
*
|
||||
* The function returns the old value of *v minus 1, even if
|
||||
* the atomic variable, v, was not decremented.
|
||||
*/
|
||||
static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
|
||||
{
|
||||
s64 old, tmp;
|
||||
smp_mb();
|
||||
__asm__ __volatile__(
|
||||
"1: ldq_l %[old],%[mem]\n"
|
||||
" subq %[old],1,%[tmp]\n"
|
||||
" ble %[old],2f\n"
|
||||
" stq_c %[tmp],%[mem]\n"
|
||||
" beq %[tmp],3f\n"
|
||||
"2:\n"
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
: [old] "=&r"(old), [tmp] "=&r"(tmp)
|
||||
: [mem] "m"(*v)
|
||||
: "memory");
|
||||
smp_mb();
|
||||
return old - 1;
|
||||
}
|
||||
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
|
||||
|
||||
#endif /* _ALPHA_ATOMIC_H */
|
||||
@ -1,23 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __BARRIER_H
|
||||
#define __BARRIER_H
|
||||
|
||||
#define mb() __asm__ __volatile__("mb": : :"memory")
|
||||
#define rmb() __asm__ __volatile__("mb": : :"memory")
|
||||
#define wmb() __asm__ __volatile__("wmb": : :"memory")
|
||||
|
||||
#define __smp_load_acquire(p) \
|
||||
({ \
|
||||
compiletime_assert_atomic_type(*p); \
|
||||
__READ_ONCE(*p); \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define __ASM_SMP_MB "\tmb\n"
|
||||
#else
|
||||
#define __ASM_SMP_MB
|
||||
#endif
|
||||
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* __BARRIER_H */
|
||||
@ -1,459 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_BITOPS_H
|
||||
#define _ALPHA_BITOPS_H
|
||||
|
||||
#ifndef _LINUX_BITOPS_H
|
||||
#error only <linux/bitops.h> can be included directly
|
||||
#endif
|
||||
|
||||
#include <asm/compiler.h>
|
||||
#include <asm/barrier.h>
|
||||
|
||||
/*
|
||||
* Copyright 1994, Linus Torvalds.
|
||||
*/
|
||||
|
||||
/*
|
||||
* These have to be done with inline assembly: that way the bit-setting
|
||||
* is guaranteed to be atomic. All bit operations return 0 if the bit
|
||||
* was cleared before the operation and != 0 if it was not.
|
||||
*
|
||||
* To get proper branch prediction for the main line, we must branch
|
||||
* forward to code at the end of this object's .text section, then
|
||||
* branch back to restart the operation.
|
||||
*
|
||||
* bit 0 is the LSB of addr; bit 64 is the LSB of (addr+1).
|
||||
*/
|
||||
|
||||
static inline void
|
||||
set_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldl_l %0,%3\n"
|
||||
" bis %0,%2,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,2f\n"
|
||||
".subsection 2\n"
|
||||
"2: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m));
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static inline void
|
||||
__set_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
*m |= 1 << (nr & 31);
|
||||
}
|
||||
|
||||
static inline void
|
||||
clear_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldl_l %0,%3\n"
|
||||
" bic %0,%2,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,2f\n"
|
||||
".subsection 2\n"
|
||||
"2: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m));
|
||||
}
|
||||
|
||||
static inline void
|
||||
clear_bit_unlock(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
smp_mb();
|
||||
clear_bit(nr, addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static __inline__ void
|
||||
__clear_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
*m &= ~(1 << (nr & 31));
|
||||
}
|
||||
|
||||
static inline void
|
||||
__clear_bit_unlock(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
smp_mb();
|
||||
__clear_bit(nr, addr);
|
||||
}
|
||||
|
||||
static inline void
|
||||
change_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldl_l %0,%3\n"
|
||||
" xor %0,%2,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,2f\n"
|
||||
".subsection 2\n"
|
||||
"2: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m));
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static __inline__ void
|
||||
__change_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
*m ^= 1 << (nr & 31);
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_set_bit(unsigned long nr, volatile void *addr)
|
||||
{
|
||||
unsigned long oldbit;
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
"1: ldl_l %0,%4\n"
|
||||
" and %0,%3,%2\n"
|
||||
" bne %2,2f\n"
|
||||
" xor %0,%3,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,3f\n"
|
||||
"2:\n"
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
|
||||
|
||||
return oldbit != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_set_bit_lock(unsigned long nr, volatile void *addr)
|
||||
{
|
||||
unsigned long oldbit;
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldl_l %0,%4\n"
|
||||
" and %0,%3,%2\n"
|
||||
" bne %2,2f\n"
|
||||
" xor %0,%3,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,3f\n"
|
||||
"2:\n"
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
|
||||
|
||||
return oldbit != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static inline int
|
||||
__test_and_set_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long mask = 1 << (nr & 0x1f);
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
int old = *m;
|
||||
|
||||
*m = old | mask;
|
||||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_clear_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long oldbit;
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
"1: ldl_l %0,%4\n"
|
||||
" and %0,%3,%2\n"
|
||||
" beq %2,2f\n"
|
||||
" xor %0,%3,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,3f\n"
|
||||
"2:\n"
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
|
||||
|
||||
return oldbit != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static inline int
|
||||
__test_and_clear_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long mask = 1 << (nr & 0x1f);
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
int old = *m;
|
||||
|
||||
*m = old & ~mask;
|
||||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_and_change_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long oldbit;
|
||||
unsigned long temp;
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
|
||||
__asm__ __volatile__(
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
"1: ldl_l %0,%4\n"
|
||||
" and %0,%3,%2\n"
|
||||
" xor %0,%3,%0\n"
|
||||
" stl_c %0,%1\n"
|
||||
" beq %0,3f\n"
|
||||
#ifdef CONFIG_SMP
|
||||
" mb\n"
|
||||
#endif
|
||||
".subsection 2\n"
|
||||
"3: br 1b\n"
|
||||
".previous"
|
||||
:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
|
||||
:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
|
||||
|
||||
return oldbit != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* WARNING: non atomic version.
|
||||
*/
|
||||
static __inline__ int
|
||||
__test_and_change_bit(unsigned long nr, volatile void * addr)
|
||||
{
|
||||
unsigned long mask = 1 << (nr & 0x1f);
|
||||
int *m = ((int *) addr) + (nr >> 5);
|
||||
int old = *m;
|
||||
|
||||
*m = old ^ mask;
|
||||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
test_bit(int nr, const volatile void * addr)
|
||||
{
|
||||
return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL;
|
||||
}
|
||||
|
||||
/*
|
||||
* ffz = Find First Zero in word. Undefined if no zero exists,
|
||||
* so code should check against ~0UL first..
|
||||
*
|
||||
* Do a binary search on the bits. Due to the nature of large
|
||||
* constants on the alpha, it is worthwhile to split the search.
|
||||
*/
|
||||
static inline unsigned long ffz_b(unsigned long x)
|
||||
{
|
||||
unsigned long sum, x1, x2, x4;
|
||||
|
||||
x = ~x & -~x; /* set first 0 bit, clear others */
|
||||
x1 = x & 0xAA;
|
||||
x2 = x & 0xCC;
|
||||
x4 = x & 0xF0;
|
||||
sum = x2 ? 2 : 0;
|
||||
sum += (x4 != 0) * 4;
|
||||
sum += (x1 != 0);
|
||||
|
||||
return sum;
|
||||
}
|
||||
|
||||
static inline unsigned long ffz(unsigned long word)
|
||||
{
|
||||
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
|
||||
/* Whee. EV67 can calculate it directly. */
|
||||
return __kernel_cttz(~word);
|
||||
#else
|
||||
unsigned long bits, qofs, bofs;
|
||||
|
||||
bits = __kernel_cmpbge(word, ~0UL);
|
||||
qofs = ffz_b(bits);
|
||||
bits = __kernel_extbl(word, qofs);
|
||||
bofs = ffz_b(bits);
|
||||
|
||||
return qofs*8 + bofs;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* __ffs = Find First set bit in word. Undefined if no set bit exists.
|
||||
*/
|
||||
static inline unsigned long __ffs(unsigned long word)
|
||||
{
|
||||
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
|
||||
/* Whee. EV67 can calculate it directly. */
|
||||
return __kernel_cttz(word);
|
||||
#else
|
||||
unsigned long bits, qofs, bofs;
|
||||
|
||||
bits = __kernel_cmpbge(0, word);
|
||||
qofs = ffz_b(bits);
|
||||
bits = __kernel_extbl(word, qofs);
|
||||
bofs = ffz_b(~bits);
|
||||
|
||||
return qofs*8 + bofs;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* ffs: find first bit set. This is defined the same way as
|
||||
* the libc and compiler builtin ffs routines, therefore
|
||||
* differs in spirit from the above __ffs.
|
||||
*/
|
||||
|
||||
static inline int ffs(int word)
|
||||
{
|
||||
int result = __ffs(word) + 1;
|
||||
return word ? result : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* fls: find last bit set.
|
||||
*/
|
||||
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
|
||||
static inline int fls64(unsigned long word)
|
||||
{
|
||||
return 64 - __kernel_ctlz(word);
|
||||
}
|
||||
#else
|
||||
extern const unsigned char __flsm1_tab[256];
|
||||
|
||||
static inline int fls64(unsigned long x)
|
||||
{
|
||||
unsigned long t, a, r;
|
||||
|
||||
t = __kernel_cmpbge (x, 0x0101010101010101UL);
|
||||
a = __flsm1_tab[t];
|
||||
t = __kernel_extbl (x, a);
|
||||
r = a*8 + __flsm1_tab[t] + (x != 0);
|
||||
|
||||
return r;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline unsigned long __fls(unsigned long x)
|
||||
{
|
||||
return fls64(x) - 1;
|
||||
}
|
||||
|
||||
static inline int fls(unsigned int x)
|
||||
{
|
||||
return fls64(x);
|
||||
}
|
||||
|
||||
/*
|
||||
* hweightN: returns the hamming weight (i.e. the number
|
||||
* of bits set) of a N-bit word
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
|
||||
/* Whee. EV67 can calculate it directly. */
|
||||
static inline unsigned long __arch_hweight64(unsigned long w)
|
||||
{
|
||||
return __kernel_ctpop(w);
|
||||
}
|
||||
|
||||
static inline unsigned int __arch_hweight32(unsigned int w)
|
||||
{
|
||||
return __arch_hweight64(w);
|
||||
}
|
||||
|
||||
static inline unsigned int __arch_hweight16(unsigned int w)
|
||||
{
|
||||
return __arch_hweight64(w & 0xffff);
|
||||
}
|
||||
|
||||
static inline unsigned int __arch_hweight8(unsigned int w)
|
||||
{
|
||||
return __arch_hweight64(w & 0xff);
|
||||
}
|
||||
#else
|
||||
#include <asm-generic/bitops/arch_hweight.h>
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bitops/const_hweight.h>
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* Every architecture must define this function. It's the fastest
|
||||
* way of searching a 100-bit bitmap. It's guaranteed that at least
|
||||
* one of the 100 bits is cleared.
|
||||
*/
|
||||
static inline unsigned long
|
||||
sched_find_first_bit(const unsigned long b[2])
|
||||
{
|
||||
unsigned long b0, b1, ofs, tmp;
|
||||
|
||||
b0 = b[0];
|
||||
b1 = b[1];
|
||||
ofs = (b0 ? 0 : 64);
|
||||
tmp = (b0 ? b0 : b1);
|
||||
|
||||
return __ffs(tmp) + ofs;
|
||||
}
|
||||
|
||||
#include <asm-generic/bitops/le.h>
|
||||
|
||||
#include <asm-generic/bitops/ext2-atomic-setbit.h>
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ALPHA_BITOPS_H */
|
||||
@ -1,25 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_BUG_H
|
||||
#define _ALPHA_BUG_H
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#ifdef CONFIG_BUG
|
||||
#include <asm/pal.h>
|
||||
|
||||
/* ??? Would be nice to use .gprel32 here, but we can't be sure that the
|
||||
function loaded the GP, so this could fail in modules. */
|
||||
#define BUG() do { \
|
||||
__asm__ __volatile__( \
|
||||
"call_pal %0 # bugchk\n\t" \
|
||||
".long %1\n\t.8byte %2" \
|
||||
: : "i"(PAL_bugchk), "i"(__LINE__), "i"(__FILE__)); \
|
||||
unreachable(); \
|
||||
} while (0)
|
||||
|
||||
#define HAVE_ARCH_BUG
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bug.h>
|
||||
|
||||
#endif
|
||||
@ -1,20 +0,0 @@
|
||||
/*
|
||||
* include/asm-alpha/bugs.h
|
||||
*
|
||||
* Copyright (C) 1994 Linus Torvalds
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is included by init/main.c to check for architecture-dependent bugs.
|
||||
*
|
||||
* Needs:
|
||||
* void check_bugs(void);
|
||||
*/
|
||||
|
||||
/*
|
||||
* I don't know of any alpha bugs yet.. Nice chip
|
||||
*/
|
||||
|
||||
static void check_bugs(void)
|
||||
{
|
||||
}
|
||||
@ -1,23 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* include/asm-alpha/cache.h
|
||||
*/
|
||||
#ifndef __ARCH_ALPHA_CACHE_H
|
||||
#define __ARCH_ALPHA_CACHE_H
|
||||
|
||||
|
||||
/* Bytes per L1 (data) cache line. */
|
||||
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
|
||||
# define L1_CACHE_BYTES 64
|
||||
# define L1_CACHE_SHIFT 6
|
||||
#else
|
||||
/* Both EV4 and EV5 are write-through, read-allocate,
|
||||
direct-mapped, physical.
|
||||
*/
|
||||
# define L1_CACHE_BYTES 32
|
||||
# define L1_CACHE_SHIFT 5
|
||||
#endif
|
||||
|
||||
#define SMP_CACHE_BYTES L1_CACHE_BYTES
|
||||
|
||||
#endif
|
||||
@ -1,62 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_CACHEFLUSH_H
|
||||
#define _ALPHA_CACHEFLUSH_H
|
||||
|
||||
#include <linux/mm.h>
|
||||
|
||||
/* Note that the following two definitions are _highly_ dependent
|
||||
on the contexts in which they are used in the kernel. I personally
|
||||
think it is criminal how loosely defined these macros are. */
|
||||
|
||||
/* We need to flush the kernel's icache after loading modules. The
|
||||
only other use of this macro is in load_aout_interp which is not
|
||||
used on Alpha.
|
||||
|
||||
Note that this definition should *not* be used for userspace
|
||||
icache flushing. While functional, it is _way_ overkill. The
|
||||
icache is tagged with ASNs and it suffices to allocate a new ASN
|
||||
for the process. */
|
||||
#ifndef CONFIG_SMP
|
||||
#define flush_icache_range(start, end) imb()
|
||||
#else
|
||||
#define flush_icache_range(start, end) smp_imb()
|
||||
extern void smp_imb(void);
|
||||
#endif
|
||||
|
||||
/* We need to flush the userspace icache after setting breakpoints in
|
||||
ptrace.
|
||||
|
||||
Instead of indiscriminately using imb, take advantage of the fact
|
||||
that icache entries are tagged with the ASN and load a new mm context. */
|
||||
/* ??? Ought to use this in arch/alpha/kernel/signal.c too. */
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#include <linux/sched.h>
|
||||
|
||||
extern void __load_new_mm_context(struct mm_struct *);
|
||||
static inline void
|
||||
flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long addr, int len)
|
||||
{
|
||||
if (vma->vm_flags & VM_EXEC) {
|
||||
struct mm_struct *mm = vma->vm_mm;
|
||||
if (current->active_mm == mm)
|
||||
__load_new_mm_context(mm);
|
||||
else
|
||||
mm->context[smp_processor_id()] = 0;
|
||||
}
|
||||
}
|
||||
#define flush_icache_user_page flush_icache_user_page
|
||||
#else /* CONFIG_SMP */
|
||||
extern void flush_icache_user_page(struct vm_area_struct *vma,
|
||||
struct page *page, unsigned long addr, int len);
|
||||
#define flush_icache_user_page flush_icache_user_page
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/* This is used only in __do_fault and do_swap_page. */
|
||||
#define flush_icache_page(vma, page) \
|
||||
flush_icache_user_page((vma), (page), 0, 0)
|
||||
|
||||
#include <asm-generic/cacheflush.h>
|
||||
|
||||
#endif /* _ALPHA_CACHEFLUSH_H */
|
||||
@ -1,74 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_CHECKSUM_H
|
||||
#define _ALPHA_CHECKSUM_H
|
||||
|
||||
#include <linux/in6.h>
|
||||
|
||||
/*
|
||||
* This is a version of ip_compute_csum() optimized for IP headers,
|
||||
* which always checksum on 4 octet boundaries.
|
||||
*/
|
||||
extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
|
||||
|
||||
/*
|
||||
* computes the checksum of the TCP/UDP pseudo-header
|
||||
* returns a 16-bit checksum, already complemented
|
||||
*/
|
||||
__sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
|
||||
__u32 len, __u8 proto, __wsum sum);
|
||||
|
||||
__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
|
||||
__u32 len, __u8 proto, __wsum sum);
|
||||
|
||||
/*
|
||||
* computes the checksum of a memory block at buff, length len,
|
||||
* and adds in "sum" (32-bit)
|
||||
*
|
||||
* returns a 32-bit number suitable for feeding into itself
|
||||
* or csum_tcpudp_magic
|
||||
*
|
||||
* this function must be called with even lengths, except
|
||||
* for the last fragment, which may be odd
|
||||
*
|
||||
* it's best to have buff aligned on a 32-bit boundary
|
||||
*/
|
||||
extern __wsum csum_partial(const void *buff, int len, __wsum sum);
|
||||
|
||||
/*
|
||||
* the same as csum_partial, but copies from src while it
|
||||
* checksums
|
||||
*
|
||||
* here even more important to align src and dst on a 32-bit (or even
|
||||
* better 64-bit) boundary
|
||||
*/
|
||||
#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
|
||||
#define _HAVE_ARCH_CSUM_AND_COPY
|
||||
__wsum csum_and_copy_from_user(const void __user *src, void *dst, int len);
|
||||
|
||||
__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len);
|
||||
|
||||
|
||||
/*
|
||||
* this routine is used for miscellaneous IP-like checksums, mainly
|
||||
* in icmp.c
|
||||
*/
|
||||
|
||||
extern __sum16 ip_compute_csum(const void *buff, int len);
|
||||
|
||||
/*
|
||||
* Fold a partial checksum without adding pseudo headers
|
||||
*/
|
||||
|
||||
static inline __sum16 csum_fold(__wsum csum)
|
||||
{
|
||||
u32 sum = (__force u32)csum;
|
||||
sum = (sum & 0xffff) + (sum >> 16);
|
||||
sum = (sum & 0xffff) + (sum >> 16);
|
||||
return (__force __sum16)~sum;
|
||||
}
|
||||
|
||||
#define _HAVE_ARCH_IPV6_CSUM
|
||||
extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
|
||||
const struct in6_addr *daddr,
|
||||
__u32 len, __u8 proto, __wsum sum);
|
||||
#endif
|
||||
@ -1,76 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ALPHA_CMPXCHG_H
|
||||
#define _ALPHA_CMPXCHG_H
|
||||
|
||||
/*
|
||||
* Atomic exchange routines.
|
||||
*/
|
||||
|
||||
#define ____xchg(type, args...) __xchg ## type ## _local(args)
|
||||
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
|
||||
#include <asm/xchg.h>
|
||||
|
||||
#define xchg_local(ptr, x) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) _x_ = (x); \
|
||||
(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
|
||||
sizeof(*(ptr))); \
|
||||
})
|
||||
|
||||
#define arch_cmpxchg_local(ptr, o, n) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) _o_ = (o); \
|
||||
__typeof__(*(ptr)) _n_ = (n); \
|
||||
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
|
||||
(unsigned long)_n_, \
|
||||
sizeof(*(ptr))); \
|
||||
})
|
||||
|
||||
#define arch_cmpxchg64_local(ptr, o, n) \
|
||||
({ \
|
||||
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
|
||||
cmpxchg_local((ptr), (o), (n)); \
|
||||
})
|
||||
|
||||
#undef ____xchg
|
||||
#undef ____cmpxchg
|
||||
#define ____xchg(type, args...) __xchg ##type(args)
|
||||
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
|
||||
#include <asm/xchg.h>
|
||||
|
||||
/*
|
||||
* The leading and the trailing memory barriers guarantee that these
|
||||
* operations are fully ordered.
|
||||
*/
|
||||
#define arch_xchg(ptr, x) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) __ret; \
|
||||
__typeof__(*(ptr)) _x_ = (x); \
|
||||
smp_mb(); \
|
||||
__ret = (__typeof__(*(ptr))) \
|
||||
__xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
|
||||
smp_mb(); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#define arch_cmpxchg(ptr, o, n) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) __ret; \
|
||||
__typeof__(*(ptr)) _o_ = (o); \
|
||||
__typeof__(*(ptr)) _n_ = (n); \
|
||||
smp_mb(); \
|
||||
__ret = (__typeof__(*(ptr))) __cmpxchg((ptr), \
|
||||
(unsigned long)_o_, (unsigned long)_n_, sizeof(*(ptr)));\
|
||||
smp_mb(); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#define arch_cmpxchg64(ptr, o, n) \
|
||||
({ \
|
||||
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
|
||||
arch_cmpxchg((ptr), (o), (n)); \
|
||||
})
|
||||
|
||||
#undef ____cmpxchg
|
||||
|
||||
#endif /* _ALPHA_CMPXCHG_H */
|
||||
@ -1,7 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_COMPILER_H
|
||||
#define __ALPHA_COMPILER_H
|
||||
|
||||
#include <uapi/asm/compiler.h>
|
||||
|
||||
#endif /* __ALPHA_COMPILER_H */
|
||||
@ -1,30 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __AXP_CONSOLE_H
|
||||
#define __AXP_CONSOLE_H
|
||||
|
||||
#include <uapi/asm/console.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern long callback_puts(long unit, const char *s, long length);
|
||||
extern long callback_getc(long unit);
|
||||
extern long callback_open_console(void);
|
||||
extern long callback_close_console(void);
|
||||
extern long callback_open(const char *device, long length);
|
||||
extern long callback_close(long unit);
|
||||
extern long callback_read(long channel, long count, const char *buf, long lbn);
|
||||
extern long callback_getenv(long id, const char *buf, unsigned long buf_size);
|
||||
extern long callback_setenv(long id, const char *buf, unsigned long buf_size);
|
||||
extern long callback_save_env(void);
|
||||
|
||||
extern int srm_fixup(unsigned long new_callback_addr,
|
||||
unsigned long new_hwrpb_addr);
|
||||
extern long srm_puts(const char *, long);
|
||||
extern long srm_printk(const char *, ...)
|
||||
__attribute__ ((format (printf, 1, 2)));
|
||||
|
||||
struct crb_struct;
|
||||
struct hwrpb_struct;
|
||||
extern int callback_init_done;
|
||||
extern void * callback_init(void *);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __AXP_CONSOLE_H */
|
||||
@ -1,518 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_APECS__H__
|
||||
#define __ALPHA_APECS__H__
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/compiler.h>
|
||||
|
||||
/*
|
||||
* APECS is the internal name for the 2107x chipset which provides
|
||||
* memory controller and PCI access for the 21064 chip based systems.
|
||||
*
|
||||
* This file is based on:
|
||||
*
|
||||
* DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
|
||||
* Data Sheet
|
||||
*
|
||||
* EC-N0648-72
|
||||
*
|
||||
*
|
||||
* david.rusling@reo.mts.dec.com Initial Version.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
|
||||
that get passed through the PCI<->ISA bridge chip. So we've gotta use
|
||||
both windows to max out the physical memory we can DMA to. Sigh...
|
||||
|
||||
If we try a window at 0 for 1GB as a work-around, we run into conflicts
|
||||
with ISA/PCI bus memory which can't be relocated, like VGA aperture and
|
||||
BIOS ROMs. So we must put the windows high enough to avoid these areas.
|
||||
|
||||
We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
|
||||
and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.
|
||||
Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
|
||||
be used for that range (via virt_to_bus()).
|
||||
|
||||
Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,
|
||||
to keep virt_to_bus() from returning an address in the first window, for
|
||||
a data area that goes beyond the 64Mb first DMA window. Sigh...
|
||||
The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but
|
||||
we can't just use that here, because of header file looping... :-(
|
||||
|
||||
Window 1 will be used for all DMA from the ISA bus; yes, that does
|
||||
limit what memory an ISA floppy or sound card or Ethernet can touch, but
|
||||
it's also a known limitation on other platforms as well. We use the
|
||||
same technique that is used on INTEL platforms with similar limitation:
|
||||
set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
|
||||
We trust that any ISA bus device drivers will *always* ask for DMAable
|
||||
memory explicitly via kmalloc()/get_free_pages() flags arguments.
|
||||
|
||||
Note that most PCI bus devices' drivers do *not* explicitly ask for
|
||||
DMAable memory; they count on being able to DMA to any memory they
|
||||
get from kmalloc()/get_free_pages(). They will also use window 1 for
|
||||
any physical memory accesses below 64Mb; the rest will be handled by
|
||||
window 2, maxing out at 1Gb of memory. I trust this is enough... :-)
|
||||
|
||||
We hope that the area before the first window is large enough so that
|
||||
there will be no overlap at the top end (64Mb). We *must* locate the
|
||||
PCI cards' memory just below window 1, so that there's still the
|
||||
possibility of being able to access it via SPARSE space. This is
|
||||
important for cards such as the Matrox Millennium, whose Xserver
|
||||
wants to access memory-mapped registers in byte and short lengths.
|
||||
|
||||
Note that the XL is treated differently from the AVANTI, even though
|
||||
for most other things they are identical. It didn't seem reasonable to
|
||||
make the AVANTI support pay for the limitations of the XL. It is true,
|
||||
however, that an XL kernel will run on an AVANTI without problems.
|
||||
|
||||
%%% All of this should be obviated by the ability to route
|
||||
everything through the iommu.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 21071-DA Control and Status registers.
|
||||
* These are used for PCI memory access.
|
||||
*/
|
||||
#define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL)
|
||||
#define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL)
|
||||
#define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL)
|
||||
#define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL)
|
||||
#define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL)
|
||||
#define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL)
|
||||
|
||||
#define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL)
|
||||
#define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL)
|
||||
|
||||
#define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL)
|
||||
#define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL)
|
||||
|
||||
#define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL)
|
||||
#define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL)
|
||||
|
||||
#define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL)
|
||||
#define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL)
|
||||
#define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL)
|
||||
|
||||
#define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL)
|
||||
|
||||
#define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL)
|
||||
#define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL)
|
||||
#define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL)
|
||||
#define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL)
|
||||
#define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL)
|
||||
#define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL)
|
||||
#define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL)
|
||||
#define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL)
|
||||
|
||||
#define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL)
|
||||
#define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL)
|
||||
#define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL)
|
||||
#define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL)
|
||||
#define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL)
|
||||
#define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL)
|
||||
#define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL)
|
||||
#define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL)
|
||||
|
||||
#define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL)
|
||||
|
||||
|
||||
/*
|
||||
* 21071-CA Control and Status registers.
|
||||
* These are used to program memory timing,
|
||||
* configure memory and initialise the B-Cache.
|
||||
*/
|
||||
#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL)
|
||||
#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL)
|
||||
#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL)
|
||||
#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL)
|
||||
#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL)
|
||||
#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
|
||||
#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL)
|
||||
#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL)
|
||||
#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL)
|
||||
#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL)
|
||||
#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL)
|
||||
#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL)
|
||||
#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL)
|
||||
|
||||
/* Bank x Base Address Register */
|
||||
#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL)
|
||||
#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL)
|
||||
#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL)
|
||||
#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL)
|
||||
#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL)
|
||||
#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL)
|
||||
#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL)
|
||||
#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL)
|
||||
#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL)
|
||||
|
||||
/* Bank x Configuration Register */
|
||||
#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL)
|
||||
#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL)
|
||||
#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL)
|
||||
#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL)
|
||||
#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL)
|
||||
#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL)
|
||||
#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL)
|
||||
#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL)
|
||||
#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL)
|
||||
|
||||
/* Bank x Timing Register A */
|
||||
#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL)
|
||||
#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL)
|
||||
#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL)
|
||||
#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL)
|
||||
#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL)
|
||||
#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL)
|
||||
#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL)
|
||||
#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL)
|
||||
#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL)
|
||||
|
||||
/* Bank x Timing Register B */
|
||||
#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL)
|
||||
#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL)
|
||||
#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL)
|
||||
#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL)
|
||||
#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL)
|
||||
#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL)
|
||||
#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL)
|
||||
#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL)
|
||||
#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL)
|
||||
|
||||
|
||||
/*
|
||||
* Memory spaces:
|
||||
*/
|
||||
#define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL)
|
||||
#define APECS_CONF (IDENT_ADDR + 0x1e0000000UL)
|
||||
#define APECS_IO (IDENT_ADDR + 0x1c0000000UL)
|
||||
#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
|
||||
#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
|
||||
|
||||
|
||||
/*
|
||||
* Bit definitions for I/O Controller status register 0:
|
||||
*/
|
||||
#define APECS_IOC_STAT0_CMD 0xf
|
||||
#define APECS_IOC_STAT0_ERR (1<<4)
|
||||
#define APECS_IOC_STAT0_LOST (1<<5)
|
||||
#define APECS_IOC_STAT0_THIT (1<<6)
|
||||
#define APECS_IOC_STAT0_TREF (1<<7)
|
||||
#define APECS_IOC_STAT0_CODE_SHIFT 8
|
||||
#define APECS_IOC_STAT0_CODE_MASK 0x7
|
||||
#define APECS_IOC_STAT0_P_NBR_SHIFT 13
|
||||
#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff
|
||||
|
||||
#define APECS_HAE_ADDRESS APECS_IOC_HAXR1
|
||||
|
||||
|
||||
/*
|
||||
* Data structure for handling APECS machine checks:
|
||||
*/
|
||||
|
||||
struct el_apecs_mikasa_sysdata_mcheck
|
||||
{
|
||||
unsigned long coma_gcr;
|
||||
unsigned long coma_edsr;
|
||||
unsigned long coma_ter;
|
||||
unsigned long coma_elar;
|
||||
unsigned long coma_ehar;
|
||||
unsigned long coma_ldlr;
|
||||
unsigned long coma_ldhr;
|
||||
unsigned long coma_base0;
|
||||
unsigned long coma_base1;
|
||||
unsigned long coma_base2;
|
||||
unsigned long coma_base3;
|
||||
unsigned long coma_cnfg0;
|
||||
unsigned long coma_cnfg1;
|
||||
unsigned long coma_cnfg2;
|
||||
unsigned long coma_cnfg3;
|
||||
unsigned long epic_dcsr;
|
||||
unsigned long epic_pear;
|
||||
unsigned long epic_sear;
|
||||
unsigned long epic_tbr1;
|
||||
unsigned long epic_tbr2;
|
||||
unsigned long epic_pbr1;
|
||||
unsigned long epic_pbr2;
|
||||
unsigned long epic_pmr1;
|
||||
unsigned long epic_pmr2;
|
||||
unsigned long epic_harx1;
|
||||
unsigned long epic_harx2;
|
||||
unsigned long epic_pmlt;
|
||||
unsigned long epic_tag0;
|
||||
unsigned long epic_tag1;
|
||||
unsigned long epic_tag2;
|
||||
unsigned long epic_tag3;
|
||||
unsigned long epic_tag4;
|
||||
unsigned long epic_tag5;
|
||||
unsigned long epic_tag6;
|
||||
unsigned long epic_tag7;
|
||||
unsigned long epic_data0;
|
||||
unsigned long epic_data1;
|
||||
unsigned long epic_data2;
|
||||
unsigned long epic_data3;
|
||||
unsigned long epic_data4;
|
||||
unsigned long epic_data5;
|
||||
unsigned long epic_data6;
|
||||
unsigned long epic_data7;
|
||||
|
||||
unsigned long pceb_vid;
|
||||
unsigned long pceb_did;
|
||||
unsigned long pceb_revision;
|
||||
unsigned long pceb_command;
|
||||
unsigned long pceb_status;
|
||||
unsigned long pceb_latency;
|
||||
unsigned long pceb_control;
|
||||
unsigned long pceb_arbcon;
|
||||
unsigned long pceb_arbpri;
|
||||
|
||||
unsigned long esc_id;
|
||||
unsigned long esc_revision;
|
||||
unsigned long esc_int0;
|
||||
unsigned long esc_int1;
|
||||
unsigned long esc_elcr0;
|
||||
unsigned long esc_elcr1;
|
||||
unsigned long esc_last_eisa;
|
||||
unsigned long esc_nmi_stat;
|
||||
|
||||
unsigned long pci_ir;
|
||||
unsigned long pci_imr;
|
||||
unsigned long svr_mgr;
|
||||
};
|
||||
|
||||
/* This for the normal APECS machines. */
|
||||
struct el_apecs_sysdata_mcheck
|
||||
{
|
||||
unsigned long coma_gcr;
|
||||
unsigned long coma_edsr;
|
||||
unsigned long coma_ter;
|
||||
unsigned long coma_elar;
|
||||
unsigned long coma_ehar;
|
||||
unsigned long coma_ldlr;
|
||||
unsigned long coma_ldhr;
|
||||
unsigned long coma_base0;
|
||||
unsigned long coma_base1;
|
||||
unsigned long coma_base2;
|
||||
unsigned long coma_cnfg0;
|
||||
unsigned long coma_cnfg1;
|
||||
unsigned long coma_cnfg2;
|
||||
unsigned long epic_dcsr;
|
||||
unsigned long epic_pear;
|
||||
unsigned long epic_sear;
|
||||
unsigned long epic_tbr1;
|
||||
unsigned long epic_tbr2;
|
||||
unsigned long epic_pbr1;
|
||||
unsigned long epic_pbr2;
|
||||
unsigned long epic_pmr1;
|
||||
unsigned long epic_pmr2;
|
||||
unsigned long epic_harx1;
|
||||
unsigned long epic_harx2;
|
||||
unsigned long epic_pmlt;
|
||||
unsigned long epic_tag0;
|
||||
unsigned long epic_tag1;
|
||||
unsigned long epic_tag2;
|
||||
unsigned long epic_tag3;
|
||||
unsigned long epic_tag4;
|
||||
unsigned long epic_tag5;
|
||||
unsigned long epic_tag6;
|
||||
unsigned long epic_tag7;
|
||||
unsigned long epic_data0;
|
||||
unsigned long epic_data1;
|
||||
unsigned long epic_data2;
|
||||
unsigned long epic_data3;
|
||||
unsigned long epic_data4;
|
||||
unsigned long epic_data5;
|
||||
unsigned long epic_data6;
|
||||
unsigned long epic_data7;
|
||||
};
|
||||
|
||||
struct el_apecs_procdata
|
||||
{
|
||||
unsigned long paltemp[32]; /* PAL TEMP REGS. */
|
||||
/* EV4-specific fields */
|
||||
unsigned long exc_addr; /* Address of excepting instruction. */
|
||||
unsigned long exc_sum; /* Summary of arithmetic traps. */
|
||||
unsigned long exc_mask; /* Exception mask (from exc_sum). */
|
||||
unsigned long iccsr; /* IBox hardware enables. */
|
||||
unsigned long pal_base; /* Base address for PALcode. */
|
||||
unsigned long hier; /* Hardware Interrupt Enable. */
|
||||
unsigned long hirr; /* Hardware Interrupt Request. */
|
||||
unsigned long csr; /* D-stream fault info. */
|
||||
unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */
|
||||
unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
|
||||
unsigned long abox_ctl; /* ABox Control Register. */
|
||||
unsigned long biu_stat; /* BIU Status. */
|
||||
unsigned long biu_addr; /* BUI Address. */
|
||||
unsigned long biu_ctl; /* BIU Control. */
|
||||
unsigned long fill_syndrome;/* For correcting ECC errors. */
|
||||
unsigned long fill_addr; /* Cache block which was being read */
|
||||
unsigned long va; /* Effective VA of fault or miss. */
|
||||
unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/
|
||||
};
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifndef __EXTERN_INLINE
|
||||
#define __EXTERN_INLINE extern inline
|
||||
#define __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O functions:
|
||||
*
|
||||
* Unlike Jensen, the APECS machines have no concept of local
|
||||
* I/O---everything goes over the PCI bus.
|
||||
*
|
||||
* There is plenty room for optimization here. In particular,
|
||||
* the Alpha's insb/insw/extb/extw should be useful in moving
|
||||
* data to/from the right byte-lanes.
|
||||
*/
|
||||
|
||||
#define vip volatile int __force *
|
||||
#define vuip volatile unsigned int __force *
|
||||
#define vulp volatile unsigned long __force *
|
||||
|
||||
#define APECS_SET_HAE \
|
||||
do { \
|
||||
if (addr >= (1UL << 24)) { \
|
||||
unsigned long msb = addr & 0xf8000000; \
|
||||
addr -= msb; \
|
||||
set_hae(msb); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= APECS_DENSE_MEM) {
|
||||
addr -= APECS_DENSE_MEM;
|
||||
APECS_SET_HAE;
|
||||
base_and_type = APECS_SPARSE_MEM + 0x00;
|
||||
} else {
|
||||
addr -= APECS_IO;
|
||||
base_and_type = APECS_IO + 0x00;
|
||||
}
|
||||
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extbl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= APECS_DENSE_MEM) {
|
||||
addr -= APECS_DENSE_MEM;
|
||||
APECS_SET_HAE;
|
||||
base_and_type = APECS_SPARSE_MEM + 0x00;
|
||||
} else {
|
||||
addr -= APECS_IO;
|
||||
base_and_type = APECS_IO + 0x00;
|
||||
}
|
||||
|
||||
w = __kernel_insbl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= APECS_DENSE_MEM) {
|
||||
addr -= APECS_DENSE_MEM;
|
||||
APECS_SET_HAE;
|
||||
base_and_type = APECS_SPARSE_MEM + 0x08;
|
||||
} else {
|
||||
addr -= APECS_IO;
|
||||
base_and_type = APECS_IO + 0x08;
|
||||
}
|
||||
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extwl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= APECS_DENSE_MEM) {
|
||||
addr -= APECS_DENSE_MEM;
|
||||
APECS_SET_HAE;
|
||||
base_and_type = APECS_SPARSE_MEM + 0x08;
|
||||
} else {
|
||||
addr -= APECS_IO;
|
||||
base_and_type = APECS_IO + 0x08;
|
||||
}
|
||||
|
||||
w = __kernel_inswl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < APECS_DENSE_MEM)
|
||||
addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
|
||||
return *(vuip)addr;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < APECS_DENSE_MEM)
|
||||
addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
|
||||
*(vuip)addr = b;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + APECS_IO);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,
|
||||
unsigned long size)
|
||||
{
|
||||
return (void __iomem *)(addr + APECS_DENSE_MEM);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return addr >= IDENT_ADDR + 0x180000000UL;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)
|
||||
{
|
||||
return (unsigned long)addr >= APECS_DENSE_MEM;
|
||||
}
|
||||
|
||||
#undef APECS_SET_HAE
|
||||
|
||||
#undef vip
|
||||
#undef vuip
|
||||
#undef vulp
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX apecs
|
||||
#define apecs_trivial_io_bw 0
|
||||
#define apecs_trivial_io_lq 0
|
||||
#define apecs_trivial_rw_bw 2
|
||||
#define apecs_trivial_rw_lq 1
|
||||
#define apecs_trivial_iounmap 1
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#ifdef __IO_EXTERN_INLINE
|
||||
#undef __EXTERN_INLINE
|
||||
#undef __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_APECS__H__ */
|
||||
@ -1,501 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_CIA__H__
|
||||
#define __ALPHA_CIA__H__
|
||||
|
||||
/* Define to experiment with fitting everything into one 512MB HAE window. */
|
||||
#define CIA_ONE_HAE_WINDOW 1
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/compiler.h>
|
||||
|
||||
/*
|
||||
* CIA is the internal name for the 21171 chipset which provides
|
||||
* memory controller and PCI access for the 21164 chip based systems.
|
||||
* Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
|
||||
*
|
||||
* The lineage is a bit confused, since the 21174 was reportedly started
|
||||
* from the 21171 Pass 1 mask, and so is missing bug fixes that appear
|
||||
* in 21171 Pass 2 and 21172, but it also contains additional features.
|
||||
*
|
||||
* This file is based on:
|
||||
*
|
||||
* DECchip 21171 Core Logic Chipset
|
||||
* Technical Reference Manual
|
||||
*
|
||||
* EC-QE18B-TE
|
||||
*
|
||||
* david.rusling@reo.mts.dec.com Initial Version.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* CIA ADDRESS BIT DEFINITIONS
|
||||
*
|
||||
* 3333 3333 3322 2222 2222 1111 1111 11
|
||||
* 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
|
||||
* 1 000
|
||||
* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
|
||||
* | |\|
|
||||
* | Byte Enable --+ |
|
||||
* | Transfer Length --+
|
||||
* +-- IO space, not cached
|
||||
*
|
||||
* Byte Transfer
|
||||
* Enable Length Transfer Byte Address
|
||||
* adr<6:5> adr<4:3> Length Enable Adder
|
||||
* ---------------------------------------------
|
||||
* 00 00 Byte 1110 0x000
|
||||
* 01 00 Byte 1101 0x020
|
||||
* 10 00 Byte 1011 0x040
|
||||
* 11 00 Byte 0111 0x060
|
||||
*
|
||||
* 00 01 Word 1100 0x008
|
||||
* 01 01 Word 1001 0x028 <= Not supported in this code.
|
||||
* 10 01 Word 0011 0x048
|
||||
*
|
||||
* 00 10 Tribyte 1000 0x010
|
||||
* 01 10 Tribyte 0001 0x030
|
||||
*
|
||||
* 10 11 Longword 0000 0x058
|
||||
*
|
||||
* Note that byte enables are asserted low.
|
||||
*
|
||||
*/
|
||||
|
||||
#define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
|
||||
#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
|
||||
#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
|
||||
|
||||
/*
|
||||
* 21171-CA Control and Status Registers
|
||||
*/
|
||||
#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
|
||||
# define CIA_REV_MASK 0xff
|
||||
#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
|
||||
#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
|
||||
# define CIA_CTRL_PCI_EN (1 << 0)
|
||||
# define CIA_CTRL_PCI_LOCK_EN (1 << 1)
|
||||
# define CIA_CTRL_PCI_LOOP_EN (1 << 2)
|
||||
# define CIA_CTRL_FST_BB_EN (1 << 3)
|
||||
# define CIA_CTRL_PCI_MST_EN (1 << 4)
|
||||
# define CIA_CTRL_PCI_MEM_EN (1 << 5)
|
||||
# define CIA_CTRL_PCI_REQ64_EN (1 << 6)
|
||||
# define CIA_CTRL_PCI_ACK64_EN (1 << 7)
|
||||
# define CIA_CTRL_ADDR_PE_EN (1 << 8)
|
||||
# define CIA_CTRL_PERR_EN (1 << 9)
|
||||
# define CIA_CTRL_FILL_ERR_EN (1 << 10)
|
||||
# define CIA_CTRL_MCHK_ERR_EN (1 << 11)
|
||||
# define CIA_CTRL_ECC_CHK_EN (1 << 12)
|
||||
# define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
|
||||
# define CIA_CTRL_COM_IDLE_BC (1 << 14)
|
||||
# define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
|
||||
# define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
|
||||
# define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
|
||||
# define CIA_CTRL_ARB_CPU_EN (1 << 18)
|
||||
# define CIA_CTRL_EN_ARB_LINK (1 << 19)
|
||||
# define CIA_CTRL_RD_TYPE_SHIFT 20
|
||||
# define CIA_CTRL_RL_TYPE_SHIFT 24
|
||||
# define CIA_CTRL_RM_TYPE_SHIFT 28
|
||||
# define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
|
||||
#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
|
||||
# define CIA_CNFG_IOA_BWEN (1 << 0)
|
||||
# define CIA_CNFG_PCI_MWEN (1 << 4)
|
||||
# define CIA_CNFG_PCI_DWEN (1 << 5)
|
||||
# define CIA_CNFG_PCI_WLEN (1 << 8)
|
||||
#define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
|
||||
#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
|
||||
#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
|
||||
#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
|
||||
#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
|
||||
# define CIA_CACK_EN_LOCK_EN (1 << 0)
|
||||
# define CIA_CACK_EN_MB_EN (1 << 1)
|
||||
# define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
|
||||
# define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
|
||||
|
||||
|
||||
/*
|
||||
* 21171-CA Diagnostic Registers
|
||||
*/
|
||||
#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
|
||||
#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
|
||||
|
||||
/*
|
||||
* 21171-CA Performance Monitor registers
|
||||
*/
|
||||
#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
|
||||
#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
|
||||
|
||||
/*
|
||||
* 21171-CA Error registers
|
||||
*/
|
||||
#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
|
||||
#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
|
||||
#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
|
||||
# define CIA_ERR_COR_ERR (1 << 0)
|
||||
# define CIA_ERR_UN_COR_ERR (1 << 1)
|
||||
# define CIA_ERR_CPU_PE (1 << 2)
|
||||
# define CIA_ERR_MEM_NEM (1 << 3)
|
||||
# define CIA_ERR_PCI_SERR (1 << 4)
|
||||
# define CIA_ERR_PERR (1 << 5)
|
||||
# define CIA_ERR_PCI_ADDR_PE (1 << 6)
|
||||
# define CIA_ERR_RCVD_MAS_ABT (1 << 7)
|
||||
# define CIA_ERR_RCVD_TAR_ABT (1 << 8)
|
||||
# define CIA_ERR_PA_PTE_INV (1 << 9)
|
||||
# define CIA_ERR_FROM_WRT_ERR (1 << 10)
|
||||
# define CIA_ERR_IOA_TIMEOUT (1 << 11)
|
||||
# define CIA_ERR_LOST_CORR_ERR (1 << 16)
|
||||
# define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
|
||||
# define CIA_ERR_LOST_CPU_PE (1 << 18)
|
||||
# define CIA_ERR_LOST_MEM_NEM (1 << 19)
|
||||
# define CIA_ERR_LOST_PERR (1 << 21)
|
||||
# define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
|
||||
# define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
|
||||
# define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
|
||||
# define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
|
||||
# define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
|
||||
# define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
|
||||
# define CIA_ERR_VALID (1 << 31)
|
||||
#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
|
||||
#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
|
||||
#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
|
||||
#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
|
||||
#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
|
||||
#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
|
||||
#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
|
||||
#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
|
||||
|
||||
/*
|
||||
* 21171-CA System configuration registers
|
||||
*/
|
||||
#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
|
||||
#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
|
||||
#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
|
||||
#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
|
||||
#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
|
||||
#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
|
||||
#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
|
||||
#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
|
||||
#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
|
||||
#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
|
||||
#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
|
||||
#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
|
||||
|
||||
/*
|
||||
* 2117A-CA PCI Address and Scatter-Gather Registers.
|
||||
*/
|
||||
#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
|
||||
|
||||
#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
|
||||
#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
|
||||
#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
|
||||
|
||||
#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
|
||||
#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
|
||||
#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
|
||||
|
||||
#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
|
||||
#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
|
||||
#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
|
||||
|
||||
#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
|
||||
#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
|
||||
#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
|
||||
|
||||
#define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
|
||||
#define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
|
||||
#define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
|
||||
|
||||
#define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
|
||||
|
||||
/*
|
||||
* 2117A-CA Address Translation Registers.
|
||||
*/
|
||||
|
||||
/* 8 tag registers, the first 4 of which are lockable. */
|
||||
#define CIA_IOC_TB_TAGn(n) \
|
||||
(IDENT_ADDR + 0x8760000800UL + (n)*0x40)
|
||||
|
||||
/* 4 page registers per tag register. */
|
||||
#define CIA_IOC_TBn_PAGEm(n,m) \
|
||||
(IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
|
||||
|
||||
/*
|
||||
* Memory spaces:
|
||||
*/
|
||||
#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
|
||||
#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
|
||||
#define CIA_IO (IDENT_ADDR + 0x8580000000UL)
|
||||
#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
|
||||
#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
|
||||
#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
|
||||
#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
|
||||
#define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
|
||||
#define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
|
||||
#define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
|
||||
#define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
|
||||
|
||||
/*
|
||||
* ALCOR's GRU ASIC registers
|
||||
*/
|
||||
#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
|
||||
#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
|
||||
#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
|
||||
#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
|
||||
#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
|
||||
|
||||
#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
|
||||
#define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
|
||||
#define GRU_LED (IDENT_ADDR + 0x8780000800UL)
|
||||
#define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
|
||||
|
||||
#define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
|
||||
#define XLT_GRU_INT_REQ_BITS 0x80003fffUL
|
||||
#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
|
||||
|
||||
/*
|
||||
* PYXIS interrupt control registers
|
||||
*/
|
||||
#define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
|
||||
#define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
|
||||
#define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
|
||||
#define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
|
||||
#define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
|
||||
#define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
|
||||
#define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
|
||||
#define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
|
||||
#define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
|
||||
#define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
|
||||
|
||||
/* Offset between ram physical addresses and pci64 DAC bus addresses. */
|
||||
#define PYXIS_DAC_OFFSET (1UL << 40)
|
||||
|
||||
/*
|
||||
* Data structure for handling CIA machine checks.
|
||||
*/
|
||||
|
||||
/* System-specific info. */
|
||||
struct el_CIA_sysdata_mcheck {
|
||||
unsigned long cpu_err0;
|
||||
unsigned long cpu_err1;
|
||||
unsigned long cia_err;
|
||||
unsigned long cia_stat;
|
||||
unsigned long err_mask;
|
||||
unsigned long cia_syn;
|
||||
unsigned long mem_err0;
|
||||
unsigned long mem_err1;
|
||||
unsigned long pci_err0;
|
||||
unsigned long pci_err1;
|
||||
unsigned long pci_err2;
|
||||
};
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifndef __EXTERN_INLINE
|
||||
/* Do not touch, this should *NOT* be static inline */
|
||||
#define __EXTERN_INLINE extern inline
|
||||
#define __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O functions:
|
||||
*
|
||||
* CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
|
||||
* series of processors uses a sparse address mapping scheme to
|
||||
* get at PCI memory and I/O.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory functions. 64-bit and 32-bit accesses are done through
|
||||
* dense memory space, everything else through sparse space.
|
||||
*
|
||||
* For reading and writing 8 and 16 bit quantities we need to
|
||||
* go through one of the three sparse address mapping regions
|
||||
* and use the HAE_MEM CSR to provide some bits of the address.
|
||||
* The following few routines use only sparse address region 1
|
||||
* which gives 1Gbyte of accessible space which relates exactly
|
||||
* to the amount of PCI memory mapping *into* system address space.
|
||||
* See p 6-17 of the specification but it looks something like this:
|
||||
*
|
||||
* 21164 Address:
|
||||
*
|
||||
* 3 2 1
|
||||
* 9876543210987654321098765432109876543210
|
||||
* 1ZZZZ0.PCI.QW.Address............BBLL
|
||||
*
|
||||
* ZZ = SBZ
|
||||
* BB = Byte offset
|
||||
* LL = Transfer length
|
||||
*
|
||||
* PCI Address:
|
||||
*
|
||||
* 3 2 1
|
||||
* 10987654321098765432109876543210
|
||||
* HHH....PCI.QW.Address........ 00
|
||||
*
|
||||
* HHH = 31:29 HAE_MEM CSR
|
||||
*
|
||||
*/
|
||||
|
||||
#define vip volatile int __force *
|
||||
#define vuip volatile unsigned int __force *
|
||||
#define vulp volatile unsigned long __force *
|
||||
|
||||
__EXTERN_INLINE unsigned int cia_ioread8(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= CIA_DENSE_MEM)
|
||||
base_and_type = CIA_SPARSE_MEM + 0x00;
|
||||
else
|
||||
base_and_type = CIA_IO + 0x00;
|
||||
|
||||
/* We can use CIA_MEM_R1_MASK for io ports too, since it is large
|
||||
enough to cover all io ports, and smaller than CIA_IO. */
|
||||
addr &= CIA_MEM_R1_MASK;
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extbl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= CIA_DENSE_MEM)
|
||||
base_and_type = CIA_SPARSE_MEM + 0x00;
|
||||
else
|
||||
base_and_type = CIA_IO + 0x00;
|
||||
|
||||
addr &= CIA_MEM_R1_MASK;
|
||||
w = __kernel_insbl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int cia_ioread16(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= CIA_DENSE_MEM)
|
||||
base_and_type = CIA_SPARSE_MEM + 0x08;
|
||||
else
|
||||
base_and_type = CIA_IO + 0x08;
|
||||
|
||||
addr &= CIA_MEM_R1_MASK;
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extwl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= CIA_DENSE_MEM)
|
||||
base_and_type = CIA_SPARSE_MEM + 0x08;
|
||||
else
|
||||
base_and_type = CIA_IO + 0x08;
|
||||
|
||||
addr &= CIA_MEM_R1_MASK;
|
||||
w = __kernel_inswl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int cia_ioread32(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < CIA_DENSE_MEM)
|
||||
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
|
||||
return *(vuip)addr;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < CIA_DENSE_MEM)
|
||||
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
|
||||
*(vuip)addr = b;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + CIA_IO);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
|
||||
unsigned long size)
|
||||
{
|
||||
return (void __iomem *)(addr + CIA_DENSE_MEM);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return addr >= IDENT_ADDR + 0x8000000000UL;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
|
||||
{
|
||||
return (unsigned long)addr >= CIA_DENSE_MEM;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + CIA_BW_IO);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
|
||||
unsigned long size)
|
||||
{
|
||||
return (void __iomem *)(addr + CIA_BW_MEM);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return addr >= IDENT_ADDR + 0x8000000000UL;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
|
||||
{
|
||||
return (unsigned long)addr < CIA_BW_IO;
|
||||
}
|
||||
|
||||
#undef vip
|
||||
#undef vuip
|
||||
#undef vulp
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX cia
|
||||
#define cia_trivial_rw_bw 2
|
||||
#define cia_trivial_rw_lq 1
|
||||
#define cia_trivial_io_bw 0
|
||||
#define cia_trivial_io_lq 0
|
||||
#define cia_trivial_iounmap 1
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX cia_bwx
|
||||
#define cia_bwx_trivial_rw_bw 1
|
||||
#define cia_bwx_trivial_rw_lq 1
|
||||
#define cia_bwx_trivial_io_bw 1
|
||||
#define cia_bwx_trivial_io_lq 1
|
||||
#define cia_bwx_trivial_iounmap 1
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#ifdef CONFIG_ALPHA_PYXIS
|
||||
#define __IO_PREFIX cia_bwx
|
||||
#else
|
||||
#define __IO_PREFIX cia
|
||||
#endif
|
||||
|
||||
#ifdef __IO_EXTERN_INLINE
|
||||
#undef __EXTERN_INLINE
|
||||
#undef __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_CIA__H__ */
|
||||
@ -1,233 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_IRONGATE__H__
|
||||
#define __ALPHA_IRONGATE__H__
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/compiler.h>
|
||||
|
||||
/*
|
||||
* IRONGATE is the internal name for the AMD-751 K7 core logic chipset
|
||||
* which provides memory controller and PCI access for NAUTILUS-based
|
||||
* EV6 (21264) systems.
|
||||
*
|
||||
* This file is based on:
|
||||
*
|
||||
* IronGate management library, (c) 1999 Alpha Processor, Inc.
|
||||
* Copyright (C) 1999 Alpha Processor, Inc.,
|
||||
* (David Daniel, Stig Telfer, Soohoon Lee)
|
||||
*/
|
||||
|
||||
/*
|
||||
* The 21264 supports, and internally recognizes, a 44-bit physical
|
||||
* address space that is divided equally between memory address space
|
||||
* and I/O address space. Memory address space resides in the lower
|
||||
* half of the physical address space (PA[43]=0) and I/O address space
|
||||
* resides in the upper half of the physical address space (PA[43]=1).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
|
||||
* through the routines given is 32-bit.
|
||||
*
|
||||
* The first 0x40 bytes are standard as per the PCI spec.
|
||||
*/
|
||||
|
||||
typedef volatile __u32 igcsr32;
|
||||
|
||||
typedef struct {
|
||||
igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
|
||||
igcsr32 stat_cmd; /* 0x04 - status, command */
|
||||
igcsr32 class; /* 0x08 - class code, rev ID */
|
||||
igcsr32 latency; /* 0x0C - header type, PCI latency */
|
||||
igcsr32 bar0; /* 0x10 - BAR0 - AGP */
|
||||
igcsr32 bar1; /* 0x14 - BAR1 - GART */
|
||||
igcsr32 bar2; /* 0x18 - Power Management reg block */
|
||||
|
||||
igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
|
||||
|
||||
igcsr32 capptr; /* 0x34 - Capabilities pointer */
|
||||
|
||||
igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
|
||||
|
||||
igcsr32 bacsr10; /* 0x40 - base address chip selects */
|
||||
igcsr32 bacsr32; /* 0x44 - base address chip selects */
|
||||
igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
|
||||
761: ECC, mode/status */
|
||||
|
||||
igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
|
||||
|
||||
igcsr32 drammap; /* 0x50 - address mapping control */
|
||||
igcsr32 dramtm; /* 0x54 - timing, driver strength */
|
||||
igcsr32 dramms; /* 0x58 - DRAM mode/status */
|
||||
|
||||
igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
|
||||
|
||||
igcsr32 biu0; /* 0x60 - bus interface unit */
|
||||
igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
|
||||
|
||||
igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
|
||||
|
||||
igcsr32 mro; /* 0x70 - memory request optimiser */
|
||||
|
||||
igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
|
||||
|
||||
igcsr32 whami; /* 0x80 - who am I */
|
||||
igcsr32 pciarb; /* 0x84 - PCI arbitration control */
|
||||
igcsr32 pcicfg; /* 0x88 - PCI config status */
|
||||
|
||||
igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
|
||||
|
||||
igcsr32 pci_mem; /* 0x9C - PCI top of memory,
|
||||
761 only */
|
||||
|
||||
/* AGP (bus 1) control registers */
|
||||
igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
|
||||
igcsr32 agpstat; /* 0xA4 - AGP status register */
|
||||
igcsr32 agpcmd; /* 0xA8 - AGP control register */
|
||||
igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
|
||||
igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
|
||||
} Irongate0;
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
|
||||
igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
|
||||
igcsr32 class; /* 0x08 - subclass, baseclass etc */
|
||||
igcsr32 htype; /* 0x0C - header type (at 0x0E) */
|
||||
igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
|
||||
igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
|
||||
igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
|
||||
igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
|
||||
igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
|
||||
igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
|
||||
igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
|
||||
igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
|
||||
igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
|
||||
|
||||
} Irongate1;
|
||||
|
||||
extern igcsr32 *IronECC;
|
||||
|
||||
/*
|
||||
* Memory spaces:
|
||||
*/
|
||||
|
||||
/* Irongate is consistent with a subset of the Tsunami memory map */
|
||||
#ifdef USE_48_BIT_KSEG
|
||||
#define IRONGATE_BIAS 0x80000000000UL
|
||||
#else
|
||||
#define IRONGATE_BIAS 0x10000000000UL
|
||||
#endif
|
||||
|
||||
|
||||
#define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
|
||||
#define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
|
||||
#define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
|
||||
#define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
|
||||
|
||||
/*
|
||||
* PCI Configuration space accesses are formed like so:
|
||||
*
|
||||
* 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
|
||||
* : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
|
||||
* ---bus numer--- -device-- -fun- ---register----
|
||||
*/
|
||||
|
||||
#define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
|
||||
((dev)<<11) | \
|
||||
((fun)<<8) | \
|
||||
(reg) )
|
||||
|
||||
#define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
|
||||
#define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
|
||||
|
||||
/*
|
||||
* Data structure for handling IRONGATE machine checks:
|
||||
* This is the standard OSF logout frame
|
||||
*/
|
||||
|
||||
#define SCB_Q_SYSERR 0x620 /* OSF definitions */
|
||||
#define SCB_Q_PROCERR 0x630
|
||||
#define SCB_Q_SYSMCHK 0x660
|
||||
#define SCB_Q_PROCMCHK 0x670
|
||||
|
||||
struct el_IRONGATE_sysdata_mcheck {
|
||||
__u32 FrameSize; /* Bytes, including this field */
|
||||
__u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
|
||||
__u32 CpuOffset; /* Offset to CPU-specific into */
|
||||
__u32 SystemOffset; /* Offset to system-specific info */
|
||||
__u32 MCHK_Code;
|
||||
__u32 MCHK_Frame_Rev;
|
||||
__u64 I_STAT;
|
||||
__u64 DC_STAT;
|
||||
__u64 C_ADDR;
|
||||
__u64 DC1_SYNDROME;
|
||||
__u64 DC0_SYNDROME;
|
||||
__u64 C_STAT;
|
||||
__u64 C_STS;
|
||||
__u64 RESERVED0;
|
||||
__u64 EXC_ADDR;
|
||||
__u64 IER_CM;
|
||||
__u64 ISUM;
|
||||
__u64 MM_STAT;
|
||||
__u64 PAL_BASE;
|
||||
__u64 I_CTL;
|
||||
__u64 PCTX;
|
||||
};
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifndef __EXTERN_INLINE
|
||||
#define __EXTERN_INLINE extern inline
|
||||
#define __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O functions:
|
||||
*
|
||||
* IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
|
||||
* K7 can only use linear accesses to get at PCI memory and I/O spaces.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory functions. All accesses are done through linear space.
|
||||
*/
|
||||
|
||||
__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + IRONGATE_IO);
|
||||
}
|
||||
|
||||
extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
|
||||
extern void irongate_iounmap(volatile void __iomem *addr);
|
||||
|
||||
__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return addr >= IRONGATE_MEM;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long)xaddr;
|
||||
return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
|
||||
}
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX irongate
|
||||
#define irongate_trivial_rw_bw 1
|
||||
#define irongate_trivial_rw_lq 1
|
||||
#define irongate_trivial_io_bw 1
|
||||
#define irongate_trivial_io_lq 1
|
||||
#define irongate_trivial_iounmap 0
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#ifdef __IO_EXTERN_INLINE
|
||||
#undef __EXTERN_INLINE
|
||||
#undef __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_IRONGATE__H__ */
|
||||
@ -1,362 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ALPHA_LCA__H__
|
||||
#define __ALPHA_LCA__H__
|
||||
|
||||
#include <asm/compiler.h>
|
||||
#include <asm/mce.h>
|
||||
|
||||
/*
|
||||
* Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,
|
||||
* for example).
|
||||
*
|
||||
* This file is based on:
|
||||
*
|
||||
* DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors
|
||||
* Hardware Reference Manual; Digital Equipment Corp.; May 1994;
|
||||
* Maynard, MA; Order Number: EC-N2681-71.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: The LCA uses a Host Address Extension (HAE) register to access
|
||||
* PCI addresses that are beyond the first 27 bits of address
|
||||
* space. Updating the HAE requires an external cycle (and
|
||||
* a memory barrier), which tends to be slow. Instead of updating
|
||||
* it on each sparse memory access, we keep the current HAE value
|
||||
* cached in variable cache_hae. Only if the cached HAE differs
|
||||
* from the desired HAE value do we actually updated HAE register.
|
||||
* The HAE register is preserved by the interrupt handler entry/exit
|
||||
* code, so this scheme works even in the presence of interrupts.
|
||||
*
|
||||
* Dense memory space doesn't require the HAE, but is restricted to
|
||||
* aligned 32 and 64 bit accesses. Special Cycle and Interrupt
|
||||
* Acknowledge cycles may also require the use of the HAE. The LCA
|
||||
* limits I/O address space to the bottom 24 bits of address space,
|
||||
* but this easily covers the 16 bit ISA I/O address space.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE 2! The memory operations do not set any memory barriers, as
|
||||
* it's not needed for cases like a frame buffer that is essentially
|
||||
* memory-like. You need to do them by hand if the operations depend
|
||||
* on ordering.
|
||||
*
|
||||
* Similarly, the port I/O operations do a "mb" only after a write
|
||||
* operation: if an mb is needed before (as in the case of doing
|
||||
* memory mapped I/O first, and then a port I/O operation to the same
|
||||
* device), it needs to be done by hand.
|
||||
*
|
||||
* After the above has bitten me 100 times, I'll give up and just do
|
||||
* the mb all the time, but right now I'm hoping this will work out.
|
||||
* Avoiding mb's may potentially be a noticeable speed improvement,
|
||||
* but I can't honestly say I've tested it.
|
||||
*
|
||||
* Handling interrupts that need to do mb's to synchronize to
|
||||
* non-interrupts is another fun race area. Don't do it (because if
|
||||
* you do, I'll have to do *everything* with interrupts disabled,
|
||||
* ugh).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory Controller registers:
|
||||
*/
|
||||
#define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
|
||||
#define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
|
||||
#define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
|
||||
#define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
|
||||
#define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
|
||||
#define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
|
||||
#define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
|
||||
#define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
|
||||
#define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
|
||||
#define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
|
||||
#define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
|
||||
#define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
|
||||
#define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
|
||||
#define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
|
||||
#define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
|
||||
#define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
|
||||
#define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
|
||||
#define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
|
||||
#define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
|
||||
|
||||
/*
|
||||
* I/O Controller registers:
|
||||
*/
|
||||
#define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
|
||||
#define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
|
||||
#define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
|
||||
#define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
|
||||
#define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
|
||||
#define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
|
||||
#define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
|
||||
#define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
|
||||
#define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
|
||||
#define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
|
||||
#define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
|
||||
#define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
|
||||
#define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
|
||||
#define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
|
||||
#define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
|
||||
#define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
|
||||
#define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
|
||||
#define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
|
||||
#define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
|
||||
#define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
|
||||
#define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
|
||||
#define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
|
||||
|
||||
/*
|
||||
* Memory spaces:
|
||||
*/
|
||||
#define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
|
||||
#define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
|
||||
#define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
|
||||
#define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
|
||||
#define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
|
||||
|
||||
/*
|
||||
* Bit definitions for I/O Controller status register 0:
|
||||
*/
|
||||
#define LCA_IOC_STAT0_CMD 0xf
|
||||
#define LCA_IOC_STAT0_ERR (1<<4)
|
||||
#define LCA_IOC_STAT0_LOST (1<<5)
|
||||
#define LCA_IOC_STAT0_THIT (1<<6)
|
||||
#define LCA_IOC_STAT0_TREF (1<<7)
|
||||
#define LCA_IOC_STAT0_CODE_SHIFT 8
|
||||
#define LCA_IOC_STAT0_CODE_MASK 0x7
|
||||
#define LCA_IOC_STAT0_P_NBR_SHIFT 13
|
||||
#define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
|
||||
|
||||
#define LCA_HAE_ADDRESS LCA_IOC_HAE
|
||||
|
||||
/* LCA PMR Power Management register defines */
|
||||
#define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL)
|
||||
#define LCA_PMR_PDIV 0x7 /* Primary clock divisor */
|
||||
#define LCA_PMR_ODIV 0x38 /* Override clock divisor */
|
||||
#define LCA_PMR_INTO 0x40 /* Interrupt override */
|
||||
#define LCA_PMR_DMAO 0x80 /* DMA override */
|
||||
#define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */
|
||||
#define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */
|
||||
#define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L
|
||||
|
||||
/* LCA PMR Macros */
|
||||
|
||||
#define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR)
|
||||
#define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d))
|
||||
|
||||
#define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV)
|
||||
#define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV)
|
||||
#define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c)))
|
||||
|
||||
/* LCA PMR Divisor values */
|
||||
#define LCA_PMR_DIV_1 0x0
|
||||
#define LCA_PMR_DIV_1_5 0x1
|
||||
#define LCA_PMR_DIV_2 0x2
|
||||
#define LCA_PMR_DIV_4 0x3
|
||||
#define LCA_PMR_DIV_8 0x4
|
||||
#define LCA_PMR_DIV_16 0x5
|
||||
#define LCA_PMR_DIV_MIN DIV_1
|
||||
#define LCA_PMR_DIV_MAX DIV_16
|
||||
|
||||
|
||||
/*
|
||||
* Data structure for handling LCA machine checks. Correctable errors
|
||||
* result in a short logout frame, uncorrectable ones in a long one.
|
||||
*/
|
||||
struct el_lca_mcheck_short {
|
||||
struct el_common h; /* common logout header */
|
||||
unsigned long esr; /* error-status register */
|
||||
unsigned long ear; /* error-address register */
|
||||
unsigned long dc_stat; /* dcache status register */
|
||||
unsigned long ioc_stat0; /* I/O controller status register 0 */
|
||||
unsigned long ioc_stat1; /* I/O controller status register 1 */
|
||||
};
|
||||
|
||||
struct el_lca_mcheck_long {
|
||||
struct el_common h; /* common logout header */
|
||||
unsigned long pt[31]; /* PAL temps */
|
||||
unsigned long exc_addr; /* exception address */
|
||||
unsigned long pad1[3];
|
||||
unsigned long pal_base; /* PALcode base address */
|
||||
unsigned long hier; /* hw interrupt enable */
|
||||
unsigned long hirr; /* hw interrupt request */
|
||||
unsigned long mm_csr; /* MMU control & status */
|
||||
unsigned long dc_stat; /* data cache status */
|
||||
unsigned long dc_addr; /* data cache addr register */
|
||||
unsigned long abox_ctl; /* address box control register */
|
||||
unsigned long esr; /* error status register */
|
||||
unsigned long ear; /* error address register */
|
||||
unsigned long car; /* cache control register */
|
||||
unsigned long ioc_stat0; /* I/O controller status register 0 */
|
||||
unsigned long ioc_stat1; /* I/O controller status register 1 */
|
||||
unsigned long va; /* virtual address register */
|
||||
};
|
||||
|
||||
union el_lca {
|
||||
struct el_common * c;
|
||||
struct el_lca_mcheck_long * l;
|
||||
struct el_lca_mcheck_short * s;
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#ifndef __EXTERN_INLINE
|
||||
#define __EXTERN_INLINE extern inline
|
||||
#define __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O functions:
|
||||
*
|
||||
* Unlike Jensen, the Noname machines have no concept of local
|
||||
* I/O---everything goes over the PCI bus.
|
||||
*
|
||||
* There is plenty room for optimization here. In particular,
|
||||
* the Alpha's insb/insw/extb/extw should be useful in moving
|
||||
* data to/from the right byte-lanes.
|
||||
*/
|
||||
|
||||
#define vip volatile int __force *
|
||||
#define vuip volatile unsigned int __force *
|
||||
#define vulp volatile unsigned long __force *
|
||||
|
||||
#define LCA_SET_HAE \
|
||||
do { \
|
||||
if (addr >= (1UL << 24)) { \
|
||||
unsigned long msb = addr & 0xf8000000; \
|
||||
addr -= msb; \
|
||||
set_hae(msb); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
__EXTERN_INLINE unsigned int lca_ioread8(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= LCA_DENSE_MEM) {
|
||||
addr -= LCA_DENSE_MEM;
|
||||
LCA_SET_HAE;
|
||||
base_and_type = LCA_SPARSE_MEM + 0x00;
|
||||
} else {
|
||||
addr -= LCA_IO;
|
||||
base_and_type = LCA_IO + 0x00;
|
||||
}
|
||||
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extbl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= LCA_DENSE_MEM) {
|
||||
addr -= LCA_DENSE_MEM;
|
||||
LCA_SET_HAE;
|
||||
base_and_type = LCA_SPARSE_MEM + 0x00;
|
||||
} else {
|
||||
addr -= LCA_IO;
|
||||
base_and_type = LCA_IO + 0x00;
|
||||
}
|
||||
|
||||
w = __kernel_insbl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int lca_ioread16(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long result, base_and_type;
|
||||
|
||||
if (addr >= LCA_DENSE_MEM) {
|
||||
addr -= LCA_DENSE_MEM;
|
||||
LCA_SET_HAE;
|
||||
base_and_type = LCA_SPARSE_MEM + 0x08;
|
||||
} else {
|
||||
addr -= LCA_IO;
|
||||
base_and_type = LCA_IO + 0x08;
|
||||
}
|
||||
|
||||
result = *(vip) ((addr << 5) + base_and_type);
|
||||
return __kernel_extwl(result, addr & 3);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
unsigned long w, base_and_type;
|
||||
|
||||
if (addr >= LCA_DENSE_MEM) {
|
||||
addr -= LCA_DENSE_MEM;
|
||||
LCA_SET_HAE;
|
||||
base_and_type = LCA_SPARSE_MEM + 0x08;
|
||||
} else {
|
||||
addr -= LCA_IO;
|
||||
base_and_type = LCA_IO + 0x08;
|
||||
}
|
||||
|
||||
w = __kernel_inswl(b, addr & 3);
|
||||
*(vuip) ((addr << 5) + base_and_type) = w;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE unsigned int lca_ioread32(const void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < LCA_DENSE_MEM)
|
||||
addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
|
||||
return *(vuip)addr;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
|
||||
{
|
||||
unsigned long addr = (unsigned long) xaddr;
|
||||
if (addr < LCA_DENSE_MEM)
|
||||
addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
|
||||
*(vuip)addr = b;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)(addr + LCA_IO);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr,
|
||||
unsigned long size)
|
||||
{
|
||||
return (void __iomem *)(addr + LCA_DENSE_MEM);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return addr >= IDENT_ADDR + 0x120000000UL;
|
||||
}
|
||||
|
||||
__EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr)
|
||||
{
|
||||
return (unsigned long)addr >= LCA_DENSE_MEM;
|
||||
}
|
||||
|
||||
#undef vip
|
||||
#undef vuip
|
||||
#undef vulp
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX lca
|
||||
#define lca_trivial_rw_bw 2
|
||||
#define lca_trivial_rw_lq 1
|
||||
#define lca_trivial_io_bw 0
|
||||
#define lca_trivial_io_lq 0
|
||||
#define lca_trivial_iounmap 1
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#ifdef __IO_EXTERN_INLINE
|
||||
#undef __EXTERN_INLINE
|
||||
#undef __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_LCA__H__ */
|
||||
@ -1,378 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access
|
||||
*
|
||||
* This file is based on:
|
||||
*
|
||||
* Marvel / EV7 System Programmer's Manual
|
||||
* Revision 1.00
|
||||
* 14 May 2001
|
||||
*/
|
||||
|
||||
#ifndef __ALPHA_MARVEL__H__
|
||||
#define __ALPHA_MARVEL__H__
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/compiler.h>
|
||||
|
||||
#define MARVEL_MAX_PIDS 32 /* as long as we rely on 43-bit superpage */
|
||||
#define MARVEL_IRQ_VEC_PE_SHIFT (10)
|
||||
#define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1)
|
||||
#define MARVEL_NR_IRQS \
|
||||
(16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT)))
|
||||
|
||||
/*
|
||||
* EV7 RBOX Registers
|
||||
*/
|
||||
typedef struct {
|
||||
volatile unsigned long csr __attribute__((aligned(16)));
|
||||
} ev7_csr;
|
||||
|
||||
typedef struct {
|
||||
ev7_csr RBOX_CFG; /* 0x0000 */
|
||||
ev7_csr RBOX_NSVC;
|
||||
ev7_csr RBOX_EWVC;
|
||||
ev7_csr RBOX_WHAMI;
|
||||
ev7_csr RBOX_TCTL; /* 0x0040 */
|
||||
ev7_csr RBOX_INT;
|
||||
ev7_csr RBOX_IMASK;
|
||||
ev7_csr RBOX_IREQ;
|
||||
ev7_csr RBOX_INTQ; /* 0x0080 */
|
||||
ev7_csr RBOX_INTA;
|
||||
ev7_csr RBOX_IT;
|
||||
ev7_csr RBOX_SCRATCH1;
|
||||
ev7_csr RBOX_SCRATCH2; /* 0x00c0 */
|
||||
ev7_csr RBOX_L_ERR;
|
||||
} ev7_csrs;
|
||||
|
||||
/*
|
||||
* EV7 CSR addressing macros
|
||||
*/
|
||||
#define EV7_MASK40(addr) ((addr) & ((1UL << 41) - 1))
|
||||
#define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
|
||||
|
||||
#define EV7_PE_MASK 0x1ffUL /* 9 bits ( 256 + mem/io ) */
|
||||
#define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35)
|
||||
|
||||
#define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
|
||||
#define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL))
|
||||
|
||||
#define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))
|
||||
#define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))
|
||||
|
||||
#define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr)
|
||||
|
||||
/*
|
||||
* IO7 registers
|
||||
*/
|
||||
typedef struct {
|
||||
volatile unsigned long csr __attribute__((aligned(64)));
|
||||
} io7_csr;
|
||||
|
||||
typedef struct {
|
||||
/* I/O Port Control Registers */
|
||||
io7_csr POx_CTRL; /* 0x0000 */
|
||||
io7_csr POx_CACHE_CTL;
|
||||
io7_csr POx_TIMER;
|
||||
io7_csr POx_IO_ADR_EXT;
|
||||
io7_csr POx_MEM_ADR_EXT; /* 0x0100 */
|
||||
io7_csr POx_XCAL_CTRL;
|
||||
io7_csr rsvd1[2]; /* ?? spec doesn't show 0x180 */
|
||||
io7_csr POx_DM_SOURCE; /* 0x0200 */
|
||||
io7_csr POx_DM_DEST;
|
||||
io7_csr POx_DM_SIZE;
|
||||
io7_csr POx_DM_CTRL;
|
||||
io7_csr rsvd2[4]; /* 0x0300 */
|
||||
|
||||
/* AGP Control Registers -- port 3 only */
|
||||
io7_csr AGP_CAP_ID; /* 0x0400 */
|
||||
io7_csr AGP_STAT;
|
||||
io7_csr AGP_CMD;
|
||||
io7_csr rsvd3;
|
||||
|
||||
/* I/O Port Monitor Registers */
|
||||
io7_csr POx_MONCTL; /* 0x0500 */
|
||||
io7_csr POx_CTRA;
|
||||
io7_csr POx_CTRB;
|
||||
io7_csr POx_CTR56;
|
||||
io7_csr POx_SCRATCH; /* 0x0600 */
|
||||
io7_csr POx_XTRA_A;
|
||||
io7_csr POx_XTRA_TS;
|
||||
io7_csr POx_XTRA_Z;
|
||||
io7_csr rsvd4; /* 0x0700 */
|
||||
io7_csr POx_THRESHA;
|
||||
io7_csr POx_THRESHB;
|
||||
io7_csr rsvd5[33];
|
||||
|
||||
/* System Address Space Window Control Registers */
|
||||
|
||||
io7_csr POx_WBASE[4]; /* 0x1000 */
|
||||
io7_csr POx_WMASK[4];
|
||||
io7_csr POx_TBASE[4];
|
||||
io7_csr POx_SG_TBIA;
|
||||
io7_csr POx_MSI_WBASE;
|
||||
io7_csr rsvd6[50];
|
||||
|
||||
/* I/O Port Error Registers */
|
||||
io7_csr POx_ERR_SUM;
|
||||
io7_csr POx_FIRST_ERR;
|
||||
io7_csr POx_MSK_HEI;
|
||||
io7_csr POx_TLB_ERR;
|
||||
io7_csr POx_SPL_COMPLT;
|
||||
io7_csr POx_TRANS_SUM;
|
||||
io7_csr POx_FRC_PCI_ERR;
|
||||
io7_csr POx_MULT_ERR;
|
||||
io7_csr rsvd7[8];
|
||||
|
||||
/* I/O Port End of Interrupt Registers */
|
||||
io7_csr EOI_DAT;
|
||||
io7_csr rsvd8[7];
|
||||
io7_csr POx_IACK_SPECIAL;
|
||||
io7_csr rsvd9[103];
|
||||
} io7_ioport_csrs;
|
||||
|
||||
typedef struct {
|
||||
io7_csr IO_ASIC_REV; /* 0x30.0000 */
|
||||
io7_csr IO_SYS_REV;
|
||||
io7_csr SER_CHAIN3;
|
||||
io7_csr PO7_RST1;
|
||||
io7_csr PO7_RST2; /* 0x30.0100 */
|
||||
io7_csr POx_RST[4];
|
||||
io7_csr IO7_DWNH;
|
||||
io7_csr IO7_MAF;
|
||||
io7_csr IO7_MAF_TO;
|
||||
io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */
|
||||
io7_csr IO7_PMASK;
|
||||
io7_csr IO7_IOMASK;
|
||||
io7_csr IO7_UPH;
|
||||
io7_csr IO7_UPH_TO; /* 0x30.0400 */
|
||||
io7_csr RBX_IREQ_OFF;
|
||||
io7_csr RBX_INTA_OFF;
|
||||
io7_csr INT_RTY;
|
||||
io7_csr PO7_MONCTL; /* 0x30.0500 */
|
||||
io7_csr PO7_CTRA;
|
||||
io7_csr PO7_CTRB;
|
||||
io7_csr PO7_CTR56;
|
||||
io7_csr PO7_SCRATCH; /* 0x30.0600 */
|
||||
io7_csr PO7_XTRA_A;
|
||||
io7_csr PO7_XTRA_TS;
|
||||
io7_csr PO7_XTRA_Z;
|
||||
io7_csr PO7_PMASK; /* 0x30.0700 */
|
||||
io7_csr PO7_THRESHA;
|
||||
io7_csr PO7_THRESHB;
|
||||
io7_csr rsvd1[97];
|
||||
io7_csr PO7_ERROR_SUM; /* 0x30.2000 */
|
||||
io7_csr PO7_BHOLE_MASK;
|
||||
io7_csr PO7_HEI_MSK;
|
||||
io7_csr PO7_CRD_MSK;
|
||||
io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */
|
||||
io7_csr PO7_CRRCT_SYM;
|
||||
io7_csr PO7_ERR_PKT[2];
|
||||
io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */
|
||||
io7_csr rsbv2[887];
|
||||
io7_csr PO7_LSI_CTL[128]; /* 0x31.0000 */
|
||||
io7_csr rsvd3[123];
|
||||
io7_csr HLT_CTL; /* 0x31.3ec0 */
|
||||
io7_csr HPI_CTL; /* 0x31.3f00 */
|
||||
io7_csr CRD_CTL;
|
||||
io7_csr STV_CTL;
|
||||
io7_csr HEI_CTL;
|
||||
io7_csr PO7_MSI_CTL[16]; /* 0x31.4000 */
|
||||
io7_csr rsvd4[240];
|
||||
|
||||
/*
|
||||
* Interrupt Diagnostic / Test
|
||||
*/
|
||||
struct {
|
||||
io7_csr INT_PND;
|
||||
io7_csr INT_CLR;
|
||||
io7_csr INT_EOI;
|
||||
io7_csr rsvd[29];
|
||||
} INT_DIAG[4];
|
||||
io7_csr rsvd5[125]; /* 0x31.a000 */
|
||||
io7_csr MISC_PND; /* 0x31.b800 */
|
||||
io7_csr rsvd6[31];
|
||||
io7_csr MSI_PND[16]; /* 0x31.c000 */
|
||||
io7_csr rsvd7[16];
|
||||
io7_csr MSI_CLR[16]; /* 0x31.c800 */
|
||||
} io7_port7_csrs;
|
||||
|
||||
/*
|
||||
* IO7 DMA Window Base register (POx_WBASEx)
|
||||
*/
|
||||
#define wbase_m_ena 0x1
|
||||
#define wbase_m_sg 0x2
|
||||
#define wbase_m_dac 0x4
|
||||
#define wbase_m_addr 0xFFF00000
|
||||
union IO7_POx_WBASE {
|
||||
struct {
|
||||
unsigned ena : 1; /* <0> */
|
||||
unsigned sg : 1; /* <1> */
|
||||
unsigned dac : 1; /* <2> -- window 3 only */
|
||||
unsigned rsvd1 : 17;
|
||||
unsigned addr : 12; /* <31:20> */
|
||||
unsigned rsvd2 : 32;
|
||||
} bits;
|
||||
unsigned as_long[2];
|
||||
unsigned as_quad;
|
||||
};
|
||||
|
||||
/*
|
||||
* IO7 IID (Interrupt IDentifier) format
|
||||
*
|
||||
* For level-sensative interrupts, int_num is encoded as:
|
||||
*
|
||||
* bus/port slot/device INTx
|
||||
* <7:5> <4:2> <1:0>
|
||||
*/
|
||||
union IO7_IID {
|
||||
struct {
|
||||
unsigned int_num : 9; /* <8:0> */
|
||||
unsigned tpu_mask : 4; /* <12:9> rsvd */
|
||||
unsigned msi : 1; /* 13 */
|
||||
unsigned ipe : 10; /* <23:14> */
|
||||
unsigned long rsvd : 40;
|
||||
} bits;
|
||||
unsigned int as_long[2];
|
||||
unsigned long as_quad;
|
||||
};
|
||||
|
||||
/*
|
||||
* IO7 addressing macros
|
||||
*/
|
||||
#define IO7_KERN_ADDR(addr) (EV7_KERN_ADDR(addr))
|
||||
|
||||
#define IO7_PORT_MASK 0x07UL /* 3 bits of port */
|
||||
|
||||
#define IO7_IPE(pe) (EV7_IPE(pe))
|
||||
#define IO7_IPORT(port) ((~((long)(port)) & IO7_PORT_MASK) << 32)
|
||||
|
||||
#define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port))
|
||||
|
||||
#define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL)
|
||||
#define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL)
|
||||
#define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL)
|
||||
#define IO7_CSR_PHYS(pe, port, off) \
|
||||
(IO7_HOSE(pe, port) | 0xFF800000UL | (off))
|
||||
#define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL))
|
||||
#define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
|
||||
|
||||
#define IO7_MEM_KERN(pe, port) (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))
|
||||
#define IO7_CONF_KERN(pe, port) (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))
|
||||
#define IO7_IO_KERN(pe, port) (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))
|
||||
#define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))
|
||||
#define IO7_CSRS_KERN(pe, port) (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))
|
||||
#define IO7_PORT7_CSRS_KERN(pe) (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))
|
||||
|
||||
#define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7)
|
||||
#define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7)
|
||||
|
||||
#define IO7_MEM_SPACE (2UL * 1024 * 1024 * 1024) /* 2GB MEM */
|
||||
#define IO7_IO_SPACE (8UL * 1024 * 1024) /* 8MB I/O */
|
||||
|
||||
|
||||
/*
|
||||
* Offset between ram physical addresses and pci64 DAC addresses
|
||||
*/
|
||||
#define IO7_DAC_OFFSET (1UL << 49)
|
||||
|
||||
/*
|
||||
* This is needed to satisify the IO() macro used in initializing the machvec
|
||||
*/
|
||||
#define MARVEL_IACK_SC \
|
||||
((unsigned long) \
|
||||
(&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL)))
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* IO7 structs
|
||||
*/
|
||||
#define IO7_NUM_PORTS 4
|
||||
#define IO7_AGP_PORT 3
|
||||
|
||||
struct io7_port {
|
||||
struct io7 *io7;
|
||||
struct pci_controller *hose;
|
||||
|
||||
int enabled;
|
||||
unsigned int port;
|
||||
io7_ioport_csrs *csrs;
|
||||
|
||||
unsigned long saved_wbase[4];
|
||||
unsigned long saved_wmask[4];
|
||||
unsigned long saved_tbase[4];
|
||||
};
|
||||
|
||||
struct io7 {
|
||||
struct io7 *next;
|
||||
|
||||
unsigned int pe;
|
||||
io7_port7_csrs *csrs;
|
||||
struct io7_port ports[IO7_NUM_PORTS];
|
||||
|
||||
raw_spinlock_t irq_lock;
|
||||
};
|
||||
|
||||
#ifndef __EXTERN_INLINE
|
||||
# define __EXTERN_INLINE extern inline
|
||||
# define __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I/O functions. All access through linear space.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory functions. All accesses through linear space.
|
||||
*/
|
||||
|
||||
#define vucp volatile unsigned char __force *
|
||||
#define vusp volatile unsigned short __force *
|
||||
|
||||
extern unsigned int marvel_ioread8(const void __iomem *);
|
||||
extern void marvel_iowrite8(u8 b, void __iomem *);
|
||||
|
||||
__EXTERN_INLINE unsigned int marvel_ioread16(const void __iomem *addr)
|
||||
{
|
||||
return __kernel_ldwu(*(vusp)addr);
|
||||
}
|
||||
|
||||
__EXTERN_INLINE void marvel_iowrite16(u16 b, void __iomem *addr)
|
||||
{
|
||||
__kernel_stw(b, *(vusp)addr);
|
||||
}
|
||||
|
||||
extern void __iomem *marvel_ioremap(unsigned long addr, unsigned long size);
|
||||
extern void marvel_iounmap(volatile void __iomem *addr);
|
||||
extern void __iomem *marvel_ioportmap (unsigned long addr);
|
||||
|
||||
__EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr)
|
||||
{
|
||||
return (addr >> 40) & 1;
|
||||
}
|
||||
|
||||
extern int marvel_is_mmio(const volatile void __iomem *);
|
||||
|
||||
#undef vucp
|
||||
#undef vusp
|
||||
|
||||
#undef __IO_PREFIX
|
||||
#define __IO_PREFIX marvel
|
||||
#define marvel_trivial_rw_bw 1
|
||||
#define marvel_trivial_rw_lq 1
|
||||
#define marvel_trivial_io_bw 0
|
||||
#define marvel_trivial_io_lq 1
|
||||
#define marvel_trivial_iounmap 0
|
||||
#include <asm/io_trivial.h>
|
||||
|
||||
#ifdef __IO_EXTERN_INLINE
|
||||
# undef __EXTERN_INLINE
|
||||
# undef __IO_EXTERN_INLINE
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_MARVEL__H__ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user