From 4da0de7e0f8440bd9c8b14a19f4b07f4cbe51612 Mon Sep 17 00:00:00 2001 From: "Raziel K. Crowe" <101006007+RazielCrowe@users.noreply.github.com> Date: Fri, 9 Sep 2022 14:11:12 +0500 Subject: [PATCH] redo --- ...Technical_Reference_Manual-r1p0-00rel0.pdf | Bin 354303 -> 0 bytes .../verilog/herculesae_vx_aes.sv | 246 - .../verilog/herculesae_vx_aesd1.sv | 307 - .../verilog/herculesae_vx_aese1.sv | 158 - .../verilog/herculesae_vx_aesed2.sv | 610 -- .../verilog/herculesae_vx_aesed2_lut.sv | 93 - .../verilog/herculesae_vx_aesimc.sv | 234 - .../verilog/herculesae_vx_aesinv.sv | 517 -- .../verilog/herculesae_vx_aesmc.sv | 186 - .../verilog/herculesae_vx_crypt.sv | 966 -- .../verilog/herculesae_vx_pmull.sv | 257 - .../verilog/herculesae_vx_sha1.sv | 78 - .../verilog/herculesae_vx_sha1cpm.sv | 101 - .../verilog/herculesae_vx_sha256h32.sv | 104 - .../verilog/herculesae_vx_sha256su0.sv | 76 - .../verilog/herculesae_vx_sha256su1.sv | 90 - .../logical/maia/verilog/MAIA.v | 4802 ---------- .../logical/maia/verilog/MAIA_feq20.v | 4801 ---------- .../logical/maia/verilog/MAIA_feq20_s.v | 4821 ---------- .../logical/maia/verilog/MAIA_feq28.v | 4801 ---------- .../logical/maia/verilog/MAIA_feq28_s.v | 4821 ---------- .../logical/maia/verilog/MAIA_s.v | 4821 ---------- .../logical/maia/verilog/maia_noncpu.v | 7931 ---------------- .../logical/maia/verilog/maia_noncpu_feq20.v | 7934 ---------------- .../maia/verilog/maia_noncpu_feq20_s.v | 7951 ---------------- .../logical/maia/verilog/maia_noncpu_feq28.v | 7934 ---------------- .../maia/verilog/maia_noncpu_feq28_s.v | 7951 ---------------- .../logical/maia/verilog/maia_noncpu_s.v | 7952 ----------------- .../maia_complex/verilog/maia_complex.v | 2816 ------ .../maia_complex/verilog/maia_cx_crypt2.v | 351 - .../maia_complex/verilog/maia_cx_crypt3.v | 713 -- .../tests/aarch32/crypto/Makefile.inc | 67 - .../tests/aarch32/crypto/crypto.elf | Bin 326256 -> 0 bytes .../aarch32/crypto/crypto_aarch32el0.elf | Bin 283720 -> 0 bytes .../tests/aarch32/crypto/crypto_functions.s | 212 - .../tests/aarch64/crypto/Makefile.inc | 63 - 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23 - rdp-acceleraed/.gitignore | 18 - rdp-acceleraed/LICENSE | 21 - rdp-acceleraed/README.md | 71 - rdp-acceleraed/RPI-Client/CMakeLists.txt | 11 - rdp-acceleraed/RPI-Client/client.cpp | 371 - rdp-acceleraed/RPI-Client/events.cpp | 71 - rdp-acceleraed/RPI-Client/mouse.h | 127 - rdp-acceleraed/Server/CMakeLists.txt | 121 - rdp-acceleraed/Server/Capture.h | 8 - rdp-acceleraed/Server/FFMPEG_encoding.hpp | 194 - rdp-acceleraed/Server/FindDirectX.cmake | 31 - rdp-acceleraed/Server/GDICapture.h | 63 - rdp-acceleraed/Server/NV_encoding.hpp | 100 - rdp-acceleraed/Server/NvEncoder/NvEncoder.h | 503 -- .../Server/NvEncoder/NvHWEncoder.cpp | 1268 --- rdp-acceleraed/Server/NvEncoder/NvHWEncoder.h | 202 - rdp-acceleraed/Server/NvEncoder/nvCPUOPSys.h | 28 - rdp-acceleraed/Server/NvEncoder/nvEncodeAPI.h | 2965 ------ rdp-acceleraed/Server/NvEncoder/nvFileIO.h | 177 - rdp-acceleraed/Server/NvEncoder/nvUtils.h | 127 - rdp-acceleraed/Server/WDDMCapture.h | 40 - rdp-acceleraed/Server/bounded_buffer.h | 53 - rdp-acceleraed/Server/color_conversion.cu | 100 - rdp-acceleraed/Server/color_conversion.h | 1 - rdp-acceleraed/Server/config.h.in | 4 - rdp-acceleraed/Server/fps.h | 43 - rdp-acceleraed/Server/monitor.h | 19 - rdp-acceleraed/Server/params.h | 38 - rdp-acceleraed/Server/server.cpp | 278 - rdp-acceleraed/Server/wddm.h | 405 - rdp-acceleraed/WindowsCompileGuide.md | 49 - rdp-acceleraed/win8-wddm/win8-wddm.sln | 20 - rdp-acceleraed/win8-wddm/win8-wddm/main.cpp | 30 - rdp-acceleraed/win8-wddm/win8-wddm/wddm.h | 383 - .../win8-wddm/win8-wddm.vcxproj.filters | 27 - temp-telegraf/README.md | 37 - temp-telegraf/telegraf.conf | 5 - temp-telegraf/telegraf_pi_temp.sh | 7 - 98 files changed, 3910 insertions(+), 96509 deletions(-) delete mode 100644 Security Algo Accelerator/docs/Cortex_A72_MPCore_Cryptography_Technical_Reference_Manual-r1p0-00rel0.pdf delete mode 100644 Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv delete mode 100644 Security Algo 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zvuDFgur}fm%oQI&0xkN2xRf6}}!rv(LYS5_cPb?*~yFIRVAgNWdk!L~7* z<4##O33A__>6ar9s+?1WkhUDr?8mAK3g;GO5(CmkT;Yh*oHJ1l#}?H^RVV8THXJf% z#4e(TT2PBkwp}zu7X8K9-P?dgO1Up}u`q+x!?13ZN^|&{q7&ras&ps}{BniHPLMhPxLwF?yEai*kZU|OnIQwEVxXFdOo`x+m5fp%V6&|?-kqy5Sk6~mXJ&M ntRKLyB&$LHw`p;4HF9?KbT%`GVPRuoVrPXRBNI~)hllweEQg+c diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv deleted file mode 100644 index c7d99fa383..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv +++ /dev/null @@ -1,246 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aes -( - - - input wire clk, - input wire reset, - input wire ival_v1_q, - - input wire aesd_v1_q, - input wire aese_v1_q, - input wire aesd_or_e_v1_q, - input wire aesmc_v1_q, - input wire aesimc_v1_q, - input wire aesdimc_v1_q, - input wire aesemc_v1_q, - - input wire [127:0] opa_v1, - input wire [127:0] opb_v1, - - output wire [127:0] aesout_v2 -); - - - - - - - - wire [15:0] aes_shf_v1; - wire [127:0] aesd_out_v2; - wire [15:0] aesd_shf_v1; - wire [127:0] aesd_v1; - reg aesdimc_h_v2_q; - reg aesdimc_l_v2_q; - wire [127:0] aesdimc_out_v2; - wire [127:0] aese_out_v2; - wire [15:0] aese_shf_v1; - wire [127:0] aese_v1; - wire [127:0] aesed_lut_in_v1; - wire [127:0] aesed_lut_out_v1; - reg aesemc_h_v2_q; - reg aesemc_l_v2_q; - wire [127:0] aesemc_out_v2; - reg aesimc_h_v2_q; - reg aesimc_l_v2_q; - wire [127:0] aesimc_out_v2; - reg aesmc_h_v2_q; - reg aesmc_l_v2_q; - wire [127:0] aesmc_out_v2; - wire block_opa_passthrough; - wire [127:0] opa_aes_nxt_v1; - reg [127:0] opa_aes_v2_q; - wire [127:0] qx_v1; - reg sel_aesd_h_v2_q; - reg sel_aesd_l_v2_q; - wire sel_aesd_v1; - reg sel_aese_h_v2_q; - reg sel_aese_l_v2_q; - wire sel_aese_v1; - - - assign sel_aesd_v1 = aesd_v1_q & ~aesdimc_v1_q; - assign sel_aese_v1 = aese_v1_q & ~aesemc_v1_q; - - assign block_opa_passthrough = aesd_or_e_v1_q; - - - always_ff @(posedge clk or posedge reset) - begin: u_aesmc_h_v2_q_grp - if (reset == 1'b1) begin - aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) begin - aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q; - aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q; - aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q; - aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q; - aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q; - aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q; - aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q; - aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q; - sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1; - sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1; - sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1; - sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1; - end - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else begin - aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - end -`else - else if (ival_v1_q == 1'b1) begin - aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q; - aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q; - aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q; - aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q; - aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q; - aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q; - aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q; - aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q; - sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1; - sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1; - sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1; - sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1; - end -`endif - end - - - - assign qx_v1[127:0] = {128{aesd_or_e_v1_q}} & (opb_v1[127:0] ^ opa_v1[127:0]); - - herculesae_vx_aese1 u_aese1( - .q (qx_v1[127:0]), - .aese_out (aese_v1[127:0]), - .aese_shf (aese_shf_v1[15:0])); - - herculesae_vx_aesd1 u_aesd1( - .q (qx_v1[127:0]), - .aesd_out (aesd_v1[127:0]), - .aesd_shf (aesd_shf_v1[15:0])); - - assign aes_shf_v1[15:0] = {16{aese_v1_q}} & aese_shf_v1[15:0] | - {16{aesd_v1_q}} & aesd_shf_v1[15:0]; - - assign aesed_lut_in_v1[127:0] = ({128{aese_v1_q}} & aese_v1[127:0]) | ({128{aesd_v1_q}} & aesd_v1[127:0]); - - herculesae_vx_aesed2_lut u_aesed2_lut_v1( - .lut_in (aesed_lut_in_v1[127:0]), - .lut_out (aesed_lut_out_v1[127:0])); - - assign opa_aes_nxt_v1[127:0] = ({128{aesd_or_e_v1_q}} & aesed_lut_out_v1[127:0]) - | ({128{~block_opa_passthrough}} & opa_v1[127:0]); - - - always_ff @(posedge clk or posedge reset) - begin: u_opa_aes_v2_q_127_0 - if (reset == 1'b1) - opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) - opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0]; - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else - opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; -`else - else if (ival_v1_q == 1'b1) - opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0]; -`endif - end - - - - herculesae_vx_aesmc u_aesmc( - .d_in (opa_aes_v2_q[127:0]), - .mc (aesmc_out_v2[127:0])); - - herculesae_vx_aesimc u_aesimc( - .d_in (opa_aes_v2_q[127:0]), - .imc (aesimc_out_v2[127:0])); - - herculesae_vx_aesed2 u_aesed2( - .clk (clk), - .reset (reset), - .ival_v1_q (ival_v1_q), - .aes_din_v1 (aesed_lut_out_v1[127:0]), - .aes_shf_v1 (aes_shf_v1[15:0]), - .aesd_out (aesd_out_v2[127:0]), - .aese_out (aese_out_v2[127:0]), - .aesemc_out (aesemc_out_v2[127:0]), - .aesdimc_out (aesdimc_out_v2[127:0])); - - assign aesout_v2[127:64] = ({64{sel_aesd_h_v2_q}} & aesd_out_v2[127:64]) - | ({64{sel_aese_h_v2_q}} & aese_out_v2[127:64]) - | ({64{aesmc_h_v2_q}} & aesmc_out_v2[127:64]) - | ({64{aesemc_h_v2_q}} & aesemc_out_v2[127:64]) - | ({64{aesimc_h_v2_q}} & aesimc_out_v2[127:64]) - | ({64{aesdimc_h_v2_q}} & aesdimc_out_v2[127:64]); - - assign aesout_v2[63:0] = ({64{sel_aesd_l_v2_q}} & aesd_out_v2[63:0]) - | ({64{sel_aese_l_v2_q}} & aese_out_v2[63:0]) - | ({64{aesmc_l_v2_q}} & aesmc_out_v2[63:0]) - | ({64{aesemc_l_v2_q}} & aesemc_out_v2[63:0]) - | ({64{aesimc_l_v2_q}} & aesimc_out_v2[63:0]) - | ({64{aesdimc_l_v2_q}} & aesdimc_out_v2[63:0]); - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesd1.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesd1.sv deleted file mode 100644 index 17062c9dc3..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesd1.sv +++ /dev/null @@ -1,307 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesd1 -( - - - input wire [127:0] q, - - output wire [127:0] aesd_out, - output wire [15:0] aesd_shf -); - - - - - - - - wire [127:0] aesd_noshf; - wire [7:0] s00; - wire [7:0] s01; - wire [7:0] s02; - wire [7:0] s03; - wire [7:0] s10; - wire [7:0] s11; - wire [7:0] s12; - wire [7:0] s13; - wire [7:0] s20; - wire [7:0] s21; - wire [7:0] s22; - wire [7:0] s23; - wire [7:0] s30; - wire [7:0] s31; - wire [7:0] s32; - wire [7:0] s33; - wire [7:0] sp00; - wire [7:0] sp01; - wire [7:0] sp02; - wire [7:0] sp03; - wire [7:0] sp10; - wire [7:0] sp11; - wire [7:0] sp12; - wire [7:0] sp13; - wire [7:0] sp20; - wire [7:0] sp21; - wire [7:0] sp22; - wire [7:0] sp23; - wire [7:0] sp30; - wire [7:0] sp31; - wire [7:0] sp32; - wire [7:0] sp33; - - - -assign s33[7:0] = q[127:120]; -assign s23[7:0] = q[119:112]; -assign s13[7:0] = q[111:104]; -assign s03[7:0] = q[103:96]; - -assign s32[7:0] = q[95:88]; -assign s22[7:0] = q[87:80]; -assign s12[7:0] = q[79:72]; -assign s02[7:0] = q[71:64]; - -assign s31[7:0] = q[63:56]; -assign s21[7:0] = q[55:48]; -assign s11[7:0] = q[47:40]; -assign s01[7:0] = q[39:32]; - -assign s30[7:0] = q[31:24]; -assign s20[7:0] = q[23:16]; -assign s10[7:0] = q[15:8]; -assign s00[7:0] = q[7:0]; - - -assign sp00[7:0] = s00[7:0]; -assign sp01[7:0] = s01[7:0]; -assign sp02[7:0] = s02[7:0]; -assign sp03[7:0] = s03[7:0]; - -assign sp10[7:0] = s13[7:0]; -assign sp11[7:0] = s10[7:0]; -assign sp12[7:0] = s11[7:0]; -assign sp13[7:0] = s12[7:0]; - -assign sp20[7:0] = s22[7:0]; -assign sp21[7:0] = s23[7:0]; -assign sp22[7:0] = s20[7:0]; -assign sp23[7:0] = s21[7:0]; - -assign sp30[7:0] = s31[7:0]; -assign sp31[7:0] = s32[7:0]; -assign sp32[7:0] = s33[7:0]; -assign sp33[7:0] = s30[7:0]; - - -assign aesd_noshf[0] = sp00[2] ^ sp00[5] ^ sp00[7] ^ 1'b1; -assign aesd_noshf[1] = sp00[0] ^ sp00[3] ^ sp00[6] ^ 1'b0; -assign aesd_noshf[2] = sp00[1] ^ sp00[4] ^ sp00[7] ^ 1'b1; -assign aesd_noshf[3] = sp00[0] ^ sp00[2] ^ sp00[5] ^ 1'b0; -assign aesd_noshf[4] = sp00[1] ^ sp00[3] ^ sp00[6] ^ 1'b0; -assign aesd_noshf[5] = sp00[2] ^ sp00[4] ^ sp00[7] ^ 1'b0; -assign aesd_noshf[6] = sp00[0] ^ sp00[3] ^ sp00[5] ^ 1'b0; -assign aesd_noshf[7] = sp00[1] ^ sp00[4] ^ sp00[6] ^ 1'b0; -assign aesd_noshf[32] = sp01[2] ^ sp01[5] ^ sp01[7] ^ 1'b1; -assign aesd_noshf[33] = sp01[0] ^ sp01[3] ^ sp01[6] ^ 1'b0; -assign aesd_noshf[34] = sp01[1] ^ sp01[4] ^ sp01[7] ^ 1'b1; -assign aesd_noshf[35] = sp01[0] ^ sp01[2] ^ sp01[5] ^ 1'b0; -assign aesd_noshf[36] = sp01[1] ^ sp01[3] ^ sp01[6] ^ 1'b0; -assign aesd_noshf[37] = sp01[2] ^ sp01[4] ^ sp01[7] ^ 1'b0; -assign aesd_noshf[38] = sp01[0] ^ sp01[3] ^ sp01[5] ^ 1'b0; -assign aesd_noshf[39] = sp01[1] ^ sp01[4] ^ sp01[6] ^ 1'b0; -assign aesd_noshf[64] = sp02[2] ^ sp02[5] ^ sp02[7] ^ 1'b1; -assign aesd_noshf[65] = sp02[0] ^ sp02[3] ^ sp02[6] ^ 1'b0; -assign aesd_noshf[66] = sp02[1] ^ sp02[4] ^ sp02[7] ^ 1'b1; -assign aesd_noshf[67] = sp02[0] ^ sp02[2] ^ sp02[5] ^ 1'b0; -assign aesd_noshf[68] = sp02[1] ^ sp02[3] ^ sp02[6] ^ 1'b0; -assign aesd_noshf[69] = sp02[2] ^ sp02[4] ^ sp02[7] ^ 1'b0; -assign aesd_noshf[70] = sp02[0] ^ sp02[3] ^ sp02[5] ^ 1'b0; -assign aesd_noshf[71] = sp02[1] ^ sp02[4] ^ sp02[6] ^ 1'b0; -assign aesd_noshf[96] = sp03[2] ^ sp03[5] ^ sp03[7] ^ 1'b1; -assign aesd_noshf[97] = sp03[0] ^ sp03[3] ^ sp03[6] ^ 1'b0; -assign aesd_noshf[98] = sp03[1] ^ sp03[4] ^ sp03[7] ^ 1'b1; -assign aesd_noshf[99] = sp03[0] ^ sp03[2] ^ sp03[5] ^ 1'b0; -assign aesd_noshf[100] = sp03[1] ^ sp03[3] ^ sp03[6] ^ 1'b0; -assign aesd_noshf[101] = sp03[2] ^ sp03[4] ^ sp03[7] ^ 1'b0; -assign aesd_noshf[102] = sp03[0] ^ sp03[3] ^ sp03[5] ^ 1'b0; -assign aesd_noshf[103] = sp03[1] ^ sp03[4] ^ sp03[6] ^ 1'b0; - -assign aesd_noshf[8] = sp10[2] ^ sp10[5] ^ sp10[7] ^ 1'b1; -assign aesd_noshf[9] = sp10[0] ^ sp10[3] ^ sp10[6] ^ 1'b0; -assign aesd_noshf[10] = sp10[1] ^ sp10[4] ^ sp10[7] ^ 1'b1; -assign aesd_noshf[11] = sp10[0] ^ sp10[2] ^ sp10[5] ^ 1'b0; -assign aesd_noshf[12] = sp10[1] ^ sp10[3] ^ sp10[6] ^ 1'b0; -assign aesd_noshf[13] = sp10[2] ^ sp10[4] ^ sp10[7] ^ 1'b0; -assign aesd_noshf[14] = sp10[0] ^ sp10[3] ^ sp10[5] ^ 1'b0; -assign aesd_noshf[15] = sp10[1] ^ sp10[4] ^ sp10[6] ^ 1'b0; -assign aesd_noshf[40] = sp11[2] ^ sp11[5] ^ sp11[7] ^ 1'b1; -assign aesd_noshf[41] = sp11[0] ^ sp11[3] ^ sp11[6] ^ 1'b0; -assign aesd_noshf[42] = sp11[1] ^ sp11[4] ^ sp11[7] ^ 1'b1; -assign aesd_noshf[43] = sp11[0] ^ sp11[2] ^ sp11[5] ^ 1'b0; -assign aesd_noshf[44] = sp11[1] ^ sp11[3] ^ sp11[6] ^ 1'b0; -assign aesd_noshf[45] = sp11[2] ^ sp11[4] ^ sp11[7] ^ 1'b0; -assign aesd_noshf[46] = sp11[0] ^ sp11[3] ^ sp11[5] ^ 1'b0; -assign aesd_noshf[47] = sp11[1] ^ sp11[4] ^ sp11[6] ^ 1'b0; -assign aesd_noshf[72] = sp12[2] ^ sp12[5] ^ sp12[7] ^ 1'b1; -assign aesd_noshf[73] = sp12[0] ^ sp12[3] ^ sp12[6] ^ 1'b0; -assign aesd_noshf[74] = sp12[1] ^ sp12[4] ^ sp12[7] ^ 1'b1; -assign aesd_noshf[75] = sp12[0] ^ sp12[2] ^ sp12[5] ^ 1'b0; -assign aesd_noshf[76] = sp12[1] ^ sp12[3] ^ sp12[6] ^ 1'b0; -assign aesd_noshf[77] = sp12[2] ^ sp12[4] ^ sp12[7] ^ 1'b0; -assign aesd_noshf[78] = sp12[0] ^ sp12[3] ^ sp12[5] ^ 1'b0; -assign aesd_noshf[79] = sp12[1] ^ sp12[4] ^ sp12[6] ^ 1'b0; -assign aesd_noshf[104] = sp13[2] ^ sp13[5] ^ sp13[7] ^ 1'b1; -assign aesd_noshf[105] = sp13[0] ^ sp13[3] ^ sp13[6] ^ 1'b0; -assign aesd_noshf[106] = sp13[1] ^ sp13[4] ^ sp13[7] ^ 1'b1; -assign aesd_noshf[107] = sp13[0] ^ sp13[2] ^ sp13[5] ^ 1'b0; -assign aesd_noshf[108] = sp13[1] ^ sp13[3] ^ sp13[6] ^ 1'b0; -assign aesd_noshf[109] = sp13[2] ^ sp13[4] ^ sp13[7] ^ 1'b0; -assign aesd_noshf[110] = sp13[0] ^ sp13[3] ^ sp13[5] ^ 1'b0; -assign aesd_noshf[111] = sp13[1] ^ sp13[4] ^ sp13[6] ^ 1'b0; - -assign aesd_noshf[16] = sp20[2] ^ sp20[5] ^ sp20[7] ^ 1'b1; -assign aesd_noshf[17] = sp20[0] ^ sp20[3] ^ sp20[6] ^ 1'b0; -assign aesd_noshf[18] = sp20[1] ^ sp20[4] ^ sp20[7] ^ 1'b1; -assign aesd_noshf[19] = sp20[0] ^ sp20[2] ^ sp20[5] ^ 1'b0; -assign aesd_noshf[20] = sp20[1] ^ sp20[3] ^ sp20[6] ^ 1'b0; -assign aesd_noshf[21] = sp20[2] ^ sp20[4] ^ sp20[7] ^ 1'b0; -assign aesd_noshf[22] = sp20[0] ^ sp20[3] ^ sp20[5] ^ 1'b0; -assign aesd_noshf[23] = sp20[1] ^ sp20[4] ^ sp20[6] ^ 1'b0; -assign aesd_noshf[48] = sp21[2] ^ sp21[5] ^ sp21[7] ^ 1'b1; -assign aesd_noshf[49] = sp21[0] ^ sp21[3] ^ sp21[6] ^ 1'b0; -assign aesd_noshf[50] = sp21[1] ^ sp21[4] ^ sp21[7] ^ 1'b1; -assign aesd_noshf[51] = sp21[0] ^ sp21[2] ^ sp21[5] ^ 1'b0; -assign aesd_noshf[52] = sp21[1] ^ sp21[3] ^ sp21[6] ^ 1'b0; -assign aesd_noshf[53] = sp21[2] ^ sp21[4] ^ sp21[7] ^ 1'b0; -assign aesd_noshf[54] = sp21[0] ^ sp21[3] ^ sp21[5] ^ 1'b0; -assign aesd_noshf[55] = sp21[1] ^ sp21[4] ^ sp21[6] ^ 1'b0; -assign aesd_noshf[80] = sp22[2] ^ sp22[5] ^ sp22[7] ^ 1'b1; -assign aesd_noshf[81] = sp22[0] ^ sp22[3] ^ sp22[6] ^ 1'b0; -assign aesd_noshf[82] = sp22[1] ^ sp22[4] ^ sp22[7] ^ 1'b1; -assign aesd_noshf[83] = sp22[0] ^ sp22[2] ^ sp22[5] ^ 1'b0; -assign aesd_noshf[84] = sp22[1] ^ sp22[3] ^ sp22[6] ^ 1'b0; -assign aesd_noshf[85] = sp22[2] ^ sp22[4] ^ sp22[7] ^ 1'b0; -assign aesd_noshf[86] = sp22[0] ^ sp22[3] ^ sp22[5] ^ 1'b0; -assign aesd_noshf[87] = sp22[1] ^ sp22[4] ^ sp22[6] ^ 1'b0; -assign aesd_noshf[112] = sp23[2] ^ sp23[5] ^ sp23[7] ^ 1'b1; -assign aesd_noshf[113] = sp23[0] ^ sp23[3] ^ sp23[6] ^ 1'b0; -assign aesd_noshf[114] = sp23[1] ^ sp23[4] ^ sp23[7] ^ 1'b1; -assign aesd_noshf[115] = sp23[0] ^ sp23[2] ^ sp23[5] ^ 1'b0; -assign aesd_noshf[116] = sp23[1] ^ sp23[3] ^ sp23[6] ^ 1'b0; -assign aesd_noshf[117] = sp23[2] ^ sp23[4] ^ sp23[7] ^ 1'b0; -assign aesd_noshf[118] = sp23[0] ^ sp23[3] ^ sp23[5] ^ 1'b0; -assign aesd_noshf[119] = sp23[1] ^ sp23[4] ^ sp23[6] ^ 1'b0; - -assign aesd_noshf[24] = sp30[2] ^ sp30[5] ^ sp30[7] ^ 1'b1; -assign aesd_noshf[25] = sp30[0] ^ sp30[3] ^ sp30[6] ^ 1'b0; -assign aesd_noshf[26] = sp30[1] ^ sp30[4] ^ sp30[7] ^ 1'b1; -assign aesd_noshf[27] = sp30[0] ^ sp30[2] ^ sp30[5] ^ 1'b0; -assign aesd_noshf[28] = sp30[1] ^ sp30[3] ^ sp30[6] ^ 1'b0; -assign aesd_noshf[29] = sp30[2] ^ sp30[4] ^ sp30[7] ^ 1'b0; -assign aesd_noshf[30] = sp30[0] ^ sp30[3] ^ sp30[5] ^ 1'b0; -assign aesd_noshf[31] = sp30[1] ^ sp30[4] ^ sp30[6] ^ 1'b0; -assign aesd_noshf[56] = sp31[2] ^ sp31[5] ^ sp31[7] ^ 1'b1; -assign aesd_noshf[57] = sp31[0] ^ sp31[3] ^ sp31[6] ^ 1'b0; -assign aesd_noshf[58] = sp31[1] ^ sp31[4] ^ sp31[7] ^ 1'b1; -assign aesd_noshf[59] = sp31[0] ^ sp31[2] ^ sp31[5] ^ 1'b0; -assign aesd_noshf[60] = sp31[1] ^ sp31[3] ^ sp31[6] ^ 1'b0; -assign aesd_noshf[61] = sp31[2] ^ sp31[4] ^ sp31[7] ^ 1'b0; -assign aesd_noshf[62] = sp31[0] ^ sp31[3] ^ sp31[5] ^ 1'b0; -assign aesd_noshf[63] = sp31[1] ^ sp31[4] ^ sp31[6] ^ 1'b0; -assign aesd_noshf[88] = sp32[2] ^ sp32[5] ^ sp32[7] ^ 1'b1; -assign aesd_noshf[89] = sp32[0] ^ sp32[3] ^ sp32[6] ^ 1'b0; -assign aesd_noshf[90] = sp32[1] ^ sp32[4] ^ sp32[7] ^ 1'b1; -assign aesd_noshf[91] = sp32[0] ^ sp32[2] ^ sp32[5] ^ 1'b0; -assign aesd_noshf[92] = sp32[1] ^ sp32[3] ^ sp32[6] ^ 1'b0; -assign aesd_noshf[93] = sp32[2] ^ sp32[4] ^ sp32[7] ^ 1'b0; -assign aesd_noshf[94] = sp32[0] ^ sp32[3] ^ sp32[5] ^ 1'b0; -assign aesd_noshf[95] = sp32[1] ^ sp32[4] ^ sp32[6] ^ 1'b0; -assign aesd_noshf[120] = sp33[2] ^ sp33[5] ^ sp33[7] ^ 1'b1; -assign aesd_noshf[121] = sp33[0] ^ sp33[3] ^ sp33[6] ^ 1'b0; -assign aesd_noshf[122] = sp33[1] ^ sp33[4] ^ sp33[7] ^ 1'b1; -assign aesd_noshf[123] = sp33[0] ^ sp33[2] ^ sp33[5] ^ 1'b0; -assign aesd_noshf[124] = sp33[1] ^ sp33[3] ^ sp33[6] ^ 1'b0; -assign aesd_noshf[125] = sp33[2] ^ sp33[4] ^ sp33[7] ^ 1'b0; -assign aesd_noshf[126] = sp33[0] ^ sp33[3] ^ sp33[5] ^ 1'b0; -assign aesd_noshf[127] = sp33[1] ^ sp33[4] ^ sp33[6] ^ 1'b0; - -assign aesd_shf[15] = ~aesd_noshf[127]; -assign aesd_shf[14] = ~aesd_noshf[119]; -assign aesd_shf[13] = ~aesd_noshf[111]; -assign aesd_shf[12] = ~aesd_noshf[103]; -assign aesd_shf[11] = ~aesd_noshf[ 95]; -assign aesd_shf[10] = ~aesd_noshf[ 87]; -assign aesd_shf[ 9] = ~aesd_noshf[ 79]; -assign aesd_shf[ 8] = ~aesd_noshf[ 71]; -assign aesd_shf[ 7] = ~aesd_noshf[ 63]; -assign aesd_shf[ 6] = ~aesd_noshf[ 55]; -assign aesd_shf[ 5] = ~aesd_noshf[ 47]; -assign aesd_shf[ 4] = ~aesd_noshf[ 39]; -assign aesd_shf[ 3] = ~aesd_noshf[ 31]; -assign aesd_shf[ 2] = ~aesd_noshf[ 23]; -assign aesd_shf[ 1] = ~aesd_noshf[ 15]; -assign aesd_shf[ 0] = ~aesd_noshf[ 7]; - -assign aesd_out[127:120] = {8{ aesd_shf[15]}} & {aesd_noshf[126:120], 1'b0} | - {8{~aesd_shf[15]}} & aesd_noshf[127:120]; -assign aesd_out[119:112] = {8{ aesd_shf[14]}} & {aesd_noshf[118:112], 1'b0} | - {8{~aesd_shf[14]}} & aesd_noshf[119:112]; -assign aesd_out[111:104] = {8{ aesd_shf[13]}} & {aesd_noshf[110:104], 1'b0} | - {8{~aesd_shf[13]}} & aesd_noshf[111:104]; -assign aesd_out[103: 96] = {8{ aesd_shf[12]}} & {aesd_noshf[102: 96], 1'b0} | - {8{~aesd_shf[12]}} & aesd_noshf[103: 96]; -assign aesd_out[ 95: 88] = {8{ aesd_shf[11]}} & {aesd_noshf[ 94: 88], 1'b0} | - {8{~aesd_shf[11]}} & aesd_noshf[ 95: 88]; -assign aesd_out[ 87: 80] = {8{ aesd_shf[10]}} & {aesd_noshf[ 86: 80], 1'b0} | - {8{~aesd_shf[10]}} & aesd_noshf[ 87: 80]; -assign aesd_out[ 79: 72] = {8{ aesd_shf[ 9]}} & {aesd_noshf[ 78: 72], 1'b0} | - {8{~aesd_shf[ 9]}} & aesd_noshf[ 79: 72]; -assign aesd_out[ 71: 64] = {8{ aesd_shf[ 8]}} & {aesd_noshf[ 70: 64], 1'b0} | - {8{~aesd_shf[ 8]}} & aesd_noshf[ 71: 64]; -assign aesd_out[ 63: 56] = {8{ aesd_shf[ 7]}} & {aesd_noshf[ 62: 56], 1'b0} | - {8{~aesd_shf[ 7]}} & aesd_noshf[ 63: 56]; -assign aesd_out[ 55: 48] = {8{ aesd_shf[ 6]}} & {aesd_noshf[ 54: 48], 1'b0} | - {8{~aesd_shf[ 6]}} & aesd_noshf[ 55: 48]; -assign aesd_out[ 47: 40] = {8{ aesd_shf[ 5]}} & {aesd_noshf[ 46: 40], 1'b0} | - {8{~aesd_shf[ 5]}} & aesd_noshf[ 47: 40]; -assign aesd_out[ 39: 32] = {8{ aesd_shf[ 4]}} & {aesd_noshf[ 38: 32], 1'b0} | - {8{~aesd_shf[ 4]}} & aesd_noshf[ 39: 32]; -assign aesd_out[ 31: 24] = {8{ aesd_shf[ 3]}} & {aesd_noshf[ 30: 24], 1'b0} | - {8{~aesd_shf[ 3]}} & aesd_noshf[ 31: 24]; -assign aesd_out[ 23: 16] = {8{ aesd_shf[ 2]}} & {aesd_noshf[ 22: 16], 1'b0} | - {8{~aesd_shf[ 2]}} & aesd_noshf[ 23: 16]; -assign aesd_out[ 15: 8] = {8{ aesd_shf[ 1]}} & {aesd_noshf[ 14: 8], 1'b0} | - {8{~aesd_shf[ 1]}} & aesd_noshf[ 15: 8]; -assign aesd_out[ 7: 0] = {8{ aesd_shf[ 0]}} & {aesd_noshf[ 6: 0], 1'b0} | - {8{~aesd_shf[ 0]}} & aesd_noshf[ 7: 0]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aese1.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aese1.sv deleted file mode 100644 index 47a88af5ac..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aese1.sv +++ /dev/null @@ -1,158 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aese1 -( - - - input wire [127:0] q, - - output wire [127:0] aese_out, - output wire [15:0] aese_shf -); - - - - - - - - wire [127:0] aese_noshf; - wire [7:0] s00; - wire [7:0] s01; - wire [7:0] s02; - wire [7:0] s03; - wire [7:0] s10; - wire [7:0] s11; - wire [7:0] s12; - wire [7:0] s13; - wire [7:0] s20; - wire [7:0] s21; - wire [7:0] s22; - wire [7:0] s23; - wire [7:0] s30; - wire [7:0] s31; - wire [7:0] s32; - wire [7:0] s33; - - - -assign s33[7:0] = q[127:120]; -assign s23[7:0] = q[119:112]; -assign s13[7:0] = q[111:104]; -assign s03[7:0] = q[103:96]; - -assign s32[7:0] = q[95:88]; -assign s22[7:0] = q[87:80]; -assign s12[7:0] = q[79:72]; -assign s02[7:0] = q[71:64]; - -assign s31[7:0] = q[63:56]; -assign s21[7:0] = q[55:48]; -assign s11[7:0] = q[47:40]; -assign s01[7:0] = q[39:32]; - -assign s30[7:0] = q[31:24]; -assign s20[7:0] = q[23:16]; -assign s10[7:0] = q[15:8]; -assign s00[7:0] = q[7:0]; - - -assign aese_noshf[7:0] = s00[7:0]; -assign aese_noshf[39:32] = s01[7:0]; -assign aese_noshf[71:64] = s02[7:0]; -assign aese_noshf[103:96] = s03[7:0]; - -assign aese_noshf[15:8] = s11[7:0]; -assign aese_noshf[47:40] = s12[7:0]; -assign aese_noshf[79:72] = s13[7:0]; -assign aese_noshf[111:104] = s10[7:0]; - -assign aese_noshf[23:16] = s22[7:0]; -assign aese_noshf[55:48] = s23[7:0]; -assign aese_noshf[87:80] = s20[7:0]; -assign aese_noshf[119:112] = s21[7:0]; - -assign aese_noshf[31:24] = s33[7:0]; -assign aese_noshf[63:56] = s30[7:0]; -assign aese_noshf[95:88] = s31[7:0]; -assign aese_noshf[127:120] = s32[7:0]; - -assign aese_shf[15] = ~aese_noshf[127]; -assign aese_shf[14] = ~aese_noshf[119]; -assign aese_shf[13] = ~aese_noshf[111]; -assign aese_shf[12] = ~aese_noshf[103]; -assign aese_shf[11] = ~aese_noshf[ 95]; -assign aese_shf[10] = ~aese_noshf[ 87]; -assign aese_shf[ 9] = ~aese_noshf[ 79]; -assign aese_shf[ 8] = ~aese_noshf[ 71]; -assign aese_shf[ 7] = ~aese_noshf[ 63]; -assign aese_shf[ 6] = ~aese_noshf[ 55]; -assign aese_shf[ 5] = ~aese_noshf[ 47]; -assign aese_shf[ 4] = ~aese_noshf[ 39]; -assign aese_shf[ 3] = ~aese_noshf[ 31]; -assign aese_shf[ 2] = ~aese_noshf[ 23]; -assign aese_shf[ 1] = ~aese_noshf[ 15]; -assign aese_shf[ 0] = ~aese_noshf[ 7]; - -assign aese_out[127:120] = {8{ aese_shf[15]}} & {aese_noshf[126:120], 1'b0} | - {8{~aese_shf[15]}} & aese_noshf[127:120]; -assign aese_out[119:112] = {8{ aese_shf[14]}} & {aese_noshf[118:112], 1'b0} | - {8{~aese_shf[14]}} & aese_noshf[119:112]; -assign aese_out[111:104] = {8{ aese_shf[13]}} & {aese_noshf[110:104], 1'b0} | - {8{~aese_shf[13]}} & aese_noshf[111:104]; -assign aese_out[103: 96] = {8{ aese_shf[12]}} & {aese_noshf[102: 96], 1'b0} | - {8{~aese_shf[12]}} & aese_noshf[103: 96]; -assign aese_out[ 95: 88] = {8{ aese_shf[11]}} & {aese_noshf[ 94: 88], 1'b0} | - {8{~aese_shf[11]}} & aese_noshf[ 95: 88]; -assign aese_out[ 87: 80] = {8{ aese_shf[10]}} & {aese_noshf[ 86: 80], 1'b0} | - {8{~aese_shf[10]}} & aese_noshf[ 87: 80]; -assign aese_out[ 79: 72] = {8{ aese_shf[ 9]}} & {aese_noshf[ 78: 72], 1'b0} | - {8{~aese_shf[ 9]}} & aese_noshf[ 79: 72]; -assign aese_out[ 71: 64] = {8{ aese_shf[ 8]}} & {aese_noshf[ 70: 64], 1'b0} | - {8{~aese_shf[ 8]}} & aese_noshf[ 71: 64]; -assign aese_out[ 63: 56] = {8{ aese_shf[ 7]}} & {aese_noshf[ 62: 56], 1'b0} | - {8{~aese_shf[ 7]}} & aese_noshf[ 63: 56]; -assign aese_out[ 55: 48] = {8{ aese_shf[ 6]}} & {aese_noshf[ 54: 48], 1'b0} | - {8{~aese_shf[ 6]}} & aese_noshf[ 55: 48]; -assign aese_out[ 47: 40] = {8{ aese_shf[ 5]}} & {aese_noshf[ 46: 40], 1'b0} | - {8{~aese_shf[ 5]}} & aese_noshf[ 47: 40]; -assign aese_out[ 39: 32] = {8{ aese_shf[ 4]}} & {aese_noshf[ 38: 32], 1'b0} | - {8{~aese_shf[ 4]}} & aese_noshf[ 39: 32]; -assign aese_out[ 31: 24] = {8{ aese_shf[ 3]}} & {aese_noshf[ 30: 24], 1'b0} | - {8{~aese_shf[ 3]}} & aese_noshf[ 31: 24]; -assign aese_out[ 23: 16] = {8{ aese_shf[ 2]}} & {aese_noshf[ 22: 16], 1'b0} | - {8{~aese_shf[ 2]}} & aese_noshf[ 23: 16]; -assign aese_out[ 15: 8] = {8{ aese_shf[ 1]}} & {aese_noshf[ 14: 8], 1'b0} | - {8{~aese_shf[ 1]}} & aese_noshf[ 15: 8]; -assign aese_out[ 7: 0] = {8{ aese_shf[ 0]}} & {aese_noshf[ 6: 0], 1'b0} | - {8{~aese_shf[ 0]}} & aese_noshf[ 7: 0]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2.sv deleted file mode 100644 index f04cecf1dd..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2.sv +++ /dev/null @@ -1,610 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesed2 -( - - - input wire clk, - input wire reset, - input wire ival_v1_q, - - input wire [127:0] aes_din_v1, - input wire [15:0] aes_shf_v1, - - output wire [127:0] aesd_out, - output wire [127:0] aese_out, - output wire [127:0] aesemc_out, - output wire [127:0] aesdimc_out -); - - - - - - - - wire [127:0] aesimc_in; - wire [127:0] aesmc_in; - wire [7:0] b00_corr_v1; - wire [7:0] b00_redn_v1; - reg [7:0] b00_redn_v2_q; - wire [7:0] b00_shf_v1; - wire [7:0] b00_v1; - wire [7:0] b01_corr_v1; - wire [7:0] b01_redn_v1; - reg [7:0] b01_redn_v2_q; - wire [7:0] b01_shf_v1; - wire [7:0] b01_v1; - wire [7:0] b02_corr_v1; - wire [7:0] b02_redn_v1; - reg [7:0] b02_redn_v2_q; - wire [7:0] b02_shf_v1; - wire [7:0] b02_v1; - wire [7:0] b03_corr_v1; - wire [7:0] b03_redn_v1; - reg [7:0] b03_redn_v2_q; - wire [7:0] b03_shf_v1; - wire [7:0] b03_v1; - wire [7:0] b10_corr_v1; - wire [7:0] b10_redn_v1; - reg [7:0] b10_redn_v2_q; - wire [7:0] b10_shf_v1; - wire [7:0] b10_v1; - wire [7:0] b11_corr_v1; - wire [7:0] b11_redn_v1; - reg [7:0] b11_redn_v2_q; - wire [7:0] b11_shf_v1; - wire [7:0] b11_v1; - wire [7:0] b12_corr_v1; - wire [7:0] b12_redn_v1; - reg [7:0] b12_redn_v2_q; - wire [7:0] b12_shf_v1; - wire [7:0] b12_v1; - wire [7:0] b13_corr_v1; - wire [7:0] b13_redn_v1; - reg [7:0] b13_redn_v2_q; - wire [7:0] b13_shf_v1; - wire [7:0] b13_v1; - wire [7:0] b20_corr_v1; - wire [7:0] b20_redn_v1; - reg [7:0] b20_redn_v2_q; - wire [7:0] b20_shf_v1; - wire [7:0] b20_v1; - wire [7:0] b21_corr_v1; - wire [7:0] b21_redn_v1; - reg [7:0] b21_redn_v2_q; - wire [7:0] b21_shf_v1; - wire [7:0] b21_v1; - wire [7:0] b22_corr_v1; - wire [7:0] b22_redn_v1; - reg [7:0] b22_redn_v2_q; - wire [7:0] b22_shf_v1; - wire [7:0] b22_v1; - wire [7:0] b23_corr_v1; - wire [7:0] b23_redn_v1; - reg [7:0] b23_redn_v2_q; - wire [7:0] b23_shf_v1; - wire [7:0] b23_v1; - wire [7:0] b30_corr_v1; - wire [7:0] b30_redn_v1; - reg [7:0] b30_redn_v2_q; - wire [7:0] b30_shf_v1; - wire [7:0] b30_v1; - wire [7:0] b31_corr_v1; - wire [7:0] b31_redn_v1; - reg [7:0] b31_redn_v2_q; - wire [7:0] b31_shf_v1; - wire [7:0] b31_v1; - wire [7:0] b32_corr_v1; - wire [7:0] b32_redn_v1; - reg [7:0] b32_redn_v2_q; - wire [7:0] b32_shf_v1; - wire [7:0] b32_v1; - wire [7:0] b33_corr_v1; - wire [7:0] b33_redn_v1; - reg [7:0] b33_redn_v2_q; - wire [7:0] b33_shf_v1; - wire [7:0] b33_v1; - - - -assign b33_v1[7:0] = aes_din_v1[127:120]; -assign b23_v1[7:0] = aes_din_v1[119:112]; -assign b13_v1[7:0] = aes_din_v1[111:104]; -assign b03_v1[7:0] = aes_din_v1[103:96]; -assign b32_v1[7:0] = aes_din_v1[95:88]; -assign b22_v1[7:0] = aes_din_v1[87:80]; -assign b12_v1[7:0] = aes_din_v1[79:72]; -assign b02_v1[7:0] = aes_din_v1[71:64]; -assign b31_v1[7:0] = aes_din_v1[63:56]; -assign b21_v1[7:0] = aes_din_v1[55:48]; -assign b11_v1[7:0] = aes_din_v1[47:40]; -assign b01_v1[7:0] = aes_din_v1[39:32]; -assign b30_v1[7:0] = aes_din_v1[31:24]; -assign b20_v1[7:0] = aes_din_v1[23:16]; -assign b10_v1[7:0] = aes_din_v1[15:8]; -assign b00_v1[7:0] = aes_din_v1[7:0]; -assign b33_shf_v1[7:0] = {8{ aes_shf_v1[15]}} & {b33_v1[6:0], 1'b0} | - {8{~aes_shf_v1[15]}} & {b33_v1[7:0]}; -assign b23_shf_v1[7:0] = {8{ aes_shf_v1[14]}} & {b23_v1[6:0], 1'b0} | - {8{~aes_shf_v1[14]}} & {b23_v1[7:0]}; -assign b13_shf_v1[7:0] = {8{ aes_shf_v1[13]}} & {b13_v1[6:0], 1'b0} | - {8{~aes_shf_v1[13]}} & {b13_v1[7:0]}; -assign b03_shf_v1[7:0] = {8{ aes_shf_v1[12]}} & {b03_v1[6:0], 1'b0} | - {8{~aes_shf_v1[12]}} & {b03_v1[7:0]}; -assign b32_shf_v1[7:0] = {8{ aes_shf_v1[11]}} & {b32_v1[6:0], 1'b0} | - {8{~aes_shf_v1[11]}} & {b32_v1[7:0]}; -assign b22_shf_v1[7:0] = {8{ aes_shf_v1[10]}} & {b22_v1[6:0], 1'b0} | - {8{~aes_shf_v1[10]}} & {b22_v1[7:0]}; -assign b12_shf_v1[7:0] = {8{ aes_shf_v1[ 9]}} & {b12_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 9]}} & {b12_v1[7:0]}; -assign b02_shf_v1[7:0] = {8{ aes_shf_v1[ 8]}} & {b02_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 8]}} & {b02_v1[7:0]}; -assign b31_shf_v1[7:0] = {8{ aes_shf_v1[ 7]}} & {b31_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 7]}} & {b31_v1[7:0]}; -assign b21_shf_v1[7:0] = {8{ aes_shf_v1[ 6]}} & {b21_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 6]}} & {b21_v1[7:0]}; -assign b11_shf_v1[7:0] = {8{ aes_shf_v1[ 5]}} & {b11_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 5]}} & {b11_v1[7:0]}; -assign b01_shf_v1[7:0] = {8{ aes_shf_v1[ 4]}} & {b01_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 4]}} & {b01_v1[7:0]}; -assign b30_shf_v1[7:0] = {8{ aes_shf_v1[ 3]}} & {b30_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 3]}} & {b30_v1[7:0]}; -assign b20_shf_v1[7:0] = {8{ aes_shf_v1[ 2]}} & {b20_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 2]}} & {b20_v1[7:0]}; -assign b10_shf_v1[7:0] = {8{ aes_shf_v1[ 1]}} & {b10_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 1]}} & {b10_v1[7:0]}; -assign b00_shf_v1[7:0] = {8{ aes_shf_v1[ 0]}} & {b00_v1[6:0], 1'b0} | - {8{~aes_shf_v1[ 0]}} & {b00_v1[7:0]}; - - - - -assign b33_corr_v1[7:0] = {8{aes_shf_v1[15]}} & {8{b33_v1[7]}} & 8'h1b; -assign b23_corr_v1[7:0] = {8{aes_shf_v1[14]}} & {8{b23_v1[7]}} & 8'h1b; -assign b13_corr_v1[7:0] = {8{aes_shf_v1[13]}} & {8{b13_v1[7]}} & 8'h1b; -assign b03_corr_v1[7:0] = {8{aes_shf_v1[12]}} & {8{b03_v1[7]}} & 8'h1b; -assign b32_corr_v1[7:0] = {8{aes_shf_v1[11]}} & {8{b32_v1[7]}} & 8'h1b; -assign b22_corr_v1[7:0] = {8{aes_shf_v1[10]}} & {8{b22_v1[7]}} & 8'h1b; -assign b12_corr_v1[7:0] = {8{aes_shf_v1[ 9]}} & {8{b12_v1[7]}} & 8'h1b; -assign b02_corr_v1[7:0] = {8{aes_shf_v1[ 8]}} & {8{b02_v1[7]}} & 8'h1b; -assign b31_corr_v1[7:0] = {8{aes_shf_v1[ 7]}} & {8{b31_v1[7]}} & 8'h1b; -assign b21_corr_v1[7:0] = {8{aes_shf_v1[ 6]}} & {8{b21_v1[7]}} & 8'h1b; -assign b11_corr_v1[7:0] = {8{aes_shf_v1[ 5]}} & {8{b11_v1[7]}} & 8'h1b; -assign b01_corr_v1[7:0] = {8{aes_shf_v1[ 4]}} & {8{b01_v1[7]}} & 8'h1b; -assign b30_corr_v1[7:0] = {8{aes_shf_v1[ 3]}} & {8{b30_v1[7]}} & 8'h1b; -assign b20_corr_v1[7:0] = {8{aes_shf_v1[ 2]}} & {8{b20_v1[7]}} & 8'h1b; -assign b10_corr_v1[7:0] = {8{aes_shf_v1[ 1]}} & {8{b10_v1[7]}} & 8'h1b; -assign b00_corr_v1[7:0] = {8{aes_shf_v1[ 0]}} & {8{b00_v1[7]}} & 8'h1b; - -assign b33_redn_v1[7:0] = b33_corr_v1[7:0] ^ b33_shf_v1[7:0]; -assign b23_redn_v1[7:0] = b23_corr_v1[7:0] ^ b23_shf_v1[7:0]; -assign b13_redn_v1[7:0] = b13_corr_v1[7:0] ^ b13_shf_v1[7:0]; -assign b03_redn_v1[7:0] = b03_corr_v1[7:0] ^ b03_shf_v1[7:0]; -assign b32_redn_v1[7:0] = b32_corr_v1[7:0] ^ b32_shf_v1[7:0]; -assign b22_redn_v1[7:0] = b22_corr_v1[7:0] ^ b22_shf_v1[7:0]; -assign b12_redn_v1[7:0] = b12_corr_v1[7:0] ^ b12_shf_v1[7:0]; -assign b02_redn_v1[7:0] = b02_corr_v1[7:0] ^ b02_shf_v1[7:0]; -assign b31_redn_v1[7:0] = b31_corr_v1[7:0] ^ b31_shf_v1[7:0]; -assign b21_redn_v1[7:0] = b21_corr_v1[7:0] ^ b21_shf_v1[7:0]; -assign b11_redn_v1[7:0] = b11_corr_v1[7:0] ^ b11_shf_v1[7:0]; -assign b01_redn_v1[7:0] = b01_corr_v1[7:0] ^ b01_shf_v1[7:0]; -assign b30_redn_v1[7:0] = b30_corr_v1[7:0] ^ b30_shf_v1[7:0]; -assign b20_redn_v1[7:0] = b20_corr_v1[7:0] ^ b20_shf_v1[7:0]; -assign b10_redn_v1[7:0] = b10_corr_v1[7:0] ^ b10_shf_v1[7:0]; -assign b00_redn_v1[7:0] = b00_corr_v1[7:0] ^ b00_shf_v1[7:0]; - - - always_ff @(posedge clk or posedge reset) - begin: u_b33_redn_v2_q_7_0_grp - if (reset == 1'b1) begin - b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) begin - b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0]; - b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0]; - b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0]; - b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0]; - b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0]; - b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0]; - b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0]; - b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0]; - b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0]; - b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0]; - b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0]; - b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0]; - b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0]; - b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0]; - b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0]; - b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0]; - end - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else begin - b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}}; - end -`else - else if (ival_v1_q == 1'b1) begin - b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0]; - b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0]; - b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0]; - b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0]; - b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0]; - b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0]; - b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0]; - b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0]; - b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0]; - b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0]; - b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0]; - b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0]; - b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0]; - b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0]; - b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0]; - b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0]; - end -`endif - end - - - -assign aesd_out[127:120] = b33_redn_v2_q[7:0]; -assign aesd_out[119:112] = b23_redn_v2_q[7:0]; -assign aesd_out[111:104] = b13_redn_v2_q[7:0]; -assign aesd_out[103:96] = b03_redn_v2_q[7:0]; - -assign aesd_out[95:88] = b32_redn_v2_q[7:0]; -assign aesd_out[87:80] = b22_redn_v2_q[7:0]; -assign aesd_out[79:72] = b12_redn_v2_q[7:0]; -assign aesd_out[71:64] = b02_redn_v2_q[7:0]; - -assign aesd_out[63:56] = b31_redn_v2_q[7:0]; -assign aesd_out[55:48] = b21_redn_v2_q[7:0]; -assign aesd_out[47:40] = b11_redn_v2_q[7:0]; -assign aesd_out[39:32] = b01_redn_v2_q[7:0]; - -assign aesd_out[31:24] = b30_redn_v2_q[7:0]; -assign aesd_out[23:16] = b20_redn_v2_q[7:0]; -assign aesd_out[15:8] = b10_redn_v2_q[7:0]; -assign aesd_out[7:0] = b00_redn_v2_q[7:0]; - - -assign aesimc_in[127:0] = aesd_out[127:0]; - -herculesae_vx_aesimc u_aesimc( - .d_in (aesimc_in[127:0]), - .imc (aesdimc_out[127:0]) -); - -assign aese_out[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1; -assign aese_out[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1; -assign aese_out[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aese_out[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aese_out[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0; -assign aese_out[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1; -assign aese_out[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1; -assign aese_out[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aese_out[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1; -assign aese_out[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1; -assign aese_out[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aese_out[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aese_out[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0; -assign aese_out[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1; -assign aese_out[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1; -assign aese_out[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aese_out[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1; -assign aese_out[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1; -assign aese_out[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aese_out[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aese_out[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0; -assign aese_out[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1; -assign aese_out[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1; -assign aese_out[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aese_out[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1; -assign aese_out[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1; -assign aese_out[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0; -assign aese_out[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0; -assign aese_out[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0; -assign aese_out[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1; -assign aese_out[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1; -assign aese_out[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0; - -assign aese_out[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1; -assign aese_out[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1; -assign aese_out[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aese_out[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aese_out[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0; -assign aese_out[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1; -assign aese_out[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1; -assign aese_out[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aese_out[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1; -assign aese_out[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1; -assign aese_out[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aese_out[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aese_out[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0; -assign aese_out[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1; -assign aese_out[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1; -assign aese_out[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aese_out[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1; -assign aese_out[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1; -assign aese_out[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aese_out[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aese_out[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0; -assign aese_out[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1; -assign aese_out[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1; -assign aese_out[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aese_out[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1; -assign aese_out[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1; -assign aese_out[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0; -assign aese_out[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0; -assign aese_out[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0; -assign aese_out[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1; -assign aese_out[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1; -assign aese_out[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0; - -assign aese_out[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1; -assign aese_out[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1; -assign aese_out[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aese_out[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aese_out[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0; -assign aese_out[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1; -assign aese_out[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1; -assign aese_out[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aese_out[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1; -assign aese_out[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1; -assign aese_out[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aese_out[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aese_out[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0; -assign aese_out[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1; -assign aese_out[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1; -assign aese_out[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aese_out[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1; -assign aese_out[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1; -assign aese_out[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aese_out[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aese_out[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0; -assign aese_out[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1; -assign aese_out[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1; -assign aese_out[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aese_out[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1; -assign aese_out[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1; -assign aese_out[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0; -assign aese_out[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0; -assign aese_out[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0; -assign aese_out[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1; -assign aese_out[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1; -assign aese_out[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0; - -assign aese_out[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1; -assign aese_out[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1; -assign aese_out[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aese_out[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aese_out[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0; -assign aese_out[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1; -assign aese_out[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1; -assign aese_out[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aese_out[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1; -assign aese_out[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1; -assign aese_out[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aese_out[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aese_out[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0; -assign aese_out[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1; -assign aese_out[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1; -assign aese_out[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aese_out[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1; -assign aese_out[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1; -assign aese_out[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aese_out[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aese_out[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0; -assign aese_out[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1; -assign aese_out[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1; -assign aese_out[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aese_out[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1; -assign aese_out[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1; -assign aese_out[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0; -assign aese_out[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0; -assign aese_out[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0; -assign aese_out[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1; -assign aese_out[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1; -assign aese_out[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0; - - - -assign aesmc_in[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0; - -assign aesmc_in[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0; - -assign aesmc_in[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0; - -assign aesmc_in[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1; -assign aesmc_in[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0; -assign aesmc_in[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0; -assign aesmc_in[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1; -assign aesmc_in[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1; -assign aesmc_in[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0; - -herculesae_vx_aesmc u_aesmc( - .d_in (aesmc_in[127:0]), - .mc (aesemc_out[127:0]) -); - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2_lut.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2_lut.sv deleted file mode 100644 index 6e8a836b13..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2_lut.sv +++ /dev/null @@ -1,93 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesed2_lut -( - - - input wire [127:0] lut_in, - - - output wire [127:0] lut_out - -); - - - - - - - - wire [7:0] b00; - wire [7:0] b01; - wire [7:0] b02; - wire [7:0] b03; - wire [7:0] b10; - wire [7:0] b11; - wire [7:0] b12; - wire [7:0] b13; - wire [7:0] b20; - wire [7:0] b21; - wire [7:0] b22; - wire [7:0] b23; - wire [7:0] b30; - wire [7:0] b31; - wire [7:0] b32; - wire [7:0] b33; - -herculesae_vx_aesinv u_inv_lut0(.lut_in(lut_in[127:120]), .lut_out(b33[7:0])); -herculesae_vx_aesinv u_inv_lut1(.lut_in(lut_in[119:112]), .lut_out(b23[7:0])); -herculesae_vx_aesinv u_inv_lut2(.lut_in(lut_in[111:104]), .lut_out(b13[7:0])); -herculesae_vx_aesinv u_inv_lut3(.lut_in(lut_in[103:96]), .lut_out(b03[7:0])); - -herculesae_vx_aesinv u_inv_lut4(.lut_in(lut_in[95:88]), .lut_out(b32[7:0])); -herculesae_vx_aesinv u_inv_lut5(.lut_in(lut_in[87:80]), .lut_out(b22[7:0])); -herculesae_vx_aesinv u_inv_lut6(.lut_in(lut_in[79:72]), .lut_out(b12[7:0])); -herculesae_vx_aesinv u_inv_lut7(.lut_in(lut_in[71:64]), .lut_out(b02[7:0])); - -herculesae_vx_aesinv u_inv_lut8 (.lut_in(lut_in[63:56]), .lut_out(b31[7:0])); -herculesae_vx_aesinv u_inv_lut9 (.lut_in(lut_in[55:48]), .lut_out(b21[7:0])); -herculesae_vx_aesinv u_inv_lut10(.lut_in(lut_in[47:40]), .lut_out(b11[7:0])); -herculesae_vx_aesinv u_inv_lut11(.lut_in(lut_in[39:32]), .lut_out(b01[7:0])); - -herculesae_vx_aesinv u_inv_lut12(.lut_in(lut_in[31:24]), .lut_out(b30[7:0])); -herculesae_vx_aesinv u_inv_lut13(.lut_in(lut_in[23:16]), .lut_out(b20[7:0])); -herculesae_vx_aesinv u_inv_lut14(.lut_in(lut_in[15:8]), .lut_out(b10[7:0])); -herculesae_vx_aesinv u_inv_lut15(.lut_in(lut_in[7:0]), .lut_out(b00[7:0])); - -assign lut_out[127:0] = {b33[7:0],b23[7:0],b13[7:0],b03[7:0], - b32[7:0],b22[7:0],b12[7:0],b02[7:0], - b31[7:0],b21[7:0],b11[7:0],b01[7:0], - b30[7:0],b20[7:0],b10[7:0],b00[7:0] - }; - - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesimc.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesimc.sv deleted file mode 100644 index e9e20e0cc4..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesimc.sv +++ /dev/null @@ -1,234 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesimc -( - - - input wire [127:0] d_in, - - output wire [127:0] imc -); - - - - - - - - wire [7:0] i00; - wire [7:0] i01; - wire [7:0] i02; - wire [7:0] i03; - wire [7:0] i10; - wire [7:0] i11; - wire [7:0] i12; - wire [7:0] i13; - wire [7:0] i20; - wire [7:0] i21; - wire [7:0] i22; - wire [7:0] i23; - wire [7:0] i30; - wire [7:0] i31; - wire [7:0] i32; - wire [7:0] i33; - wire [7:0] s00; - wire [10:0] s00_nr; - wire [7:0] s01; - wire [10:0] s01_nr; - wire [7:0] s02; - wire [10:0] s02_nr; - wire [7:0] s03; - wire [10:0] s03_nr; - wire [7:0] s10; - wire [10:0] s10_nr; - wire [7:0] s11; - wire [10:0] s11_nr; - wire [7:0] s12; - wire [10:0] s12_nr; - wire [7:0] s13; - wire [10:0] s13_nr; - wire [7:0] s20; - wire [10:0] s20_nr; - wire [7:0] s21; - wire [10:0] s21_nr; - wire [7:0] s22; - wire [10:0] s22_nr; - wire [7:0] s23; - wire [10:0] s23_nr; - wire [7:0] s30; - wire [10:0] s30_nr; - wire [7:0] s31; - wire [10:0] s31_nr; - wire [7:0] s32; - wire [10:0] s32_nr; - wire [7:0] s33; - wire [10:0] s33_nr; - - -assign i33[7:0] = d_in[127:120]; -assign i23[7:0] = d_in[119:112]; -assign i13[7:0] = d_in[111:104]; -assign i03[7:0] = d_in[103:96]; - -assign i32[7:0] = d_in[95:88]; -assign i22[7:0] = d_in[87:80]; -assign i12[7:0] = d_in[79:72]; -assign i02[7:0] = d_in[71:64]; - -assign i31[7:0] = d_in[63:56]; -assign i21[7:0] = d_in[55:48]; -assign i11[7:0] = d_in[47:40]; -assign i01[7:0] = d_in[39:32]; - -assign i30[7:0] = d_in[31:24]; -assign i20[7:0] = d_in[23:16]; -assign i10[7:0] = d_in[15:8]; -assign i00[7:0] = d_in[7:0]; - - - -assign s00_nr[10:0] = {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {2'b00,i00[7:0],1'b0} - ^ {i10[7:0],3'b000} ^ {2'b00,i10[7:0],1'b0} ^ {3'b000,i10[7:0]} - ^ {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {3'b000,i20[7:0]} - ^ {i30[7:0],3'b000} ^ {3'b000,i30[7:0]}; -assign s00[7:0] = s00_nr[7:0] ^ ({8{s00_nr[8]}} & 8'h1b) ^ ({8{s00_nr[9]}} & 8'h36) ^ ({8{s00_nr[10]}} & 8'h6c); - -assign s01_nr[10:0] = {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {2'b00,i01[7:0],1'b0} - ^ {i11[7:0],3'b000} ^ {2'b00,i11[7:0],1'b0} ^ {3'b000,i11[7:0]} - ^ {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {3'b000,i21[7:0]} - ^ {i31[7:0],3'b000} ^ {3'b000,i31[7:0]}; -assign s01[7:0] = s01_nr[7:0] ^ ({8{s01_nr[8]}} & 8'h1b) ^ ({8{s01_nr[9]}} & 8'h36) ^ ({8{s01_nr[10]}} & 8'h6c); - -assign s02_nr[10:0] = {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {2'b00,i02[7:0],1'b0} - ^ {i12[7:0],3'b000} ^ {2'b00,i12[7:0],1'b0} ^ {3'b000,i12[7:0]} - ^ {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {3'b000,i22[7:0]} - ^ {i32[7:0],3'b000} ^ {3'b000,i32[7:0]}; -assign s02[7:0] = s02_nr[7:0] ^ ({8{s02_nr[8]}} & 8'h1b) ^ ({8{s02_nr[9]}} & 8'h36) ^ ({8{s02_nr[10]}} & 8'h6c); - -assign s03_nr[10:0] = {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {2'b00,i03[7:0],1'b0} - ^ {i13[7:0],3'b000} ^ {2'b00,i13[7:0],1'b0} ^ {3'b000,i13[7:0]} - ^ {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {3'b000,i23[7:0]} - ^ {i33[7:0],3'b000} ^ {3'b000,i33[7:0]}; -assign s03[7:0] = s03_nr[7:0] ^ ({8{s03_nr[8]}} & 8'h1b) ^ ({8{s03_nr[9]}} & 8'h36) ^ ({8{s03_nr[10]}} & 8'h6c); - -assign s10_nr[10:0] = {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {2'b00,i10[7:0],1'b0} - ^ {i20[7:0],3'b000} ^ {2'b00,i20[7:0],1'b0} ^ {3'b000,i20[7:0]} - ^ {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {3'b000,i30[7:0]} - ^ {i00[7:0],3'b000} ^ {3'b000,i00[7:0]}; -assign s10[7:0] = s10_nr[7:0] ^ ({8{s10_nr[8]}} & 8'h1b) ^ ({8{s10_nr[9]}} & 8'h36) ^ ({8{s10_nr[10]}} & 8'h6c); - -assign s11_nr[10:0] = {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {2'b00,i11[7:0],1'b0} - ^ {i21[7:0],3'b000} ^ {2'b00,i21[7:0],1'b0} ^ {3'b000,i21[7:0]} - ^ {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {3'b000,i31[7:0]} - ^ {i01[7:0],3'b000} ^ {3'b000,i01[7:0]}; -assign s11[7:0] = s11_nr[7:0] ^ ({8{s11_nr[8]}} & 8'h1b) ^ ({8{s11_nr[9]}} & 8'h36) ^ ({8{s11_nr[10]}} & 8'h6c); - -assign s12_nr[10:0] = {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {2'b00,i12[7:0],1'b0} - ^ {i22[7:0],3'b000} ^ {2'b00,i22[7:0],1'b0} ^ {3'b000,i22[7:0]} - ^ {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {3'b000,i32[7:0]} - ^ {i02[7:0],3'b000} ^ {3'b000,i02[7:0]}; -assign s12[7:0] = s12_nr[7:0] ^ ({8{s12_nr[8]}} & 8'h1b) ^ ({8{s12_nr[9]}} & 8'h36) ^ ({8{s12_nr[10]}} & 8'h6c); - -assign s13_nr[10:0] = {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {2'b00,i13[7:0],1'b0} - ^ {i23[7:0],3'b000} ^ {2'b00,i23[7:0],1'b0} ^ {3'b000,i23[7:0]} - ^ {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {3'b000,i33[7:0]} - ^ {i03[7:0],3'b000} ^ {3'b000,i03[7:0]}; -assign s13[7:0] = s13_nr[7:0] ^ ({8{s13_nr[8]}} & 8'h1b) ^ ({8{s13_nr[9]}} & 8'h36) ^ ({8{s13_nr[10]}} & 8'h6c); - -assign s20_nr[10:0] = {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {2'b00,i20[7:0],1'b0} - ^ {i30[7:0],3'b000} ^ {2'b00,i30[7:0],1'b0} ^ {3'b000,i30[7:0]} - ^ {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {3'b000,i00[7:0]} - ^ {i10[7:0],3'b000} ^ {3'b000,i10[7:0]}; -assign s20[7:0] = s20_nr[7:0] ^ ({8{s20_nr[8]}} & 8'h1b) ^ ({8{s20_nr[9]}} & 8'h36) ^ ({8{s20_nr[10]}} & 8'h6c); - -assign s21_nr[10:0] = {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {2'b00,i21[7:0],1'b0} - ^ {i31[7:0],3'b000} ^ {2'b00,i31[7:0],1'b0} ^ {3'b000,i31[7:0]} - ^ {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {3'b000,i01[7:0]} - ^ {i11[7:0],3'b000} ^ {3'b000,i11[7:0]}; -assign s21[7:0] = s21_nr[7:0] ^ ({8{s21_nr[8]}} & 8'h1b) ^ ({8{s21_nr[9]}} & 8'h36) ^ ({8{s21_nr[10]}} & 8'h6c); - -assign s22_nr[10:0] = {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {2'b00,i22[7:0],1'b0} - ^ {i32[7:0],3'b000} ^ {2'b00,i32[7:0],1'b0} ^ {3'b000,i32[7:0]} - ^ {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {3'b000,i02[7:0]} - ^ {i12[7:0],3'b000} ^ {3'b000,i12[7:0]}; -assign s22[7:0] = s22_nr[7:0] ^ ({8{s22_nr[8]}} & 8'h1b) ^ ({8{s22_nr[9]}} & 8'h36) ^ ({8{s22_nr[10]}} & 8'h6c); - -assign s23_nr[10:0] = {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {2'b00,i23[7:0],1'b0} - ^ {i33[7:0],3'b000} ^ {2'b00,i33[7:0],1'b0} ^ {3'b000,i33[7:0]} - ^ {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {3'b000,i03[7:0]} - ^ {i13[7:0],3'b000} ^ {3'b000,i13[7:0]}; -assign s23[7:0] = s23_nr[7:0] ^ ({8{s23_nr[8]}} & 8'h1b) ^ ({8{s23_nr[9]}} & 8'h36) ^ ({8{s23_nr[10]}} & 8'h6c); - -assign s30_nr[10:0] = {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {2'b00,i30[7:0],1'b0} - ^ {i00[7:0],3'b000} ^ {2'b00,i00[7:0],1'b0} ^ {3'b000,i00[7:0]} - ^ {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {3'b000,i10[7:0]} - ^ {i20[7:0],3'b000} ^ {3'b000,i20[7:0]}; -assign s30[7:0] = s30_nr[7:0] ^ ({8{s30_nr[8]}} & 8'h1b) ^ ({8{s30_nr[9]}} & 8'h36) ^ ({8{s30_nr[10]}} & 8'h6c); - -assign s31_nr[10:0] = {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {2'b00,i31[7:0],1'b0} - ^ {i01[7:0],3'b000} ^ {2'b00,i01[7:0],1'b0} ^ {3'b000,i01[7:0]} - ^ {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {3'b000,i11[7:0]} - ^ {i21[7:0],3'b000} ^ {3'b000,i21[7:0]}; -assign s31[7:0] = s31_nr[7:0] ^ ({8{s31_nr[8]}} & 8'h1b) ^ ({8{s31_nr[9]}} & 8'h36) ^ ({8{s31_nr[10]}} & 8'h6c); - -assign s32_nr[10:0] = {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {2'b00,i32[7:0],1'b0} - ^ {i02[7:0],3'b000} ^ {2'b00,i02[7:0],1'b0} ^ {3'b000,i02[7:0]} - ^ {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {3'b000,i12[7:0]} - ^ {i22[7:0],3'b000} ^ {3'b000,i22[7:0]}; -assign s32[7:0] = s32_nr[7:0] ^ ({8{s32_nr[8]}} & 8'h1b) ^ ({8{s32_nr[9]}} & 8'h36) ^ ({8{s32_nr[10]}} & 8'h6c); - -assign s33_nr[10:0] = {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {2'b00,i33[7:0],1'b0} - ^ {i03[7:0],3'b000} ^ {2'b00,i03[7:0],1'b0} ^ {3'b000,i03[7:0]} - ^ {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {3'b000,i13[7:0]} - ^ {i23[7:0],3'b000} ^ {3'b000,i23[7:0]}; -assign s33[7:0] = s33_nr[7:0] ^ ({8{s33_nr[8]}} & 8'h1b) ^ ({8{s33_nr[9]}} & 8'h36) ^ ({8{s33_nr[10]}} & 8'h6c); - -assign imc[127:120] = s33[7:0]; -assign imc[119:112] = s23[7:0]; -assign imc[111:104] = s13[7:0]; -assign imc[103:96] = s03[7:0]; - -assign imc[95:88] = s32[7:0]; -assign imc[87:80] = s22[7:0]; -assign imc[79:72] = s12[7:0]; -assign imc[71:64] = s02[7:0]; - -assign imc[63:56] = s31[7:0]; -assign imc[55:48] = s21[7:0]; -assign imc[47:40] = s11[7:0]; -assign imc[39:32] = s01[7:0]; - -assign imc[31:24] = s30[7:0]; -assign imc[23:16] = s20[7:0]; -assign imc[15:8] = s10[7:0]; -assign imc[7:0] = s00[7:0]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesinv.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesinv.sv deleted file mode 100644 index 54c67587c5..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesinv.sv +++ /dev/null @@ -1,517 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesinv -( - - - input wire [7:0] lut_in, - output wire [7:0] lut_out -); - - - - - - - - - - - assign lut_out[7] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[0]) | ( - lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | ( - !lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5] - &lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6] - &lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4] - &lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[1] - &!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | ( - !lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1] - &lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1] - &lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5] - &lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6] - &!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7] - &lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7] - &lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[5] - &lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[4] - &!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6] - &lut_in[5]&lut_in[3]&!lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4] - &lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2] - &lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]&lut_in[0]); - - assign lut_out[6] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2] - &lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6] - &lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4] - &lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[1]&!lut_in[0]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4] - &lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | ( - !lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | ( - !lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2] - &!lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (lut_in[6]&lut_in[4]&!lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4] - &lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[5]&!lut_in[4] - &lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[1] - &lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1] - &lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&lut_in[0]) | ( - lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[5] - &lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[4] - &lut_in[3]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2] - &!lut_in[1]&lut_in[0]); - - assign lut_out[5] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[0]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]) | ( - !lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1] - &lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7] - &lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | ( - !lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[5]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6] - &!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6] - &!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6] - &!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7] - &lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (!lut_in[7]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[5]&lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1] - &lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | ( - !lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7] - &!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4] - &!lut_in[3]&!lut_in[1]&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[3] - &lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1] - &lut_in[0]) | (!lut_in[7]&!lut_in[4]&lut_in[2]&lut_in[1]); - - assign lut_out[4] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &!lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | ( - lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1] - &lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4] - &lut_in[3]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4] - &lut_in[3]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2] - &lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4] - &lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | ( - !lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2] - &!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]) | (!lut_in[7]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | ( - !lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[1]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]) | (!lut_in[7]&!lut_in[6] - &lut_in[4]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3] - &!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2] - &!lut_in[1]&lut_in[0]); - - assign lut_out[3] = (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6] - &lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7] - &lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[2]&!lut_in[0]) | (lut_in[7] - &!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1] - &lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4] - &lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5] - &lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[3]&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[5] - &lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7] - &!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | ( - !lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1] - &!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4] - &lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4] - &lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6] - &!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&lut_in[4] - &lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[3]&!lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[0]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1] - &lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[1]) | ( - !lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]); - - assign lut_out[2] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6] - &lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3] - &lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - !lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2] - &lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3] - &lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6] - &lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7] - &lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4] - &lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5] - &lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5] - &lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1] - &lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7] - &lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6] - &lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | ( - lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1] - &lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3] - &lut_in[2]&!lut_in[1]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3] - &lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[2]&lut_in[1]&lut_in[0]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | ( - lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[6] - &lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7] - &lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6] - &!lut_in[5]&!lut_in[3]&!lut_in[1]); - - assign lut_out[1] = (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | ( - lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4] - &lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7] - &lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | ( - lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6] - &lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3] - &!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | ( - lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1] - &lut_in[0]) | (lut_in[7]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4] - &!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6] - &lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6] - &lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6] - &!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6] - &!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7] - &!lut_in[6]&!lut_in[4]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5] - &!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5] - &lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5] - &lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2] - &!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]) | (lut_in[7]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[1]) | ( - !lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]); - - assign lut_out[0] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5] - &!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7] - &!lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | ( - lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5] - &!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6] - &!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2] - &!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[4] - &!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6] - &!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6] - &lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | ( - lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1] - &!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2] - &!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4] - &!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6] - &lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7] - &!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | ( - !lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1] - &lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2] - &lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3] - &!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4] - &lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6] - &!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5] - &!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7] - &!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | ( - lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1] - &!lut_in[0]) | (lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1] - &lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3] - &lut_in[2]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1] - &!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[4]&!lut_in[3]&lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3] - &!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3] - &lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2] - &lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3] - &!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[2] - &!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]&lut_in[1] - &lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3] - &lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1] - &lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1] - &lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[1]) | ( - !lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | ( - !lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (!lut_in[7] - &!lut_in[6]&lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5] - &!lut_in[4]&lut_in[1]&lut_in[0]); - - - - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesmc.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesmc.sv deleted file mode 100644 index 33d55447ff..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesmc.sv +++ /dev/null @@ -1,186 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_aesmc -( - - - input wire [127:0] d_in, - - output wire [127:0] mc -); - - - - - - - - wire [7:0] i00; - wire [7:0] i01; - wire [7:0] i02; - wire [7:0] i03; - wire [7:0] i10; - wire [7:0] i11; - wire [7:0] i12; - wire [7:0] i13; - wire [7:0] i20; - wire [7:0] i21; - wire [7:0] i22; - wire [7:0] i23; - wire [7:0] i30; - wire [7:0] i31; - wire [7:0] i32; - wire [7:0] i33; - wire [7:0] s00; - wire [7:0] s01; - wire [7:0] s02; - wire [7:0] s03; - wire [7:0] s10; - wire [7:0] s11; - wire [7:0] s12; - wire [7:0] s13; - wire [7:0] s20; - wire [7:0] s21; - wire [7:0] s22; - wire [7:0] s23; - wire [7:0] s30; - wire [7:0] s31; - wire [7:0] s32; - wire [7:0] s33; - - -assign i33[7:0] = d_in[127:120]; -assign i23[7:0] = d_in[119:112]; -assign i13[7:0] = d_in[111:104]; -assign i03[7:0] = d_in[103:96]; - -assign i32[7:0] = d_in[95:88]; -assign i22[7:0] = d_in[87:80]; -assign i12[7:0] = d_in[79:72]; -assign i02[7:0] = d_in[71:64]; - -assign i31[7:0] = d_in[63:56]; -assign i21[7:0] = d_in[55:48]; -assign i11[7:0] = d_in[47:40]; -assign i01[7:0] = d_in[39:32]; - -assign i30[7:0] = d_in[31:24]; -assign i20[7:0] = d_in[23:16]; -assign i10[7:0] = d_in[15:8]; -assign i00[7:0] = d_in[7:0]; - - -assign s00[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) - ^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) ^ i10[7:0] - ^ i20[7:0] - ^ i30[7:0]; -assign s01[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) - ^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) ^ i11[7:0] - ^ i21[7:0] - ^ i31[7:0]; -assign s02[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) - ^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) ^ i12[7:0] - ^ i22[7:0] - ^ i32[7:0]; -assign s03[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) - ^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) ^ i13[7:0] - ^ i23[7:0] - ^ i33[7:0]; -assign s10[7:0] = i00[7:0] - ^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) - ^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) ^ i20[7:0] - ^ i30[7:0]; -assign s11[7:0] = i01[7:0] - ^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) - ^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) ^ i21[7:0] - ^ i31[7:0]; -assign s12[7:0] = i02[7:0] - ^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) - ^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) ^ i22[7:0] - ^ i32[7:0]; -assign s13[7:0] = i03[7:0] - ^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) - ^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) ^ i23[7:0] - ^ i33[7:0]; -assign s20[7:0] = i00[7:0] - ^ i10[7:0] - ^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) - ^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b) ^ i30[7:0]; -assign s21[7:0] = i01[7:0] - ^ i11[7:0] - ^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) - ^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b) ^ i31[7:0]; -assign s22[7:0] = i02[7:0] - ^ i12[7:0] - ^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) - ^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b) ^ i32[7:0]; -assign s23[7:0] = i03[7:0] - ^ i13[7:0] - ^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) - ^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b) ^ i33[7:0]; -assign s30[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) ^ i00[7:0] - ^ i10[7:0] - ^ i20[7:0] - ^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b); -assign s31[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) ^ i01[7:0] - ^ i11[7:0] - ^ i21[7:0] - ^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b); -assign s32[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) ^ i02[7:0] - ^ i12[7:0] - ^ i22[7:0] - ^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b); -assign s33[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) ^ i03[7:0] - ^ i13[7:0] - ^ i23[7:0] - ^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b); - -assign mc[127:120] = s33[7:0]; -assign mc[119:112] = s23[7:0]; -assign mc[111:104] = s13[7:0]; -assign mc[103:96] = s03[7:0]; - -assign mc[95:88] = s32[7:0]; -assign mc[87:80] = s22[7:0]; -assign mc[79:72] = s12[7:0]; -assign mc[71:64] = s02[7:0]; - -assign mc[63:56] = s31[7:0]; -assign mc[55:48] = s21[7:0]; -assign mc[47:40] = s11[7:0]; -assign mc[39:32] = s01[7:0]; - -assign mc[31:24] = s30[7:0]; -assign mc[23:16] = s20[7:0]; -assign mc[15:8] = s10[7:0]; -assign mc[7:0] = s00[7:0]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_crypt.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_crypt.sv deleted file mode 100644 index ba401aa24b..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_crypt.sv +++ /dev/null @@ -1,966 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_crypt -( - - input wire clk, - input wire reset, - - input wire ival_v1_q, - input wire sha1c_v1_q, - input wire sha1p_v1_q, - input wire sha1m_v1_q, - input wire sha1cpm_v1_q, - input wire sha256h_v1_q, - input wire sha256h2_v1_q, - input wire sha256hh2_v1_q, - input wire sha1h_v1_q, - input wire sha1su0_v1_q, - input wire sha1su1_v1_q, - input wire sha256su0_v1_q, - input wire sha256su1_v1_q, - input wire sha256su1_dup_x_v1_q, - input wire sha256su1_dup_y_v1_q, - input wire sha256su1_dup_z_v1_q, - - input wire [127:0] opa_v1, - input wire [127:0] opb_v1, - input wire [127:0] opc_v1, - - output wire [127:0] cryptout_v2, - output wire [127:0] cryptout_v4, - output wire crypt_active -); - - - - - - - - wire block_opa_passthrough; - wire [63:0] carry1c_v1; - wire [63:0] carry4c_v3; - wire [31:0] carry4c_v4; - wire [63:0] carry_2c4c_v2; - wire [31:0] carry_sha1cpm_v1; - wire [31:0] carry_sha1cpm_v2; - wire [31:0] carry_sha1cpm_v3; - wire [31:0] carry_sha1cpm_v4; - wire [63:0] carry_sha256h32_v1; - wire [63:0] carry_sha256h32_v2; - wire [63:0] carry_sha256h32_v3; - wire [31:0] carry_sha256h32_v4; - wire [31:0] carry_sha256su0_v1; - wire [63:0] carry_sha256su1_v1; - wire [63:0] carry_sha256su1_v2; - wire ival_en; - wire ival_v1_or_v2; - wire ival_v2_4latency; - reg ival_v2_q; - reg ival_v3_q; - wire [127:0] newa_v1; - wire [127:0] newa_v2; - wire [127:0] newa_v3; - wire [127:0] newb_v1; - wire [127:0] newb_v2; - wire [127:0] newb_v3; - wire [95:0] newc_v1; - wire [127:0] newx_v4; - wire [127:0] newy_v4; - reg [127:0] opa_v2_q; - reg [127:0] opa_v3_q; - reg [127:0] opa_v4_q; - reg [127:0] opb_v2_q; - reg [127:0] opb_v3_q; - reg [127:0] opb_v4_q; - reg [95:0] opc_v2_q; - reg [63:0] opc_v3_q; - reg [31:0] opc_v4_q; - wire [127:0] sha1_out_v1; - wire sha1_v1; - wire [127:0] sha1_xin_v1; - wire [31:0] sha1_yin_v1; - wire [31:0] sha1_zin_v1; - reg sha1c_v2_q; - reg sha1c_v3_q; - reg sha1c_v4_q; - reg sha1cpm_h_v4_q; - reg sha1cpm_l_v4_q; - reg sha1cpm_v2_q; - reg sha1cpm_v3_q; - reg sha1cpm_v4_q; - wire [127:0] sha1cpm_x_v1; - wire [127:0] sha1cpm_x_v2; - wire [127:0] sha1cpm_x_v3; - wire [127:0] sha1cpm_x_v4; - wire [127:0] sha1cpm_y_v1; - wire [127:0] sha1cpm_y_v2; - wire [127:0] sha1cpm_y_v3; - wire [31:0] sha1cpm_y_v4; - wire [31:0] sha1h_qnin_v1; - reg sha1m_v2_q; - reg sha1m_v3_q; - reg sha1m_v4_q; - reg sha1p_v2_q; - reg sha1p_v3_q; - reg sha1p_v4_q; - wire [127:0] sha1su0_q_v1; - reg sha1su0_v2_q; - wire [127:0] sha1su1_qdin_v1; - wire [127:0] sha1su1_qnin_v1; - wire [127:0] sha256_xin_v1; - wire [127:0] sha256_yin_v1; - wire [31:0] sha256_zin_v1; - reg sha256h2_h_v4_q; - reg sha256h2_l_v4_q; - reg sha256h2_v2_q; - reg sha256h2_v3_q; - reg sha256h2_v4_q; - reg sha256h_h_v4_q; - reg sha256h_l_v4_q; - reg sha256h_v2_q; - reg sha256h_v3_q; - reg sha256h_v4_q; - wire [127:0] sha256h_x_v1; - wire [127:0] sha256h_x_v2; - wire [127:0] sha256h_x_v3; - wire [127:0] sha256h_x_v4; - wire [127:0] sha256h_y_v1; - wire [127:0] sha256h_y_v2; - wire [127:0] sha256h_y_v3; - wire [127:0] sha256h_y_v4; - wire sha256hh2_v2; - wire sha256hh2_v3; - wire sha256hh2_v4; - wire [127:0] sha256su0_out_v1; - wire [127:0] sha256su0_qdin_v1; - wire [127:0] sha256su0_qnin_v1; - reg sha256su1_dup_x_v2_q; - reg sha256su1_dup_y_v2_q; - reg sha256su1_dup_z_v2_q; - reg sha256su1_h_v2_q; - reg sha256su1_l_v2_q; - reg sha256su1_v2_q; - wire [63:0] sha256su1_x_v1; - wire [63:0] sha256su1_x_v2; - reg sha_inst_h_v2_q; - reg sha_inst_l_v2_q; - wire sha_inst_v1; - reg sha_inst_v2_q; - wire short_pipe_out_v3_en; - wire [31:0] sigma0_v3; - wire [31:0] sigma0_v4; - wire [31:0] sigma1_v3; - wire [63:0] sum1c_v1; - wire [63:0] sum4c_v3; - wire [31:0] sum4c_v4; - wire [63:0] sum_2c4c_v2; - wire [31:0] sum_sha1cpm_v1; - wire [31:0] sum_sha1cpm_v2; - wire [31:0] sum_sha1cpm_v3; - wire [31:0] sum_sha1cpm_v4; - wire [63:0] sum_sha256h32_v1; - wire [63:0] sum_sha256h32_v2; - wire [63:0] sum_sha256h32_v3; - wire [31:0] sum_sha256h32_v4; - wire [31:0] sum_sha256su0_v1; - wire [63:0] sum_sha256su1_v1; - wire [63:0] sum_sha256su1_v2; - wire [63:0] sumnr1c_v1; - wire [63:0] sumnr4c_v3; - wire [31:0] sumnr4c_v4; - wire [63:0] sumnr_2c4c_v2; - wire [63:0] sumres_sha256su1_v2; - wire [31:0] tchoose_v3; - wire [31:0] tmajority_v3; - wire [31:0] tmajority_v4; - wire unused_cout1c2_v1; - wire unused_cout1c_v1; - wire unused_cout2_2c4c_v2; - wire unused_cout2_4c_v3; - wire unused_cout4c_v3; - wire unused_cout4c_v4; - wire unused_cout_2c4c_v2; - wire unused_cout_sha256su1h_v2; - wire unused_cout_sha256su1l_v2; - wire [32:0] x_fa2_c_v4; - wire [31:0] x_fa2_s_v4; - wire [127:0] x_v1; - wire [127:0] x_v2; - wire [127:0] x_v3; - wire [127:0] x_v4; - wire xprime_carry; - wire [127:96] xprime_v4; - wire [32:0] xy_fa0_c_v3; - wire [31:0] xy_fa0_s_v3; - wire [32:0] xy_fa1_c_v3; - wire [31:0] xy_fa1_c_v4; - wire [31:0] xy_fa1_s_v3; - wire [31:0] xy_fa1_s_v4; - wire [32:0] y_fa2_c_v4; - wire [31:0] y_fa2_s_v4; - wire [32:0] y_fa3_c_v4; - wire [31:0] y_fa3_s_v4; - wire [127:0] y_v1; - wire [127:0] y_v2; - wire [127:0] y_v3; - wire [127:0] y_v4; - wire [127:96] yprime_v4; - wire [127:0] z_v1; - wire [95:0] z_v2; - wire [63:0] z_v3; - wire [31:0] z_v4; - - - - assign ival_en = ival_v1_q | ival_v2_q | ival_v3_q; - - assign short_pipe_out_v3_en = sha_inst_v2_q | sha1su0_v2_q | sha256su1_v2_q; - - assign ival_v2_4latency = ~short_pipe_out_v3_en & ival_v2_q; - - assign ival_v1_or_v2 = ival_v1_q | ival_v2_q; - - - always_ff @(posedge clk or posedge reset) - begin: u_ival_v2_q - if (reset == 1'b1) - ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_en == 1'b1) - ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q; - else if (reset == 1'b0 && ival_en == 1'b0) - begin - end - else - ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; -`else - else if (ival_en == 1'b1) - ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q; -`endif - end - - - always_ff @(posedge clk or posedge reset) - begin: u_ival_v3_q - if (reset == 1'b1) - ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_en == 1'b1) - ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency; - else if (reset == 1'b0 && ival_en == 1'b0) - begin - end - else - ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; -`else - else if (ival_en == 1'b1) - ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency; -`endif - end - - - - always_ff @(posedge clk or posedge reset) - begin: u_sha1c_v2_q_grp - if (reset == 1'b1) begin - sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) begin - sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q; - sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q; - sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q; - sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q; - sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q; - sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q; - sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q; - sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - end - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else begin - sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - end -`else - else if (ival_v1_q == 1'b1) begin - sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q; - sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q; - sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q; - sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q; - sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q; - sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q; - sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1; - sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q; - sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q; - end -`endif - end - - - - always_ff @(posedge clk or posedge reset) - begin: u_sha1c_v3_q_grp - if (reset == 1'b1) begin - sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin - sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q; - sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q; - sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q; - sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q; - sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q; - sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q; - end - else if (reset == 1'b0 && ival_v2_4latency == 1'b0) - begin - end - else begin - sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - end -`else - else if (ival_v2_4latency == 1'b1) begin - sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q; - sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q; - sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q; - sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q; - sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q; - sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q; - end -`endif - end - - - - always_ff @(posedge clk or posedge reset) - begin: u_sha1c_v4_q_grp - if (reset == 1'b1) begin - sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v3_q == 1'b1) begin - sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q; - sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q; - sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q; - sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q; - sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q; - end - else if (reset == 1'b0 && ival_v3_q == 1'b0) - begin - end - else begin - sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}}; - end -`else - else if (ival_v3_q == 1'b1) begin - sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q; - sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q; - sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q; - sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q; - sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q; - sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q; - sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q; - end -`endif - end - - - - - - - assign sha1_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q; - - assign sha1h_qnin_v1[ 31:0] = {32{sha1h_v1_q}} & opa_v1[ 31:0]; - assign sha1su1_qdin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opb_v1[127:0]; - assign sha1su1_qnin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opa_v1[127:0]; - assign sha1su0_q_v1[127:0] = {128{sha1su0_v1_q}} & opc_v1[127:0]; - - herculesae_vx_sha1 u_sha1( - .sha1h_v1_i (sha1h_v1_q), - .sha1su0_v1_i (sha1su0_v1_q), - .sha1su1_v1_i (sha1su1_v1_q), - .sha1h_qn (sha1h_qnin_v1[31:0]), - .sha1su0_qd (sha1su0_q_v1[127:0]), - .sha1su1_qd (sha1su1_qdin_v1[127:0]), - .sha1su1_qn (sha1su1_qnin_v1[127:0]), - .sha1_v1_o (sha1_out_v1[127:0])); - - - - assign sha256su0_qdin_v1[127:0] = {128{sha256su0_v1_q}} & opb_v1[127:0]; - assign sha256su0_qnin_v1[127:0] = {128{sha256su0_v1_q}} & opa_v1[127:0]; - - herculesae_vx_sha256su0 u_sha256su0( - .qd (sha256su0_qdin_v1[127:0]), - .qn (sha256su0_qnin_v1[ 31:0]), - .sumd (sumnr1c_v1[31:0]), - .suma (sum_sha256su0_v1[31:0]), - .sumb (carry_sha256su0_v1[31:0]), - .d (sha256su0_out_v1[127:0])); - - - - - herculesae_vx_sha256su1 u_sha256su1_v1( - .sha256su1_x_op (sha256su1_dup_x_v1_q), - .sha256su1_y_op (sha256su1_dup_y_v1_q), - .sha256su1_z_op (sha256su1_dup_z_v1_q), - .x (opc_v1[63:0]), - .y (opa_v1[95:32]), - .z (opb_v1[127:64]), - .sumnr (sumnr1c_v1[63:0]), - .sum_3to2 (sum_sha256su1_v1[63:0]), - .carry_3to2 (carry_sha256su1_v1[63:0]), - .newx (sha256su1_x_v1[63:0])); - - - - assign x_v1[127:0] = opc_v1[127:0]; - assign y_v1[127:0] = opa_v1[127:0]; - assign z_v1[127:0] = opb_v1[127:0]; - - assign sha1_xin_v1[127:0] = {128{sha1cpm_v1_q}} & x_v1[127:0]; - assign sha1_yin_v1[31:0] = { 32{sha1cpm_v1_q}} & y_v1[31:0]; - assign sha1_zin_v1[31:0] = { 32{sha1cpm_v1_q}} & z_v1[31:0]; - - herculesae_vx_sha1cpm u_sha1cpm_v1( - .choose (sha1c_v1_q), - .parity (sha1p_v1_q), - .majority (sha1m_v1_q), - .cpm (sha1cpm_v1_q), - .x (sha1_xin_v1[127:0]), - .y (sha1_yin_v1[31:0]), - .z (sha1_zin_v1[31:0]), - .t2 (sumnr1c_v1[31:0]), - .fa1_s (sum_sha1cpm_v1[31:0]), - .fa1_c (carry_sha1cpm_v1[31:0]), - .newx (sha1cpm_x_v1[127:0]), - .newy (sha1cpm_y_v1[31:0])); - assign sha1cpm_y_v1[127:32] = {96{sha1cpm_v1_q}} & y_v1[127:32]; - - assign sha256_xin_v1[127:0] = {128{sha256hh2_v1_q}} & x_v1[127:0]; - assign sha256_yin_v1[127:0] = {128{sha256hh2_v1_q}} & y_v1[127:0]; - assign sha256_zin_v1[ 31:0] = {32{ sha256hh2_v1_q}} & z_v1[31:0]; - - herculesae_vx_sha256h32 u_sha256h32_v1( - .x (sha256_xin_v1[127:0]), - .y (sha256_yin_v1[127:0]), - .z (sha256_zin_v1[31:0]), - .sumnr (sumnr1c_v1[63:0]), - .sum (sum_sha256h32_v1[63:0]), - .carry (carry_sha256h32_v1[63:0]), - .newx (sha256h_x_v1[127:0]), - .newy (sha256h_y_v1[127:0])); - - - assign sum1c_v1[31:0] = {32{sha256su0_v1_q}} & sum_sha256su0_v1[31:0] - | {32{sha1cpm_v1_q }} & sum_sha1cpm_v1[31:0] - | {32{sha256hh2_v1_q}} & sum_sha256h32_v1[31:0] - | {32{sha256su1_v1_q}} & sum_sha256su1_v1[31:0]; - assign carry1c_v1[31:0] = {32{sha256su0_v1_q}} & carry_sha256su0_v1[31:0] - | {32{sha1cpm_v1_q }} & carry_sha1cpm_v1[31:0] - | {32{sha256hh2_v1_q}} & carry_sha256h32_v1[31:0] - | {32{sha256su1_v1_q}} & carry_sha256su1_v1[31:0]; - - - assign {unused_cout1c_v1, sumnr1c_v1[31:0]} = sum1c_v1[31:0] + carry1c_v1[31:0] + {{31{1'b0}}, 1'b0}; - - - assign sum1c_v1[63:32] = {32{sha256hh2_v1_q}} & sum_sha256h32_v1[63:32] - | {32{sha256su1_v1_q}} & sum_sha256su1_v1[63:32]; - assign carry1c_v1[63:32] = {32{sha256hh2_v1_q}} & carry_sha256h32_v1[63:32] - | {32{sha256su1_v1_q}} & carry_sha256su1_v1[63:32]; - - - assign {unused_cout1c2_v1, sumnr1c_v1[63:32]} = sum1c_v1[63:32] + carry1c_v1[63:32] + {{31{1'b0}}, 1'b0}; - - - - assign sha_inst_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q | sha256su0_v1_q; - - assign block_opa_passthrough = sha_inst_v1 | sha256su1_v1_q | - sha256hh2_v1_q | sha1cpm_v1_q; - - assign newa_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_y_v1[127:0]) - | ({128{sha256hh2_v1_q}} & sha256h_y_v1[127:0]) - | ({128{sha256su1_v1_q}} & {opb_v1[31:0],opa_v1[127:32]}) - | ({128{sha256su0_v1_q}} & sha256su0_out_v1[127:0]) - | ({128{sha1_v1}} & sha1_out_v1[127:0]) - | ({128{~(block_opa_passthrough)}} & opa_v1[127:0]); - - assign newb_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_x_v1[127:0]) - | ({128{sha256hh2_v1_q}} & sha256h_x_v1[127:0]) - | ({128{sha256su1_v1_q}} & {opc_v1[127:64], sha256su1_x_v1[63:0]}); - - assign newc_v1[95:0] = opb_v1[127:32]; - - - - always_ff @(posedge clk or posedge reset) - begin: u_opa_v2_q_127_0_grp - if (reset == 1'b1) begin - opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) begin - opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0]; - opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0]; - opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0]; - end - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else begin - opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'bx}}; - end -`else - else if (ival_v1_q == 1'b1) begin - opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0]; - opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0]; - opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0]; - end -`endif - end - - - assign x_v2[127:0] = opb_v2_q[127:0]; - assign y_v2[127:0] = opa_v2_q[127:0]; - assign z_v2[95:0] = opc_v2_q[95:0]; - - - herculesae_vx_sha256su1 u_sha256su1_v2( - .sha256su1_x_op (sha256su1_dup_x_v2_q), - .sha256su1_y_op (sha256su1_dup_y_v2_q), - .sha256su1_z_op (sha256su1_dup_z_v2_q), - .x (x_v2[127:64]), - .y (y_v2[127:64]), - .z (x_v2[63:0]), - .sumnr (sumres_sha256su1_v2[63:0]), - .sum_3to2 (sum_sha256su1_v2[63:0]), - .carry_3to2 (carry_sha256su1_v2[63:0]), - .newx (sha256su1_x_v2[63:0])); - - - - herculesae_vx_sha1cpm u_sha1cpm_v2( - .choose (sha1c_v2_q), - .parity (sha1p_v2_q), - .majority (sha1m_v2_q), - .cpm (sha1cpm_v2_q), - .x (x_v2[127:0]), - .y (y_v2[31:0]), - .z (z_v2[31:0]), - .t2 (sumnr_2c4c_v2[31:0]), - .fa1_s (sum_sha1cpm_v2[31:0]), - .fa1_c (carry_sha1cpm_v2[31:0]), - .newx (sha1cpm_x_v2[127:0]), - .newy (sha1cpm_y_v2[31:0])); - - assign sha1cpm_y_v2[127:32] = y_v2[127:32]; - - herculesae_vx_sha256h32 u_sha256h32_v2( - .x (x_v2[127:0]), - .y (y_v2[127:0]), - .z (z_v2[31:0]), - .sumnr (sumnr_2c4c_v2[63:0]), - .sum (sum_sha256h32_v2[63:0]), - .carry (carry_sha256h32_v2[63:0]), - .newx (sha256h_x_v2[127:0]), - .newy (sha256h_y_v2[127:0])); - - - assign sha256hh2_v2 = sha256h_v2_q | sha256h2_v2_q; - - - assign sum_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & sum_sha1cpm_v2[31:0] | - {32{sha256hh2_v2}} & sum_sha256h32_v2[31:0]; - assign carry_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & carry_sha1cpm_v2[31:0] | - {32{sha256hh2_v2}} & carry_sha256h32_v2[31:0]; - - assign {unused_cout_2c4c_v2, sumnr_2c4c_v2[31:0]} = sum_2c4c_v2[31:0] + carry_2c4c_v2[31:0] + {{31{1'b0}}, 1'b0}; - - - - - assign sum_2c4c_v2[63:32] = {32{sha256hh2_v2}} & sum_sha256h32_v2[63:32]; - assign carry_2c4c_v2[63:32] = {32{sha256hh2_v2}} & carry_sha256h32_v2[63:32]; - - assign {unused_cout2_2c4c_v2, sumnr_2c4c_v2[63:32]} = sum_2c4c_v2[63:32] + carry_2c4c_v2[63:32] + {{31{1'b0}}, 1'b0}; - - - - assign {unused_cout_sha256su1l_v2, sumres_sha256su1_v2[31:0]} = sum_sha256su1_v2[31:0] + carry_sha256su1_v2[31:0] + {{31{1'b0}}, 1'b0}; - - - assign {unused_cout_sha256su1h_v2, sumres_sha256su1_v2[63:32]} = sum_sha256su1_v2[63:32] + carry_sha256su1_v2[63:32] + {{31{1'b0}}, 1'b0}; - - - - assign newb_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_x_v2[127:0]) - | ({128{sha256hh2_v2}} & sha256h_x_v2[127:0]); - - assign newa_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_y_v2[127:0]) - | ({128{sha256hh2_v2}} & sha256h_y_v2[127:0]); - - - assign cryptout_v2[127:64] = ({64{sha256su1_h_v2_q}} & sha256su1_x_v2[63:0]) - | ({64{sha_inst_h_v2_q}} & opa_v2_q[127:64]); - - assign cryptout_v2[63:0] = ({64{sha256su1_l_v2_q}} & opb_v2_q[63:0]) - | ({64{sha_inst_l_v2_q}} & opa_v2_q[63:0]); - - - - always_ff @(posedge clk or posedge reset) - begin: u_opa_v3_q_127_0_grp - if (reset == 1'b1) begin - opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin - opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0]; - opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0]; - opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32]; - end - else if (reset == 1'b0 && ival_v2_4latency == 1'b0) - begin - end - else begin - opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'bx}}; - end -`else - else if (ival_v2_4latency == 1'b1) begin - opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0]; - opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0]; - opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32]; - end -`endif - end - - - - assign x_v3[127:0] = opb_v3_q[127:0]; - assign y_v3[127:0] = opa_v3_q[127:0]; - assign z_v3[63:0] = opc_v3_q[63:0]; - - herculesae_vx_sha1cpm u_sha1cpm_v3( - .choose (sha1c_v3_q), - .parity (sha1p_v3_q), - .majority (sha1m_v3_q), - .cpm (sha1cpm_v3_q), - .x (x_v3[127:0]), - .y (y_v3[31:0]), - .z (z_v3[31:0]), - .t2 (sumnr4c_v3[31:0]), - .fa1_s (sum_sha1cpm_v3[31:0]), - .fa1_c (carry_sha1cpm_v3[31:0]), - .newx (sha1cpm_x_v3[127:0]), - .newy (sha1cpm_y_v3[31:0])); - assign sha1cpm_y_v3[127:32] = y_v3[127:32]; - - herculesae_vx_sha256h32 u_sha256h32_v3( - .x (x_v3[127:0]), - .y (y_v3[127:0]), - .z (z_v3[31:0]), - .sumnr (sumnr4c_v3[63:0]), - .sum (sum_sha256h32_v3[63:0]), - .carry (carry_sha256h32_v3[63:0]), - .newx (sha256h_x_v3[127:0]), - .newy (sha256h_y_v3[127:0])); - - assign tchoose_v3[31:0] = (sha256h_y_v3[31:0] & sha256h_y_v3[63:32]) | - (~sha256h_y_v3[31:0] & sha256h_y_v3[95:64]); - - assign tmajority_v3[31:0] = (sha256h_x_v3[31:0] & sha256h_x_v3[63:32]) | - (sha256h_x_v3[31:0] & sha256h_x_v3[95:64]) | - (sha256h_x_v3[63:32] & sha256h_x_v3[95:64]); - - assign sigma0_v3[31:0] = {sha256h_x_v3[1:0], sha256h_x_v3[31:2]} - ^ {sha256h_x_v3[12:0], sha256h_x_v3[31:13]} - ^ {sha256h_x_v3[21:0], sha256h_x_v3[31:22]}; - - assign sigma1_v3[31:0] = {sha256h_y_v3[5:0], sha256h_y_v3[31:6]} - ^ {sha256h_y_v3[10:0], sha256h_y_v3[31:11]} - ^ {sha256h_y_v3[24:0], sha256h_y_v3[31:25]}; - - - assign xy_fa0_s_v3[31:0] = sha256h_y_v3[127:96] ^ z_v3[63:32] ^ tchoose_v3[31:0]; - - assign xy_fa0_c_v3[32:0] = {sha256h_y_v3[127:96] & z_v3[63:32] | tchoose_v3[31:0] & - (sha256h_y_v3[127:96] | z_v3[63:32]), 1'b0}; - - - - assign xy_fa1_s_v3[31:0] = xy_fa0_s_v3[31:0] ^ xy_fa0_c_v3[31:0] ^ sigma1_v3[31:0]; - - assign xy_fa1_c_v3[32:0] = {xy_fa0_s_v3[31:0] & xy_fa0_c_v3[31:0] | sigma1_v3[31:0] & - (xy_fa0_s_v3[31:0] | xy_fa0_c_v3[31:0]), 1'b0}; - - - assign sha256hh2_v3 = sha256h_v3_q | sha256h2_v3_q; - - assign sum4c_v3[31:0] = {32{sha1cpm_v3_q}} & sum_sha1cpm_v3[31:0] | - {32{sha256hh2_v3}} & sum_sha256h32_v3[31:0]; - assign carry4c_v3[31:0] = {32{sha1cpm_v3_q}} & carry_sha1cpm_v3[31:0] | - {32{sha256hh2_v3}} & carry_sha256h32_v3[31:0]; - - assign {unused_cout4c_v3, sumnr4c_v3[31:0]} = sum4c_v3[31:0] + carry4c_v3[31:0] + {{31{1'b0}}, 1'b0}; - - - assign sum4c_v3[63:32] = sum_sha256h32_v3[63:32]; - assign carry4c_v3[63:32] = carry_sha256h32_v3[63:32]; - - assign {unused_cout2_4c_v3, sumnr4c_v3[63:32]} = sum4c_v3[63:32] + carry4c_v3[63:32] + {{31{1'b0}}, 1'b0}; - - - - - assign newa_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_y_v3[127:0]) - | ({128{sha256h_v3_q}} & {sigma0_v3[31:0], tmajority_v3[31:0], - xy_fa1_s_v3[31:0], xy_fa1_c_v3[31:0]}) - | ({128{sha256h2_v3_q}} & {sigma0_v3[31:0],tmajority_v3[31:0], - xy_fa1_s_v3[31:0],xy_fa1_c_v3[31:0]}); - - assign newb_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_x_v3[127:0]) - | ({128{sha256h_v3_q }} & sha256h_x_v3[127:0]) - | ({128{sha256h2_v3_q }} & {sha256h_x_v3[127:96], sha256h_y_v3[95:0]}); - - - always_ff @(posedge clk or posedge reset) - begin: u_opb_v4_q_127_0_grp - if (reset == 1'b1) begin - opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; - opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'b0}}; - end -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v3_q == 1'b1) begin - opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0]; - opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0]; - opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32]; - end - else if (reset == 1'b0 && ival_v3_q == 1'b0) - begin - end - else begin - opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; - opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'bx}}; - end -`else - else if (ival_v3_q == 1'b1) begin - opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0]; - opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0]; - opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32]; - end -`endif - end - - - - assign x_v4[127:0] = opb_v4_q[127:0]; - assign y_v4[127:0] = opa_v4_q[127:0]; - assign z_v4[31:0] = opc_v4_q[31:0]; - - herculesae_vx_sha1cpm u_sha1cpm_v4( - .choose (sha1c_v4_q), - .parity (sha1p_v4_q), - .majority (sha1m_v4_q), - .cpm (sha1cpm_v4_q), - .x (x_v4[127:0]), - .y (y_v4[31:0]), - .z (z_v4[31:0]), - .t2 (sumnr4c_v4[31:0]), - .fa1_s (sum_sha1cpm_v4[31:0]), - .fa1_c (carry_sha1cpm_v4[31:0]), - .newx (sha1cpm_x_v4[127:0]), - .newy (sha1cpm_y_v4[31:0])); - - assign sigma0_v4[31:0] = y_v4[127:96]; - assign tmajority_v4[31:0] = y_v4[95:64]; - assign xy_fa1_s_v4[31:0] = y_v4[63:32]; - assign xy_fa1_c_v4[31:0] = y_v4[31:0]; - - assign x_fa2_s_v4[31:0] = xy_fa1_s_v4[31:0] ^ xy_fa1_c_v4[31:0] ^ x_v4[127:96]; - assign x_fa2_c_v4[32:0] = {xy_fa1_s_v4[31:0] & xy_fa1_c_v4[31:0] | - x_v4[127:96] & (xy_fa1_s_v4[31:0] | - xy_fa1_c_v4[31:0]), 1'b0}; - - assign y_fa2_s_v4[31:0] = sigma0_v4[31:0] ^ tmajority_v4[31:0] ^ xy_fa1_c_v4[31:0]; - - assign y_fa2_c_v4[32:0] = {sigma0_v4[31:0] & tmajority_v4[31:0] | - xy_fa1_c_v4[31:0] & (sigma0_v4[31:0] | - tmajority_v4[31:0]), 1'b0}; - - - assign y_fa3_s_v4[31:0] = y_fa2_s_v4[31:0] ^ y_fa2_c_v4[31:0] ^ xy_fa1_s_v4[31:0]; - assign y_fa3_c_v4[32:0] = {y_fa2_s_v4[31:0] & y_fa2_c_v4[31:0] | - xy_fa1_s_v4[31:0] & (y_fa2_s_v4[31:0] | - y_fa2_c_v4[31:0]), 1'b0}; - - - assign {xprime_carry, xprime_v4[127:96]} = x_fa2_s_v4[31:0] + x_fa2_c_v4[31:0] + {{31{1'b0}}, 1'b0}; - - - - assign sha256hh2_v4 = sha256h_v4_q | sha256h2_v4_q; - assign sum_sha256h32_v4[31:0] = y_fa3_s_v4[31:0]; - assign carry_sha256h32_v4[31:0] = y_fa3_c_v4[31:0]; - - assign sum4c_v4[31:0] = {32{sha1cpm_v4_q}} & sum_sha1cpm_v4[31:0] | - {32{sha256hh2_v4}} & sum_sha256h32_v4[31:0]; - assign carry4c_v4[31:0] = {32{sha1cpm_v4_q}} & carry_sha1cpm_v4[31:0] | - {32{sha256hh2_v4}} & carry_sha256h32_v4[31:0]; - - assign {unused_cout4c_v4, sumnr4c_v4[31:0]} = sum4c_v4[31:0] + carry4c_v4[31:0] + {{31{1'b0}}, 1'b0}; - - assign yprime_v4[127:96] = sumnr4c_v4[31:0]; - - assign newx_v4[127:0] = {x_v4[95:0], yprime_v4[127:96]}; - assign newy_v4[127:0] = {x_v4[95:0], xprime_v4[127:96]}; - - assign sha256h_x_v4[127:0] = newx_v4[127:0]; - assign sha256h_y_v4[127:0] = newy_v4[127:0]; - - - assign cryptout_v4[63:0] = ({64{sha1cpm_l_v4_q}} & sha1cpm_x_v4[63:0]) - | ({64{sha256h_l_v4_q}} & sha256h_x_v4[63:0]) - | ({64{sha256h2_l_v4_q}} & sha256h_y_v4[63:0]); - - assign cryptout_v4[127:64] = ({64{sha1cpm_h_v4_q}} & sha1cpm_x_v4[127:64]) - | ({64{sha256h_h_v4_q}} & sha256h_x_v4[127:64]) - | ({64{sha256h2_h_v4_q}} & sha256h_y_v4[127:64]); - - - assign crypt_active = ival_v1_or_v2; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_pmull.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_pmull.sv deleted file mode 100644 index 6bc7676814..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_pmull.sv +++ /dev/null @@ -1,257 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_pmull -( - - -input wire clk, - input wire reset, -input wire ival_v1_q, - -input wire [63:0] opa_v1, -input wire [63:0] opb_v1, - -output reg [127:0] pmullout_v2_q -); - - - - - - - - wire [63:0] a_in; - wire [63:0] b_in; - wire [127:0] p_out; - wire [63:0] pp0; - wire [63:0] pp1; - wire [63:0] pp2; - wire [63:0] pp3; - wire [63:0] pp4; - wire [63:0] pp5; - wire [63:0] pp6; - wire [63:0] pp7; - wire [63:0] pp8; - wire [63:0] pp9; - wire [63:0] pp10; - wire [63:0] pp11; - wire [63:0] pp12; - wire [63:0] pp13; - wire [63:0] pp14; - wire [63:0] pp15; - wire [63:0] pp16; - wire [63:0] pp17; - wire [63:0] pp18; - wire [63:0] pp19; - wire [63:0] pp20; - wire [63:0] pp21; - wire [63:0] pp22; - wire [63:0] pp23; - wire [63:0] pp24; - wire [63:0] pp25; - wire [63:0] pp26; - wire [63:0] pp27; - wire [63:0] pp28; - wire [63:0] pp29; - wire [63:0] pp30; - wire [63:0] pp31; - wire [63:0] pp32; - wire [63:0] pp33; - wire [63:0] pp34; - wire [63:0] pp35; - wire [63:0] pp36; - wire [63:0] pp37; - wire [63:0] pp38; - wire [63:0] pp39; - wire [63:0] pp40; - wire [63:0] pp41; - wire [63:0] pp42; - wire [63:0] pp43; - wire [63:0] pp44; - wire [63:0] pp45; - wire [63:0] pp46; - wire [63:0] pp47; - wire [63:0] pp48; - wire [63:0] pp49; - wire [63:0] pp50; - wire [63:0] pp51; - wire [63:0] pp52; - wire [63:0] pp53; - wire [63:0] pp54; - wire [63:0] pp55; - wire [63:0] pp56; - wire [63:0] pp57; - wire [63:0] pp58; - wire [63:0] pp59; - wire [63:0] pp60; - wire [63:0] pp61; - wire [63:0] pp62; - wire [63:0] pp63; - wire [66:0] rednl0_0; - wire [66:0] rednl0_1; - wire [66:0] rednl0_2; - wire [66:0] rednl0_3; - wire [66:0] rednl0_4; - wire [66:0] rednl0_5; - wire [66:0] rednl0_6; - wire [66:0] rednl0_7; - wire [66:0] rednl0_8; - wire [66:0] rednl0_9; - wire [66:0] rednl0_10; - wire [66:0] rednl0_11; - wire [66:0] rednl0_12; - wire [66:0] rednl0_13; - wire [66:0] rednl0_14; - wire [66:0] rednl0_15; - wire [78:0] rednl1_0; - wire [78:0] rednl1_1; - wire [78:0] rednl1_2; - wire [78:0] rednl1_3; - - -assign a_in[63:0] = opa_v1[63:0]; -assign b_in[63:0] = opb_v1[63:0]; -assign pp0[63:0] = {64{a_in[ 0]}} & b_in[63:0]; -assign pp1[63:0] = {64{a_in[ 1]}} & b_in[63:0]; -assign pp2[63:0] = {64{a_in[ 2]}} & b_in[63:0]; -assign pp3[63:0] = {64{a_in[ 3]}} & b_in[63:0]; -assign pp4[63:0] = {64{a_in[ 4]}} & b_in[63:0]; -assign pp5[63:0] = {64{a_in[ 5]}} & b_in[63:0]; -assign pp6[63:0] = {64{a_in[ 6]}} & b_in[63:0]; -assign pp7[63:0] = {64{a_in[ 7]}} & b_in[63:0]; -assign pp8[63:0] = {64{a_in[ 8]}} & b_in[63:0]; -assign pp9[63:0] = {64{a_in[ 9]}} & b_in[63:0]; -assign pp10[63:0] = {64{a_in[10]}} & b_in[63:0]; -assign pp11[63:0] = {64{a_in[11]}} & b_in[63:0]; -assign pp12[63:0] = {64{a_in[12]}} & b_in[63:0]; -assign pp13[63:0] = {64{a_in[13]}} & b_in[63:0]; -assign pp14[63:0] = {64{a_in[14]}} & b_in[63:0]; -assign pp15[63:0] = {64{a_in[15]}} & b_in[63:0]; -assign pp16[63:0] = {64{a_in[16]}} & b_in[63:0]; -assign pp17[63:0] = {64{a_in[17]}} & b_in[63:0]; -assign pp18[63:0] = {64{a_in[18]}} & b_in[63:0]; -assign pp19[63:0] = {64{a_in[19]}} & b_in[63:0]; -assign pp20[63:0] = {64{a_in[20]}} & b_in[63:0]; -assign pp21[63:0] = {64{a_in[21]}} & b_in[63:0]; -assign pp22[63:0] = {64{a_in[22]}} & b_in[63:0]; -assign pp23[63:0] = {64{a_in[23]}} & b_in[63:0]; -assign pp24[63:0] = {64{a_in[24]}} & b_in[63:0]; -assign pp25[63:0] = {64{a_in[25]}} & b_in[63:0]; -assign pp26[63:0] = {64{a_in[26]}} & b_in[63:0]; -assign pp27[63:0] = {64{a_in[27]}} & b_in[63:0]; -assign pp28[63:0] = {64{a_in[28]}} & b_in[63:0]; -assign pp29[63:0] = {64{a_in[29]}} & b_in[63:0]; -assign pp30[63:0] = {64{a_in[30]}} & b_in[63:0]; -assign pp31[63:0] = {64{a_in[31]}} & b_in[63:0]; -assign pp32[63:0] = {64{a_in[32]}} & b_in[63:0]; -assign pp33[63:0] = {64{a_in[33]}} & b_in[63:0]; -assign pp34[63:0] = {64{a_in[34]}} & b_in[63:0]; -assign pp35[63:0] = {64{a_in[35]}} & b_in[63:0]; -assign pp36[63:0] = {64{a_in[36]}} & b_in[63:0]; -assign pp37[63:0] = {64{a_in[37]}} & b_in[63:0]; -assign pp38[63:0] = {64{a_in[38]}} & b_in[63:0]; -assign pp39[63:0] = {64{a_in[39]}} & b_in[63:0]; -assign pp40[63:0] = {64{a_in[40]}} & b_in[63:0]; -assign pp41[63:0] = {64{a_in[41]}} & b_in[63:0]; -assign pp42[63:0] = {64{a_in[42]}} & b_in[63:0]; -assign pp43[63:0] = {64{a_in[43]}} & b_in[63:0]; -assign pp44[63:0] = {64{a_in[44]}} & b_in[63:0]; -assign pp45[63:0] = {64{a_in[45]}} & b_in[63:0]; -assign pp46[63:0] = {64{a_in[46]}} & b_in[63:0]; -assign pp47[63:0] = {64{a_in[47]}} & b_in[63:0]; -assign pp48[63:0] = {64{a_in[48]}} & b_in[63:0]; -assign pp49[63:0] = {64{a_in[49]}} & b_in[63:0]; -assign pp50[63:0] = {64{a_in[50]}} & b_in[63:0]; -assign pp51[63:0] = {64{a_in[51]}} & b_in[63:0]; -assign pp52[63:0] = {64{a_in[52]}} & b_in[63:0]; -assign pp53[63:0] = {64{a_in[53]}} & b_in[63:0]; -assign pp54[63:0] = {64{a_in[54]}} & b_in[63:0]; -assign pp55[63:0] = {64{a_in[55]}} & b_in[63:0]; -assign pp56[63:0] = {64{a_in[56]}} & b_in[63:0]; -assign pp57[63:0] = {64{a_in[57]}} & b_in[63:0]; -assign pp58[63:0] = {64{a_in[58]}} & b_in[63:0]; -assign pp59[63:0] = {64{a_in[59]}} & b_in[63:0]; -assign pp60[63:0] = {64{a_in[60]}} & b_in[63:0]; -assign pp61[63:0] = {64{a_in[61]}} & b_in[63:0]; -assign pp62[63:0] = {64{a_in[62]}} & b_in[63:0]; -assign pp63[63:0] = {64{a_in[63]}} & b_in[63:0]; - -assign rednl0_0[66:0] = { pp3[63:0], 3'b000} ^ {1'b0, pp2[63:0], 2'b00} ^ {2'b00, pp1[63:0], 1'b0} ^ {3'b000, pp0[63:0]}; -assign rednl0_1[66:0] = { pp7[63:0], 3'b000} ^ {1'b0, pp6[63:0], 2'b00} ^ {2'b00, pp5[63:0], 1'b0} ^ {3'b000, pp4[63:0]}; -assign rednl0_2[66:0] = {pp11[63:0], 3'b000} ^ {1'b0, pp10[63:0], 2'b00} ^ {2'b00, pp9[63:0], 1'b0} ^ {3'b000, pp8[63:0]}; -assign rednl0_3[66:0] = {pp15[63:0], 3'b000} ^ {1'b0, pp14[63:0], 2'b00} ^ {2'b00, pp13[63:0], 1'b0} ^ {3'b000, pp12[63:0]}; -assign rednl0_4[66:0] = {pp19[63:0], 3'b000} ^ {1'b0, pp18[63:0], 2'b00} ^ {2'b00, pp17[63:0], 1'b0} ^ {3'b000, pp16[63:0]}; -assign rednl0_5[66:0] = {pp23[63:0], 3'b000} ^ {1'b0, pp22[63:0], 2'b00} ^ {2'b00, pp21[63:0], 1'b0} ^ {3'b000, pp20[63:0]}; -assign rednl0_6[66:0] = {pp27[63:0], 3'b000} ^ {1'b0, pp26[63:0], 2'b00} ^ {2'b00, pp25[63:0], 1'b0} ^ {3'b000, pp24[63:0]}; -assign rednl0_7[66:0] = {pp31[63:0], 3'b000} ^ {1'b0, pp30[63:0], 2'b00} ^ {2'b00, pp29[63:0], 1'b0} ^ {3'b000, pp28[63:0]}; -assign rednl0_8[66:0] = {pp35[63:0], 3'b000} ^ {1'b0, pp34[63:0], 2'b00} ^ {2'b00, pp33[63:0], 1'b0} ^ {3'b000, pp32[63:0]}; -assign rednl0_9[66:0] = {pp39[63:0], 3'b000} ^ {1'b0, pp38[63:0], 2'b00} ^ {2'b00, pp37[63:0], 1'b0} ^ {3'b000, pp36[63:0]}; -assign rednl0_10[66:0] = {pp43[63:0], 3'b000} ^ {1'b0, pp42[63:0], 2'b00} ^ {2'b00, pp41[63:0], 1'b0} ^ {3'b000, pp40[63:0]}; -assign rednl0_11[66:0] = {pp47[63:0], 3'b000} ^ {1'b0, pp46[63:0], 2'b00} ^ {2'b00, pp45[63:0], 1'b0} ^ {3'b000, pp44[63:0]}; -assign rednl0_12[66:0] = {pp51[63:0], 3'b000} ^ {1'b0, pp50[63:0], 2'b00} ^ {2'b00, pp49[63:0], 1'b0} ^ {3'b000, pp48[63:0]}; -assign rednl0_13[66:0] = {pp55[63:0], 3'b000} ^ {1'b0, pp54[63:0], 2'b00} ^ {2'b00, pp53[63:0], 1'b0} ^ {3'b000, pp52[63:0]}; -assign rednl0_14[66:0] = {pp59[63:0], 3'b000} ^ {1'b0, pp58[63:0], 2'b00} ^ {2'b00, pp57[63:0], 1'b0} ^ {3'b000, pp56[63:0]}; -assign rednl0_15[66:0] = {pp63[63:0], 3'b000} ^ {1'b0, pp62[63:0], 2'b00} ^ {2'b00, pp61[63:0], 1'b0} ^ {3'b000, pp60[63:0]}; - -assign rednl1_0[78:0] = { rednl0_3[66:0], 12'h000} ^ {4'h0, rednl0_2[66:0], 8'h00} ^ {8'h00, rednl0_1[66:0], 4'h0} ^ {12'h000, rednl0_0[66:0]}; -assign rednl1_1[78:0] = { rednl0_7[66:0], 12'h000} ^ {4'h0, rednl0_6[66:0], 8'h00} ^ {8'h00, rednl0_5[66:0], 4'h0} ^ {12'h000, rednl0_4[66:0]}; -assign rednl1_2[78:0] = {rednl0_11[66:0], 12'h000} ^ {4'h0, rednl0_10[66:0], 8'h00} ^ {8'h00, rednl0_9[66:0], 4'h0} ^ {12'h000, rednl0_8[66:0]}; -assign rednl1_3[78:0] = {rednl0_15[66:0], 12'h000} ^ {4'h0, rednl0_14[66:0], 8'h00} ^ {8'h00, rednl0_13[66:0], 4'h0} ^ {12'h000, rednl0_12[66:0]}; - -assign p_out[15: 0] = rednl1_0[15: 0]; -assign p_out[31: 16] = rednl1_1[15: 0] ^ rednl1_0[31:16]; -assign p_out[47: 32] = rednl1_2[15: 0] ^ rednl1_1[31:16] ^ rednl1_0[47:32]; -assign p_out[78: 48] = rednl1_3[30: 0] ^ rednl1_2[46:16] ^ rednl1_1[62:32] ^ rednl1_0[78:48]; -assign p_out[94: 79] = rednl1_3[46:31] ^ rednl1_2[62:47] ^ rednl1_1[78:63]; -assign p_out[110: 95] = rednl1_3[62:47] ^ rednl1_2[78:63]; -assign p_out[127:111] = {1'b0, rednl1_3[78:63]}; - - - always_ff @(posedge clk or posedge reset) - begin: u_pmullout_v2_q_127_0 - if (reset == 1'b1) - pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}}; -`ifdef HERCULESAE_XPROP_FLOP - else if (reset == 1'b0 && ival_v1_q == 1'b1) - pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0]; - else if (reset == 1'b0 && ival_v1_q == 1'b0) - begin - end - else - pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}}; -`else - else if (ival_v1_q == 1'b1) - pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0]; -`endif - end - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1.sv deleted file mode 100644 index 6635959363..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1.sv +++ /dev/null @@ -1,78 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_sha1 -( - - - input wire sha1h_v1_i, - input wire sha1su0_v1_i, - input wire sha1su1_v1_i, - input wire [31:0] sha1h_qn, - input wire [127:0] sha1su0_qd, - input wire [127:0] sha1su1_qd, - input wire [127:0] sha1su1_qn, - - output wire [127:0] sha1_v1_o -); - - - - - - - - wire [31:0] sha1h_v1; - wire [63:0] sha1su0_opa_v1; - wire [127:0] sha1su0_opb_v1; - wire [127:0] sha1su0_opc_v1; - wire [127:0] sha1su0_v1; - wire [127:0] sha1su1_v1; - wire [127:0] t; - - assign sha1h_v1[31:0] = {sha1h_qn[1:0], sha1h_qn[31:2]}; - - assign sha1su0_opa_v1[63:0] = sha1su1_qn[63:0]; - assign sha1su0_opb_v1[127:0] = sha1su1_qd[127:0]; - assign sha1su0_opc_v1[127:0] = sha1su0_qd[127:0]; - - assign sha1su0_v1 [127:0] = sha1su0_opc_v1[127:0] - ^ {sha1su0_opa_v1[63:0], sha1su0_opc_v1[127:64]} - ^ sha1su0_opb_v1[127:0]; - assign t[127:0] = sha1su1_qd[127:0] ^ {{32{1'b0}}, sha1su1_qn[127:32]}; - assign sha1su1_v1[127:96] = {t[126:96], t[127]} ^ {t[29:0], t[31:30]}; - assign sha1su1_v1[95:64] = {t[94:64], t[95]}; - assign sha1su1_v1[63:32] = {t[62:32], t[63]}; - assign sha1su1_v1[31:0] = {t[30:0], t[31]}; - - assign sha1_v1_o[127:0] = {128{sha1su0_v1_i}} & sha1su0_v1[127:0] | - {128{sha1su1_v1_i}} & sha1su1_v1[127:0] | - {128{sha1h_v1_i}} & {{96{1'b0}}, sha1h_v1[31:0]}; -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1cpm.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1cpm.sv deleted file mode 100644 index c012dafd0e..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1cpm.sv +++ /dev/null @@ -1,101 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_sha1cpm -( - - - input wire choose, - input wire parity, - input wire majority, - input wire cpm, - input wire [127:0] x, - input wire [31:0] y, - input wire [31:0] z, - input wire [31:0] t2, - output wire [31:0] fa1_s, - output wire [31:0] fa1_c, - output wire [127:0] newx, - output wire [31:0] newy -); - - - - - - - - wire [32:0] fa0_c; - wire [31:0] fa0_s; - wire shacpm_nop; - wire [31:0] t1_nop; - wire [31:0] t1c; - wire [31:0] t1m; - wire [31:0] t1p; - wire [127:0] x1; - wire [127:0] x_nop; - wire [31:0] x_rol5_nop; - wire [31:0] y_nop; - wire [31:0] z_nop; - - assign shacpm_nop = ~cpm; - - - assign t1c[31:0] = (x[63:32] & x[95:64]) | (~x[63:32] & x[127:96]); - assign t1p[31:0] = x[63:32] ^ x[95:64] ^ x[127:96]; - assign t1m[31:0] = (x[63:32] & x[95:64]) - | (x[63:32] & x[127:96]) - | (x[95:64] & x[127:96]); - assign t1_nop[31:0] = ({32{choose}} & t1c[31:0]) - | ({32{parity}} & t1p[31:0]) - | ({32{majority}} & t1m[31:0]); - assign x_rol5_nop[31:0] = {32{~shacpm_nop}} & {x[26:0], x[31:27]}; - - - assign y_nop[31:0] = {32{~shacpm_nop}} & y[31:0]; - assign z_nop[31:0] = {32{~shacpm_nop}} & z[31:0]; - - assign fa0_s[31:0] = y_nop[31:0] ^ x_rol5_nop[31:0] ^ z_nop[31:0]; - assign fa0_c[32:0] = {y_nop[31:0] & x_rol5_nop[31:0] | z_nop[31:0] & (y_nop[31:0] | x_rol5_nop[31:0]), 1'b0}; - - assign fa1_s[31:0] = fa0_s[31:0] ^ fa0_c[31:0] ^ t1_nop[31:0]; - assign fa1_c[31:0] = {fa0_s[30:0] & fa0_c[30:0] | t1_nop[30:0] & (fa0_s[30:0] | fa0_c[30:0]), 1'b0}; - - - assign x_nop[127:0] = {128{~shacpm_nop}} & x[127:0]; - - assign x1[127:64] = x_nop[127:64]; - assign x1[63:32] = {x_nop[33:32], x_nop[63:34]}; - assign x1[31:0] = x_nop[31:0]; - - assign newx[127:0] = {x1[95:0], t2[31:0]}; - assign newy[31:0] = x1[127:96]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256h32.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256h32.sv deleted file mode 100644 index 6ba1162776..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256h32.sv +++ /dev/null @@ -1,104 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_sha256h32 -( - - - input wire [127:0] x, - input wire [127:0] y, - input wire [31:0] z, - - input wire [63:0] sumnr, - output wire [63:0] sum, - output wire [63:0] carry, - output wire [127:0] newx, - output wire [127:0] newy -); - - - - - - - - wire [31:0] sigma0; - wire [31:0] sigma1; - wire [31:0] tchoose; - wire [31:0] tmajority; - wire [32:0] x_fa2_c; - wire [31:0] x_fa2_s; - wire [127:96] xprime; - wire [32:0] xy_fa0_c; - wire [31:0] xy_fa0_s; - wire [32:0] xy_fa1_c; - wire [31:0] xy_fa1_s; - wire [32:0] y_fa2_c; - wire [31:0] y_fa2_s; - wire [31:0] y_fa3_c; - wire [31:0] y_fa3_s; - wire [127:96] yprime; - - - assign tchoose[31:0] = (y[31:0] & y[63:32]) | (~y[31:0] & y[95:64]); - assign tmajority[31:0] = (x[31:0] & x[63:32]) | (x[31:0] & x[95:64]) | (x[63:32] & x[95:64]); - assign sigma0[31:0] = {x[1:0], x[31:2]} - ^ {x[12:0], x[31:13]} - ^ {x[21:0], x[31:22]}; - assign sigma1[31:0] = {y[5:0], y[31:6]} - ^ {y[10:0], y[31:11]} - ^ {y[24:0], y[31:25]}; - - - assign xy_fa0_s[31:0] = y[127:96] ^ z[31:0] ^ tchoose[31:0]; - assign xy_fa0_c[32:0] = {y[127:96] & z[31:0] | tchoose[31:0] & (y[127:96] | z[31:0]), 1'b0}; - - assign xy_fa1_s[31:0] = xy_fa0_s[31:0] ^ xy_fa0_c[31:0] ^ sigma1[31:0]; - assign xy_fa1_c[32:0] = {xy_fa0_s[31:0] & xy_fa0_c[31:0] | sigma1[31:0] & (xy_fa0_s[31:0] | xy_fa0_c[31:0]), 1'b0}; - - assign x_fa2_s[31:0] = xy_fa1_s[31:0] ^ xy_fa1_c[31:0] ^ x[127:96]; - assign x_fa2_c[32:0] = {xy_fa1_s[31:0] & xy_fa1_c[31:0] | x[127:96] & (xy_fa1_s[31:0] | xy_fa1_c[31:0]), 1'b0}; - - assign y_fa2_s[31:0] = sigma0[31:0] ^ tmajority[31:0] ^ xy_fa1_c[31:0]; - assign y_fa2_c[32:0] = {sigma0[31:0] & tmajority[31:0] | xy_fa1_c[31:0] & (sigma0[31:0] | tmajority[31:0]), 1'b0}; - - assign y_fa3_s[31:0] = y_fa2_s[31:0] ^ y_fa2_c[31:0] ^ xy_fa1_s[31:0]; - assign y_fa3_c[31:0] = {y_fa2_s[30:0] & y_fa2_c[30:0] | xy_fa1_s[30:0] & (y_fa2_s[30:0] | y_fa2_c[30:0]), 1'b0}; - - assign sum[63:0] = {x_fa2_s[31:0], y_fa3_s[31:0]}; - assign carry[63:0] = {x_fa2_c[31:0], y_fa3_c[31:0]}; - assign xprime[127:96] = sumnr[63:32]; - assign yprime[127:96] = sumnr[31:0]; - - assign newx[127:0] = {x[95:0], yprime[127:96]}; - assign newy[127:0] = {y[95:0], xprime[127:96]}; - -endmodule - - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su0.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su0.sv deleted file mode 100644 index da335c1cc1..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su0.sv +++ /dev/null @@ -1,76 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_sha256su0 -( - - - input wire [127:0] qd, - input wire [31:0] qn, - input wire [31:0] sumd, - output wire [31:0] suma, - output wire [31:0] sumb, - output wire [127:0] d -); - - - - - - - - wire d1_cout; - wire d2_cout; - wire d3_cout; - wire [127:0] t; - wire [127:0] t0; - -assign t[127:0] = {qn[31:0], qd[127:32]}; -assign t0[127:96] = {t[102:96], t[127:103]} ^ {t[113:96], t[127:114]} ^ {3'b000, t[127:99]}; -assign t0[95:64] = {t[ 70:64], t[ 95: 71]} ^ {t[ 81:64], t[ 95: 82]} ^ {3'b000, t[ 95:67]}; -assign t0[63:32] = {t[ 38:32], t[ 63: 39]} ^ {t[ 49:32], t[ 63: 50]} ^ {3'b000, t[ 63:35]}; -assign t0[31:0] = {t[ 6: 0], t[ 31: 7]} ^ {t[ 17: 0], t[ 31: 18]} ^ {3'b000, t[ 31: 3]}; - - - assign {d3_cout, d[127:96]} = t0[127:96] + qd[127:96] + {{31{1'b0}}, 1'b0}; - - - assign {d2_cout, d[95:64]} = t0[95:64] + qd[95:64] + {{31{1'b0}}, 1'b0}; - - - assign {d1_cout, d[63:32]} = t0[63:32] + qd[63:32] + {{31{1'b0}}, 1'b0}; - - -assign suma[31:0] = t0[31:0]; -assign sumb[31:0] = qd[31:0]; -assign d[31:0] = sumd[31:0]; - - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su1.sv b/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su1.sv deleted file mode 100644 index 9c1284ddfe..0000000000 --- a/Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su1.sv +++ /dev/null @@ -1,90 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//----------------------------------------------------------------------------- -// SystemVerilog (IEEE Std 1800-2012) -//----------------------------------------------------------------------------- - - - - -`include "herculesae_header.sv" - - -module herculesae_vx_sha256su1 -( - - - input wire sha256su1_x_op, - input wire sha256su1_y_op, - input wire sha256su1_z_op, - input wire [63:0] x, - input wire [63:0] y, - input wire [63:0] z, - input wire [63:0] sumnr, - output wire [63:0] sum_3to2, - output wire [63:0] carry_3to2, - output wire [63:0] newx -); - - - - - - - - wire [63:0] carry; - wire [63:0] sum; - wire [63:0] x_nop; - wire [63:0] y_nop; - wire [63:0] z_nop; - wire [63:0] z_rot; - wire [63:0] zror17; - wire [63:0] zror19; - wire [63:0] zshr10; - - - - -assign x_nop[63:0] = x[63:0] & {64{sha256su1_x_op}}; -assign y_nop[63:0] = y[63:0] & {64{sha256su1_y_op}}; -assign z_nop[63:0] = z[63:0] & {64{sha256su1_z_op}}; - -assign zror17[63:0] = {z_nop[48:32], z_nop[63:49], - z_nop[16:0], z_nop[31:17]}; -assign zror19[63:0] = {z_nop[50:32], z_nop[63:51], - z_nop[18:0], z_nop[31:19]}; -assign zshr10[63:0] = {10'b00_0000_0000, z_nop[63:42], - 10'b00_0000_0000, z_nop[31:10]}; -assign z_rot[63:0] = zror17[63:0] ^ zror19[63:0] ^ zshr10[63:0]; - -assign sum[63:0] = (x_nop[63:0] ^ y_nop[63:0]) ^ z_rot[63:0]; -assign carry[63:32] = {(x_nop[62:32] & y_nop[62:32]) - | (y_nop[62:32] & z_rot[62:32]) - | (x_nop[62:32] & z_rot[62:32]), 1'b0}; -assign carry[31:0] = {(x_nop[30:0] & y_nop[30:0]) - | (y_nop[30:0] & z_rot[30:0]) - | (x_nop[30:0] & z_rot[30:0]), 1'b0}; - -assign sum_3to2[63:0] = sum[63:0]; -assign carry_3to2[63:0] = carry[63:0]; -assign newx[63:0] = sumnr[63:0]; - -endmodule - - -`define HERCULESAE_UNDEFINE -`include "herculesae_header.sv" -`undef HERCULESAE_UNDEFINE diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA.v b/Security Algo Accelerator/logical/maia/verilog/MAIA.v deleted file mode 100644 index 49910c358c..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA.v +++ /dev/null @@ -1,4802 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu unoncpu( // outputs - .ACREADYM (ACREADYM), - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WACKM (WACKM), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACADDRM (ACADDRM[43:0]), - .ACINACTM (ACINACTM), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRREADYM (CRREADYM), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v deleted file mode 100644 index e5bfc42be7..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v +++ /dev/null @@ -1,4801 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA_feq20.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA_feq20 top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA_feq20 ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu_feq20 unoncpu( // outputs - .ACREADYM (ACREADYM), - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WACKM (WACKM), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACADDRM (ACADDRM[43:0]), - .ACINACTM (ACINACTM), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRREADYM (CRREADYM), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA_feq20 - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v deleted file mode 100644 index 4f3003bd3f..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v +++ /dev/null @@ -1,4821 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA_feq20.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA_feq20 top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA_feq20_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu_feq20_s unoncpu( // outputs - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARREADYS (ARREADYS), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WREADYS (WREADYS), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACLKENS (ACLKENS), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .NODEID (NODEID[6:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RREADYS (RREADYS), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SINACT (SINACT), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA_feq20_s - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v deleted file mode 100644 index 8295b03241..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v +++ /dev/null @@ -1,4801 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA_feq28.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA_feq28 top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA_feq28 ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu_feq28 unoncpu( // outputs - .ACREADYM (ACREADYM), - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WACKM (WACKM), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACADDRM (ACADDRM[43:0]), - .ACINACTM (ACINACTM), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRREADYM (CRREADYM), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA_feq28 - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v deleted file mode 100644 index e3c19e8f3f..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v +++ /dev/null @@ -1,4821 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA_feq28.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA_feq28 top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA_feq28_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu_feq28_s unoncpu( // outputs - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARREADYS (ARREADYS), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WREADYS (WREADYS), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACLKENS (ACLKENS), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .NODEID (NODEID[6:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RREADYS (RREADYS), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SINACT (SINACT), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA_feq28_s - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v deleted file mode 100644 index 1b2ee6a6eb..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v +++ /dev/null @@ -1,4821 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: MAIA.v $ -// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ -// Revision : $Revision: 71806 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the MAIA top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module MAIA_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - - - // wires - wire aa64naa32_cpu0_o; - wire aa64naa32_cpu1_o; - wire aa64naa32_cpu2_o; - wire aa64naa32_cpu3_o; - wire afreadym_cpu0_i; - wire afreadym_cpu1_i; - wire afreadym_cpu2_i; - wire afreadym_cpu3_i; - wire afvalidm_cpu0_o; - wire afvalidm_cpu1_o; - wire afvalidm_cpu2_o; - wire afvalidm_cpu3_o; - wire [1:0] atbytesm_cpu0_i; - wire [1:0] atbytesm_cpu1_i; - wire [1:0] atbytesm_cpu2_i; - wire [1:0] atbytesm_cpu3_i; - wire atclken_cpu0_o; - wire atclken_cpu1_o; - wire atclken_cpu2_o; - wire atclken_cpu3_o; - wire [31:0] atdatam_cpu0_i; - wire [31:0] atdatam_cpu1_i; - wire [31:0] atdatam_cpu2_i; - wire [31:0] atdatam_cpu3_i; - wire [6:0] atidm_cpu0_i; - wire [6:0] atidm_cpu1_i; - wire [6:0] atidm_cpu2_i; - wire [6:0] atidm_cpu3_i; - wire atreadym_cpu0_o; - wire atreadym_cpu1_o; - wire atreadym_cpu2_o; - wire atreadym_cpu3_o; - wire atvalidm_cpu0_i; - wire atvalidm_cpu1_i; - wire atvalidm_cpu2_i; - wire atvalidm_cpu3_i; - wire cfgend_cpu0_o; - wire cfgend_cpu1_o; - wire cfgend_cpu2_o; - wire cfgend_cpu3_o; - wire cfgte_cpu0_o; - wire cfgte_cpu1_o; - wire cfgte_cpu2_o; - wire cfgte_cpu3_o; - wire ck_cpu0_crcx_clk_en_n; - wire ck_cpu0_event_reg; - wire ck_cpu0_wfe_ack; - wire ck_cpu0_wfi_ack; - wire ck_cpu1_crcx_clk_en_n; - wire ck_cpu1_event_reg; - wire ck_cpu1_wfe_ack; - wire ck_cpu1_wfi_ack; - wire ck_cpu2_crcx_clk_en_n; - wire ck_cpu2_event_reg; - wire ck_cpu2_wfe_ack; - wire ck_cpu2_wfi_ack; - wire ck_cpu3_crcx_clk_en_n; - wire ck_cpu3_event_reg; - wire ck_cpu3_wfe_ack; - wire ck_cpu3_wfi_ack; - wire [`MAIA_CN:0] ck_gclkt; - wire [7:0] clusteridaff1_cpu0_o; - wire [7:0] clusteridaff1_cpu1_o; - wire [7:0] clusteridaff1_cpu2_o; - wire [7:0] clusteridaff1_cpu3_o; - wire [7:0] clusteridaff2_cpu0_o; - wire [7:0] clusteridaff2_cpu1_o; - wire [7:0] clusteridaff2_cpu2_o; - wire [7:0] clusteridaff2_cpu3_o; - wire commrx_cpu0_i; - wire commrx_cpu1_i; - wire commrx_cpu2_i; - wire commrx_cpu3_i; - wire commtx_cpu0_i; - wire commtx_cpu1_i; - wire commtx_cpu2_i; - wire commtx_cpu3_i; - wire cp15sdisable_cpu0_o; - wire cp15sdisable_cpu1_o; - wire cp15sdisable_cpu2_o; - wire cp15sdisable_cpu3_o; - wire [1:0] cpuid_cpu0_o; - wire [1:0] cpuid_cpu1_o; - wire [1:0] cpuid_cpu2_o; - wire [1:0] cpuid_cpu3_o; - wire cryptodisable_cpu0_o; - wire cryptodisable_cpu1_o; - wire cryptodisable_cpu2_o; - wire cryptodisable_cpu3_o; - wire dbgack_cpu0_i; - wire dbgack_cpu1_i; - wire dbgack_cpu2_i; - wire dbgack_cpu3_i; - wire dbgen_cpu0_o; - wire dbgen_cpu1_o; - wire dbgen_cpu2_o; - wire dbgen_cpu3_o; - wire dbgl1rstdisable_cpu0_o; - wire dbgl1rstdisable_cpu1_o; - wire dbgl1rstdisable_cpu2_o; - wire dbgl1rstdisable_cpu3_o; - wire dbgnopwrdwn_cpu0_i; - wire dbgnopwrdwn_cpu1_i; - wire dbgnopwrdwn_cpu2_i; - wire dbgnopwrdwn_cpu3_i; - wire [43:12] dbgromaddr_cpu0_o; - wire [43:12] dbgromaddr_cpu1_o; - wire [43:12] dbgromaddr_cpu2_o; - wire [43:12] dbgromaddr_cpu3_o; - wire dbgromaddrv_cpu0_o; - wire dbgromaddrv_cpu1_o; - wire dbgromaddrv_cpu2_o; - wire dbgromaddrv_cpu3_o; - wire dbgrstreq_cpu0_i; - wire dbgrstreq_cpu1_i; - wire dbgrstreq_cpu2_i; - wire dbgrstreq_cpu3_i; - wire dftcrclkdisable_cpu0_o; - wire dftcrclkdisable_cpu1_o; - wire dftcrclkdisable_cpu2_o; - wire dftcrclkdisable_cpu3_o; - wire dftramhold_cpu0_o; - wire dftramhold_cpu1_o; - wire dftramhold_cpu2_o; - wire dftramhold_cpu3_o; - wire dftrstdisable_cpu0_o; - wire dftrstdisable_cpu1_o; - wire dftrstdisable_cpu2_o; - wire dftrstdisable_cpu3_o; - wire dftse_cpu0_o; - wire dftse_cpu1_o; - wire dftse_cpu2_o; - wire dftse_cpu3_o; - wire [2:0] ds_cpu0_cpuectlr_ret; - wire ds_cpu0_cpuectlr_smp; - wire ds_cpu0_fiq_wfe_qual; - wire ds_cpu0_fiq_wfi_qual; - wire ds_cpu0_flush; - wire [5:0] ds_cpu0_flush_type; - wire ds_cpu0_hcr_va; - wire ds_cpu0_hcr_vf; - wire ds_cpu0_hcr_vi; - wire ds_cpu0_ic_aa64naa32; - wire [4:0] ds_cpu0_ic_cpsr_mode; - wire ds_cpu0_ic_hcr_change; - wire ds_cpu0_ic_sample_spr; - wire ds_cpu0_ic_scr_change; - wire ds_cpu0_imp_abrt_wfe_qual; - wire ds_cpu0_imp_abrt_wfi_qual; - wire ds_cpu0_irq_wfe_qual; - wire ds_cpu0_irq_wfi_qual; - wire [8:0] ds_cpu0_l2_spr_addr; - wire ds_cpu0_l2_spr_dw; - wire ds_cpu0_l2_spr_en; - wire ds_cpu0_l2_spr_rd; - wire ds_cpu0_l2_spr_wr; - wire [63:0] ds_cpu0_l2_spr_wr_data; - wire ds_cpu0_reset_req; - wire ds_cpu0_sev_req; - wire ds_cpu0_sevl_req; - wire ds_cpu0_vfiq_wfe_qual; - wire ds_cpu0_vfiq_wfi_qual; - wire ds_cpu0_vimp_abrt_wfe_qual; - wire ds_cpu0_vimp_abrt_wfi_qual; - wire ds_cpu0_virq_wfe_qual; - wire ds_cpu0_virq_wfi_qual; - wire ds_cpu0_wfe_req; - wire ds_cpu0_wfi_req; - wire [2:0] ds_cpu1_cpuectlr_ret; - wire ds_cpu1_cpuectlr_smp; - wire ds_cpu1_fiq_wfe_qual; - wire ds_cpu1_fiq_wfi_qual; - wire ds_cpu1_flush; - wire [5:0] ds_cpu1_flush_type; - wire ds_cpu1_hcr_va; - wire ds_cpu1_hcr_vf; - wire ds_cpu1_hcr_vi; - wire ds_cpu1_ic_aa64naa32; - wire [4:0] ds_cpu1_ic_cpsr_mode; - wire ds_cpu1_ic_hcr_change; - wire ds_cpu1_ic_sample_spr; - wire ds_cpu1_ic_scr_change; - wire ds_cpu1_imp_abrt_wfe_qual; - wire ds_cpu1_imp_abrt_wfi_qual; - wire ds_cpu1_irq_wfe_qual; - wire ds_cpu1_irq_wfi_qual; - wire [8:0] ds_cpu1_l2_spr_addr; - wire ds_cpu1_l2_spr_dw; - wire ds_cpu1_l2_spr_en; - wire ds_cpu1_l2_spr_rd; - wire ds_cpu1_l2_spr_wr; - wire [63:0] ds_cpu1_l2_spr_wr_data; - wire ds_cpu1_reset_req; - wire ds_cpu1_sev_req; - wire ds_cpu1_sevl_req; - wire ds_cpu1_vfiq_wfe_qual; - wire ds_cpu1_vfiq_wfi_qual; - wire ds_cpu1_vimp_abrt_wfe_qual; - wire ds_cpu1_vimp_abrt_wfi_qual; - wire ds_cpu1_virq_wfe_qual; - wire ds_cpu1_virq_wfi_qual; - wire ds_cpu1_wfe_req; - wire ds_cpu1_wfi_req; - wire [2:0] ds_cpu2_cpuectlr_ret; - wire ds_cpu2_cpuectlr_smp; - wire ds_cpu2_fiq_wfe_qual; - wire ds_cpu2_fiq_wfi_qual; - wire ds_cpu2_flush; - wire [5:0] ds_cpu2_flush_type; - wire ds_cpu2_hcr_va; - wire ds_cpu2_hcr_vf; - wire ds_cpu2_hcr_vi; - wire ds_cpu2_ic_aa64naa32; - wire [4:0] ds_cpu2_ic_cpsr_mode; - wire ds_cpu2_ic_hcr_change; - wire ds_cpu2_ic_sample_spr; - wire ds_cpu2_ic_scr_change; - wire ds_cpu2_imp_abrt_wfe_qual; - wire ds_cpu2_imp_abrt_wfi_qual; - wire ds_cpu2_irq_wfe_qual; - wire ds_cpu2_irq_wfi_qual; - wire [8:0] ds_cpu2_l2_spr_addr; - wire ds_cpu2_l2_spr_dw; - wire ds_cpu2_l2_spr_en; - wire ds_cpu2_l2_spr_rd; - wire ds_cpu2_l2_spr_wr; - wire [63:0] ds_cpu2_l2_spr_wr_data; - wire ds_cpu2_reset_req; - wire ds_cpu2_sev_req; - wire ds_cpu2_sevl_req; - wire ds_cpu2_vfiq_wfe_qual; - wire ds_cpu2_vfiq_wfi_qual; - wire ds_cpu2_vimp_abrt_wfe_qual; - wire ds_cpu2_vimp_abrt_wfi_qual; - wire ds_cpu2_virq_wfe_qual; - wire ds_cpu2_virq_wfi_qual; - wire ds_cpu2_wfe_req; - wire ds_cpu2_wfi_req; - wire [2:0] ds_cpu3_cpuectlr_ret; - wire ds_cpu3_cpuectlr_smp; - wire ds_cpu3_fiq_wfe_qual; - wire ds_cpu3_fiq_wfi_qual; - wire ds_cpu3_flush; - wire [5:0] ds_cpu3_flush_type; - wire ds_cpu3_hcr_va; - wire ds_cpu3_hcr_vf; - wire ds_cpu3_hcr_vi; - wire ds_cpu3_ic_aa64naa32; - wire [4:0] ds_cpu3_ic_cpsr_mode; - wire ds_cpu3_ic_hcr_change; - wire ds_cpu3_ic_sample_spr; - wire ds_cpu3_ic_scr_change; - wire ds_cpu3_imp_abrt_wfe_qual; - wire ds_cpu3_imp_abrt_wfi_qual; - wire ds_cpu3_irq_wfe_qual; - wire ds_cpu3_irq_wfi_qual; - wire [8:0] ds_cpu3_l2_spr_addr; - wire ds_cpu3_l2_spr_dw; - wire ds_cpu3_l2_spr_en; - wire ds_cpu3_l2_spr_rd; - wire ds_cpu3_l2_spr_wr; - wire [63:0] ds_cpu3_l2_spr_wr_data; - wire ds_cpu3_reset_req; - wire ds_cpu3_sev_req; - wire ds_cpu3_sevl_req; - wire ds_cpu3_vfiq_wfe_qual; - wire ds_cpu3_vfiq_wfi_qual; - wire ds_cpu3_vimp_abrt_wfe_qual; - wire ds_cpu3_vimp_abrt_wfi_qual; - wire ds_cpu3_virq_wfe_qual; - wire ds_cpu3_virq_wfi_qual; - wire ds_cpu3_wfe_req; - wire ds_cpu3_wfi_req; - wire dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; - wire dt_cpu0_cti_trigoutack_bit1_gclk; - wire dt_cpu0_dbif_ack_gclk; - wire [14:2] dt_cpu0_dbif_addr_pclk; - wire dt_cpu0_dbif_err_gclk; - wire dt_cpu0_dbif_locked_pclk; - wire [31:0] dt_cpu0_dbif_rddata_gclk; - wire dt_cpu0_dbif_req_pclk; - wire [31:0] dt_cpu0_dbif_wrdata_pclk; - wire dt_cpu0_dbif_write_pclk; - wire dt_cpu0_edacr_frc_idleack_pclk; - wire dt_cpu0_edbgrq_pclk; - wire dt_cpu0_edecr_osuce_pclk; - wire dt_cpu0_edecr_rce_pclk; - wire dt_cpu0_edecr_ss_pclk; - wire dt_cpu0_edprcr_corepurq_pclk; - wire dt_cpu0_et_oslock_gclk; - wire dt_cpu0_halt_ack_gclk; - wire dt_cpu0_hlt_dbgevt_ok_gclk; - wire dt_cpu0_noclkstop_pclk; - wire dt_cpu0_os_double_lock_gclk; - wire dt_cpu0_pmusnapshot_ack_gclk; - wire dt_cpu0_pmusnapshot_req_pclk; - wire dt_cpu0_wfx_dbg_req_gclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; - wire dt_cpu1_cti_trigoutack_bit1_gclk; - wire dt_cpu1_dbif_ack_gclk; - wire [14:2] dt_cpu1_dbif_addr_pclk; - wire dt_cpu1_dbif_err_gclk; - wire dt_cpu1_dbif_locked_pclk; - wire [31:0] dt_cpu1_dbif_rddata_gclk; - wire dt_cpu1_dbif_req_pclk; - wire [31:0] dt_cpu1_dbif_wrdata_pclk; - wire dt_cpu1_dbif_write_pclk; - wire dt_cpu1_edacr_frc_idleack_pclk; - wire dt_cpu1_edbgrq_pclk; - wire dt_cpu1_edecr_osuce_pclk; - wire dt_cpu1_edecr_rce_pclk; - wire dt_cpu1_edecr_ss_pclk; - wire dt_cpu1_edprcr_corepurq_pclk; - wire dt_cpu1_et_oslock_gclk; - wire dt_cpu1_halt_ack_gclk; - wire dt_cpu1_hlt_dbgevt_ok_gclk; - wire dt_cpu1_noclkstop_pclk; - wire dt_cpu1_os_double_lock_gclk; - wire dt_cpu1_pmusnapshot_ack_gclk; - wire dt_cpu1_pmusnapshot_req_pclk; - wire dt_cpu1_wfx_dbg_req_gclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; - wire dt_cpu2_cti_trigoutack_bit1_gclk; - wire dt_cpu2_dbif_ack_gclk; - wire [14:2] dt_cpu2_dbif_addr_pclk; - wire dt_cpu2_dbif_err_gclk; - wire dt_cpu2_dbif_locked_pclk; - wire [31:0] dt_cpu2_dbif_rddata_gclk; - wire dt_cpu2_dbif_req_pclk; - wire [31:0] dt_cpu2_dbif_wrdata_pclk; - wire dt_cpu2_dbif_write_pclk; - wire dt_cpu2_edacr_frc_idleack_pclk; - wire dt_cpu2_edbgrq_pclk; - wire dt_cpu2_edecr_osuce_pclk; - wire dt_cpu2_edecr_rce_pclk; - wire dt_cpu2_edecr_ss_pclk; - wire dt_cpu2_edprcr_corepurq_pclk; - wire dt_cpu2_et_oslock_gclk; - wire dt_cpu2_halt_ack_gclk; - wire dt_cpu2_hlt_dbgevt_ok_gclk; - wire dt_cpu2_noclkstop_pclk; - wire dt_cpu2_os_double_lock_gclk; - wire dt_cpu2_pmusnapshot_ack_gclk; - wire dt_cpu2_pmusnapshot_req_pclk; - wire dt_cpu2_wfx_dbg_req_gclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; - wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; - wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; - wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; - wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; - wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; - wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; - wire dt_cpu3_cti_trigoutack_bit1_gclk; - wire dt_cpu3_dbif_ack_gclk; - wire [14:2] dt_cpu3_dbif_addr_pclk; - wire dt_cpu3_dbif_err_gclk; - wire dt_cpu3_dbif_locked_pclk; - wire [31:0] dt_cpu3_dbif_rddata_gclk; - wire dt_cpu3_dbif_req_pclk; - wire [31:0] dt_cpu3_dbif_wrdata_pclk; - wire dt_cpu3_dbif_write_pclk; - wire dt_cpu3_edacr_frc_idleack_pclk; - wire dt_cpu3_edbgrq_pclk; - wire dt_cpu3_edecr_osuce_pclk; - wire dt_cpu3_edecr_rce_pclk; - wire dt_cpu3_edecr_ss_pclk; - wire dt_cpu3_edprcr_corepurq_pclk; - wire dt_cpu3_et_oslock_gclk; - wire dt_cpu3_halt_ack_gclk; - wire dt_cpu3_hlt_dbgevt_ok_gclk; - wire dt_cpu3_noclkstop_pclk; - wire dt_cpu3_os_double_lock_gclk; - wire dt_cpu3_pmusnapshot_ack_gclk; - wire dt_cpu3_pmusnapshot_req_pclk; - wire dt_cpu3_wfx_dbg_req_gclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire etclken_cpu0_i; - wire etclken_cpu1_i; - wire etclken_cpu2_i; - wire etclken_cpu3_i; - wire giccdisable_cpu0_o; - wire giccdisable_cpu1_o; - wire giccdisable_cpu2_o; - wire giccdisable_cpu3_o; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; - wire [`MAIA_CN:0] ic_el_change_complete; - wire [`MAIA_CN:0] ic_hcr_change_complete; - wire [`MAIA_CN:0] ic_ich_el2_tall0; - wire [`MAIA_CN:0] ic_ich_el2_tall1; - wire [`MAIA_CN:0] ic_ich_el2_tc; - wire [`MAIA_CN:0] ic_nfiq; - wire [`MAIA_CN:0] ic_nirq; - wire [`MAIA_CN:0] ic_nsei; - wire [`MAIA_CN:0] ic_nvfiq; - wire [`MAIA_CN:0] ic_nvirq; - wire [`MAIA_CN:0] ic_nvsei; - wire [`MAIA_CN:0] ic_p_valid; - wire [`MAIA_CN:0] ic_sample_spr; - wire [`MAIA_CN:0] ic_scr_change_complete; - wire [`MAIA_CN:0] ic_sra_el1ns_en; - wire [`MAIA_CN:0] ic_sra_el1s_en; - wire [`MAIA_CN:0] ic_sra_el2_en; - wire [`MAIA_CN:0] ic_sra_el3_en; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap; - wire l2_cpu0_arb_thrshld_timeout_en; - wire l2_cpu0_barrier_done; - wire l2_cpu0_blk_non_evict_wr; - wire l2_cpu0_ccb_dbg_req_c3; - wire [48:0] l2_cpu0_ccb_req_addr_c3; - wire [4:0] l2_cpu0_ccb_req_id_c3; - wire [23:0] l2_cpu0_ccb_req_info_c3; - wire [8:0] l2_cpu0_ccb_req_type_c3; - wire l2_cpu0_cfg_ecc_en; - wire [2:0] l2_cpu0_dbufid_r1; - wire [129:0] l2_cpu0_ddata_r2; - wire l2_cpu0_ddlb_ecc_err_r3; - wire l2_cpu0_dext_err_r2; - wire l2_cpu0_dext_err_type_r2; - wire l2_cpu0_disable_clean_evict_opt; - wire l2_cpu0_dlast_r1; - wire l2_cpu0_dsngl_ecc_err_r3; - wire [3:0] l2_cpu0_dsq_clr_id_q; - wire l2_cpu0_dsq_clr_vld_q; - wire [3:0] l2_cpu0_dsq_rd_buf_id; - wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu0_dsq_rd_data_q; - wire l2_cpu0_dsq_rd_en; - wire l2_cpu0_dsq_rd_en_x2; - wire l2_cpu0_dt_pmu_evt_en; - wire l2_cpu0_dvalid_r1; - wire l2_cpu0_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; - wire l2_cpu0_flsh_if_rd_l4_dly; - wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; - wire l2_cpu0_flsh_ls_rd_l2_dly; - wire l2_cpu0_flsh_ls_rd_l4_dly; - wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; - wire l2_cpu0_flsh_ls_wr_l2_dly; - wire l2_cpu0_flsh_ls_wr_l4_dly; - wire l2_cpu0_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu0_ibufid_r1; - wire [15:0] l2_cpu0_ic_addr_arb_set; - wire l2_cpu0_ic_arb_fast; - wire l2_cpu0_ic_barrier_stall_q; - wire [43:18] l2_cpu0_ic_base; - wire [31:0] l2_cpu0_ic_data_arb_set; - wire [2:0] l2_cpu0_ic_elem_size_arb_set; - wire l2_cpu0_ic_excl_arb_set; - wire [2:0] l2_cpu0_ic_id_arb_set; - wire l2_cpu0_ic_ns_arb_set; - wire l2_cpu0_ic_vld_skid; - wire l2_cpu0_ic_write_arb_set; - wire [127:0] l2_cpu0_idata_r2; - wire l2_cpu0_idlb_ecc_err_r3; - wire l2_cpu0_idle_block_reqs_q; - wire l2_cpu0_idle_wakeup_q; - wire l2_cpu0_iext_err_r2; - wire l2_cpu0_iext_err_type_r2; - wire l2_cpu0_if_ccb_clken_c3; - wire l2_cpu0_if_ccb_req_c3; - wire l2_cpu0_if_ccb_resp; - wire [4:0] l2_cpu0_if_ccb_resp_id; - wire l2_cpu0_if_sync_done_q; - wire l2_cpu0_if_sync_req; - wire l2_cpu0_ifq_haz_pending; - wire l2_cpu0_isngl_ecc_err_r3; - wire l2_cpu0_ivalid_r1; - wire [1:0] l2_cpu0_l2_cache_size; - wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; - wire l2_cpu0_lrq_haz_pending; - wire l2_cpu0_ls_ccb_clken_c3; - wire l2_cpu0_ls_ccb_data_wr; - wire l2_cpu0_ls_ccb_req_c3; - wire l2_cpu0_ls_ccb_resp; - wire [4:0] l2_cpu0_ls_ccb_resp_id; - wire l2_cpu0_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; - wire l2_cpu0_ls_rd_haz_vld_arb_q; - wire l2_cpu0_ls_sync_req; - wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu0_ls_wr_data_w2a; - wire l2_cpu0_ls_wr_dirty_w2a; - wire l2_cpu0_ls_wr_err_w2a; - wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; - wire l2_cpu0_ls_wr_haz_vld_arb_q; - wire l2_cpu0_ls_wr_last_w2a; - wire l2_cpu0_ls_wr_req_w2a; - wire [2:0] l2_cpu0_ls_wr_type_w2a; - wire [12:0] l2_cpu0_mbist1_addr_b1; - wire l2_cpu0_mbist1_all_b1; - wire [3:0] l2_cpu0_mbist1_array_b1; - wire [7:0] l2_cpu0_mbist1_be_b1; - wire l2_cpu0_mbist1_en_b1; - wire l2_cpu0_mbist1_rd_en_b1; - wire l2_cpu0_mbist1_wr_en_b1; - wire l2_cpu0_no_intctrl; - wire l2_cpu0_pf_rd_vld_skid_popped; - wire l2_cpu0_pf_throttle_q; - wire [33:0] l2_cpu0_pmu_events; - wire [2:0] l2_cpu0_rbufid; - wire l2_cpu0_rd_aarch64_arb_set; - wire [44:0] l2_cpu0_rd_addr_arb_set; - wire l2_cpu0_rd_arb; - wire l2_cpu0_rd_arb_fast; - wire [15:8] l2_cpu0_rd_asid_arb_set; - wire l2_cpu0_rd_bypass_arb_set; - wire [2:0] l2_cpu0_rd_bypass_bufid_e5; - wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; - wire l2_cpu0_rd_bypass_req_can_e5; - wire l2_cpu0_rd_bypass_way_e5; - wire [2:0] l2_cpu0_rd_cache_attr_arb_set; - wire [2:0] l2_cpu0_rd_elem_size_arb_set; - wire l2_cpu0_rd_excl_arb_set; - wire [4:0] l2_cpu0_rd_id_arb_set; - wire [2:0] l2_cpu0_rd_lrq_id_arb_set; - wire [7:0] l2_cpu0_rd_page_attr_arb_set; - wire l2_cpu0_rd_prfm_arb_set; - wire l2_cpu0_rd_priv_arb_set; - wire l2_cpu0_rd_replayed_arb_set; - wire [1:0] l2_cpu0_rd_shared_arb_set; - wire [6:0] l2_cpu0_rd_type_arb_set; - wire l2_cpu0_rd_va48_arb_set; - wire l2_cpu0_rd_vld_skid; - wire l2_cpu0_rd_way_arb_set; - wire l2_cpu0_rexfail; - wire [1:0] l2_cpu0_rstate; - wire l2_cpu0_rvalid; - wire [2:0] l2_cpu0_spec_bufid; - wire l2_cpu0_spec_valid; - wire [63:0] l2_cpu0_spr_rd_data; - wire l2_cpu0_tbw_dbl_ecc_err; - wire [63:0] l2_cpu0_tbw_desc_data; - wire l2_cpu0_tbw_desc_vld; - wire l2_cpu0_tbw_ext_err; - wire l2_cpu0_tbw_ext_err_type; - wire l2_cpu0_tlb_ccb_clken_c3; - wire l2_cpu0_tlb_ccb_req_c3; - wire l2_cpu0_tlb_sync_complete; - wire l2_cpu0_tlb_sync_done_q; - wire l2_cpu0_tlb_sync_req; - wire l2_cpu0_trq_haz_pending; - wire l2_cpu0_tw_ccb_resp; - wire [4:0] l2_cpu0_tw_ccb_resp_id; - wire l2_cpu0_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu0_wr_addr_arb_set; - wire l2_cpu0_wr_arb; - wire l2_cpu0_wr_arb_fast; - wire [2:0] l2_cpu0_wr_cache_attr_arb_set; - wire [11:0] l2_cpu0_wr_cl_id_arb_set; - wire l2_cpu0_wr_clean_evict_arb_set; - wire [143:0] l2_cpu0_wr_data; - wire l2_cpu0_wr_data_stall; - wire l2_cpu0_wr_data_vld_x1_q; - wire l2_cpu0_wr_dirty_arb_set; - wire [2:0] l2_cpu0_wr_elem_size_arb_set; - wire l2_cpu0_wr_err_arb_set; - wire l2_cpu0_wr_evict_x1_q; - wire l2_cpu0_wr_ex_fail; - wire l2_cpu0_wr_ex_resp; - wire [3:0] l2_cpu0_wr_id_arb_set; - wire l2_cpu0_wr_last_arb_set; - wire [7:0] l2_cpu0_wr_page_attr_arb_set; - wire [3:0] l2_cpu0_wr_partial_dw_arb_set; - wire l2_cpu0_wr_priv_arb_set; - wire [1:0] l2_cpu0_wr_shared_arb_set; - wire [2:0] l2_cpu0_wr_type_arb_set; - wire l2_cpu0_wr_vld_skid; - wire l2_cpu0_wr_way_arb_set; - wire l2_cpu0_wrq_almost_full; - wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; - wire l2_cpu0_wrq_haz_pending; - wire l2_cpu1_arb_thrshld_timeout_en; - wire l2_cpu1_barrier_done; - wire l2_cpu1_blk_non_evict_wr; - wire l2_cpu1_ccb_dbg_req_c3; - wire [48:0] l2_cpu1_ccb_req_addr_c3; - wire [4:0] l2_cpu1_ccb_req_id_c3; - wire [23:0] l2_cpu1_ccb_req_info_c3; - wire [8:0] l2_cpu1_ccb_req_type_c3; - wire l2_cpu1_cfg_ecc_en; - wire [2:0] l2_cpu1_dbufid_r1; - wire [129:0] l2_cpu1_ddata_r2; - wire l2_cpu1_ddlb_ecc_err_r3; - wire l2_cpu1_dext_err_r2; - wire l2_cpu1_dext_err_type_r2; - wire l2_cpu1_disable_clean_evict_opt; - wire l2_cpu1_dlast_r1; - wire l2_cpu1_dsngl_ecc_err_r3; - wire [3:0] l2_cpu1_dsq_clr_id_q; - wire l2_cpu1_dsq_clr_vld_q; - wire [3:0] l2_cpu1_dsq_rd_buf_id; - wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu1_dsq_rd_data_q; - wire l2_cpu1_dsq_rd_en; - wire l2_cpu1_dsq_rd_en_x2; - wire l2_cpu1_dt_pmu_evt_en; - wire l2_cpu1_dvalid_r1; - wire l2_cpu1_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; - wire l2_cpu1_flsh_if_rd_l4_dly; - wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; - wire l2_cpu1_flsh_ls_rd_l2_dly; - wire l2_cpu1_flsh_ls_rd_l4_dly; - wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; - wire l2_cpu1_flsh_ls_wr_l2_dly; - wire l2_cpu1_flsh_ls_wr_l4_dly; - wire l2_cpu1_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu1_ibufid_r1; - wire [15:0] l2_cpu1_ic_addr_arb_set; - wire l2_cpu1_ic_arb_fast; - wire l2_cpu1_ic_barrier_stall_q; - wire [43:18] l2_cpu1_ic_base; - wire [31:0] l2_cpu1_ic_data_arb_set; - wire [2:0] l2_cpu1_ic_elem_size_arb_set; - wire l2_cpu1_ic_excl_arb_set; - wire [2:0] l2_cpu1_ic_id_arb_set; - wire l2_cpu1_ic_ns_arb_set; - wire l2_cpu1_ic_vld_skid; - wire l2_cpu1_ic_write_arb_set; - wire [127:0] l2_cpu1_idata_r2; - wire l2_cpu1_idlb_ecc_err_r3; - wire l2_cpu1_idle_block_reqs_q; - wire l2_cpu1_idle_wakeup_q; - wire l2_cpu1_iext_err_r2; - wire l2_cpu1_iext_err_type_r2; - wire l2_cpu1_if_ccb_clken_c3; - wire l2_cpu1_if_ccb_req_c3; - wire l2_cpu1_if_ccb_resp; - wire [4:0] l2_cpu1_if_ccb_resp_id; - wire l2_cpu1_if_sync_done_q; - wire l2_cpu1_if_sync_req; - wire l2_cpu1_ifq_haz_pending; - wire l2_cpu1_isngl_ecc_err_r3; - wire l2_cpu1_ivalid_r1; - wire [1:0] l2_cpu1_l2_cache_size; - wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; - wire l2_cpu1_lrq_haz_pending; - wire l2_cpu1_ls_ccb_clken_c3; - wire l2_cpu1_ls_ccb_data_wr; - wire l2_cpu1_ls_ccb_req_c3; - wire l2_cpu1_ls_ccb_resp; - wire [4:0] l2_cpu1_ls_ccb_resp_id; - wire l2_cpu1_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; - wire l2_cpu1_ls_rd_haz_vld_arb_q; - wire l2_cpu1_ls_sync_req; - wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu1_ls_wr_data_w2a; - wire l2_cpu1_ls_wr_dirty_w2a; - wire l2_cpu1_ls_wr_err_w2a; - wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; - wire l2_cpu1_ls_wr_haz_vld_arb_q; - wire l2_cpu1_ls_wr_last_w2a; - wire l2_cpu1_ls_wr_req_w2a; - wire [2:0] l2_cpu1_ls_wr_type_w2a; - wire [12:0] l2_cpu1_mbist1_addr_b1; - wire l2_cpu1_mbist1_all_b1; - wire [3:0] l2_cpu1_mbist1_array_b1; - wire [7:0] l2_cpu1_mbist1_be_b1; - wire l2_cpu1_mbist1_en_b1; - wire l2_cpu1_mbist1_rd_en_b1; - wire l2_cpu1_mbist1_wr_en_b1; - wire l2_cpu1_no_intctrl; - wire l2_cpu1_pf_rd_vld_skid_popped; - wire l2_cpu1_pf_throttle_q; - wire [33:0] l2_cpu1_pmu_events; - wire [2:0] l2_cpu1_rbufid; - wire l2_cpu1_rd_aarch64_arb_set; - wire [44:0] l2_cpu1_rd_addr_arb_set; - wire l2_cpu1_rd_arb; - wire l2_cpu1_rd_arb_fast; - wire [15:8] l2_cpu1_rd_asid_arb_set; - wire l2_cpu1_rd_bypass_arb_set; - wire [2:0] l2_cpu1_rd_bypass_bufid_e5; - wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; - wire l2_cpu1_rd_bypass_req_can_e5; - wire l2_cpu1_rd_bypass_way_e5; - wire [2:0] l2_cpu1_rd_cache_attr_arb_set; - wire [2:0] l2_cpu1_rd_elem_size_arb_set; - wire l2_cpu1_rd_excl_arb_set; - wire [4:0] l2_cpu1_rd_id_arb_set; - wire [2:0] l2_cpu1_rd_lrq_id_arb_set; - wire [7:0] l2_cpu1_rd_page_attr_arb_set; - wire l2_cpu1_rd_prfm_arb_set; - wire l2_cpu1_rd_priv_arb_set; - wire l2_cpu1_rd_replayed_arb_set; - wire [1:0] l2_cpu1_rd_shared_arb_set; - wire [6:0] l2_cpu1_rd_type_arb_set; - wire l2_cpu1_rd_va48_arb_set; - wire l2_cpu1_rd_vld_skid; - wire l2_cpu1_rd_way_arb_set; - wire l2_cpu1_rexfail; - wire [1:0] l2_cpu1_rstate; - wire l2_cpu1_rvalid; - wire [2:0] l2_cpu1_spec_bufid; - wire l2_cpu1_spec_valid; - wire [63:0] l2_cpu1_spr_rd_data; - wire l2_cpu1_tbw_dbl_ecc_err; - wire [63:0] l2_cpu1_tbw_desc_data; - wire l2_cpu1_tbw_desc_vld; - wire l2_cpu1_tbw_ext_err; - wire l2_cpu1_tbw_ext_err_type; - wire l2_cpu1_tlb_ccb_clken_c3; - wire l2_cpu1_tlb_ccb_req_c3; - wire l2_cpu1_tlb_sync_complete; - wire l2_cpu1_tlb_sync_done_q; - wire l2_cpu1_tlb_sync_req; - wire l2_cpu1_trq_haz_pending; - wire l2_cpu1_tw_ccb_resp; - wire [4:0] l2_cpu1_tw_ccb_resp_id; - wire l2_cpu1_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu1_wr_addr_arb_set; - wire l2_cpu1_wr_arb; - wire l2_cpu1_wr_arb_fast; - wire [2:0] l2_cpu1_wr_cache_attr_arb_set; - wire [11:0] l2_cpu1_wr_cl_id_arb_set; - wire l2_cpu1_wr_clean_evict_arb_set; - wire [143:0] l2_cpu1_wr_data; - wire l2_cpu1_wr_data_stall; - wire l2_cpu1_wr_data_vld_x1_q; - wire l2_cpu1_wr_dirty_arb_set; - wire [2:0] l2_cpu1_wr_elem_size_arb_set; - wire l2_cpu1_wr_err_arb_set; - wire l2_cpu1_wr_evict_x1_q; - wire l2_cpu1_wr_ex_fail; - wire l2_cpu1_wr_ex_resp; - wire [3:0] l2_cpu1_wr_id_arb_set; - wire l2_cpu1_wr_last_arb_set; - wire [7:0] l2_cpu1_wr_page_attr_arb_set; - wire [3:0] l2_cpu1_wr_partial_dw_arb_set; - wire l2_cpu1_wr_priv_arb_set; - wire [1:0] l2_cpu1_wr_shared_arb_set; - wire [2:0] l2_cpu1_wr_type_arb_set; - wire l2_cpu1_wr_vld_skid; - wire l2_cpu1_wr_way_arb_set; - wire l2_cpu1_wrq_almost_full; - wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; - wire l2_cpu1_wrq_haz_pending; - wire l2_cpu2_arb_thrshld_timeout_en; - wire l2_cpu2_barrier_done; - wire l2_cpu2_blk_non_evict_wr; - wire l2_cpu2_ccb_dbg_req_c3; - wire [48:0] l2_cpu2_ccb_req_addr_c3; - wire [4:0] l2_cpu2_ccb_req_id_c3; - wire [23:0] l2_cpu2_ccb_req_info_c3; - wire [8:0] l2_cpu2_ccb_req_type_c3; - wire l2_cpu2_cfg_ecc_en; - wire [2:0] l2_cpu2_dbufid_r1; - wire [129:0] l2_cpu2_ddata_r2; - wire l2_cpu2_ddlb_ecc_err_r3; - wire l2_cpu2_dext_err_r2; - wire l2_cpu2_dext_err_type_r2; - wire l2_cpu2_disable_clean_evict_opt; - wire l2_cpu2_dlast_r1; - wire l2_cpu2_dsngl_ecc_err_r3; - wire [3:0] l2_cpu2_dsq_clr_id_q; - wire l2_cpu2_dsq_clr_vld_q; - wire [3:0] l2_cpu2_dsq_rd_buf_id; - wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu2_dsq_rd_data_q; - wire l2_cpu2_dsq_rd_en; - wire l2_cpu2_dsq_rd_en_x2; - wire l2_cpu2_dt_pmu_evt_en; - wire l2_cpu2_dvalid_r1; - wire l2_cpu2_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; - wire l2_cpu2_flsh_if_rd_l4_dly; - wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; - wire l2_cpu2_flsh_ls_rd_l2_dly; - wire l2_cpu2_flsh_ls_rd_l4_dly; - wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; - wire l2_cpu2_flsh_ls_wr_l2_dly; - wire l2_cpu2_flsh_ls_wr_l4_dly; - wire l2_cpu2_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu2_ibufid_r1; - wire [15:0] l2_cpu2_ic_addr_arb_set; - wire l2_cpu2_ic_arb_fast; - wire l2_cpu2_ic_barrier_stall_q; - wire [43:18] l2_cpu2_ic_base; - wire [31:0] l2_cpu2_ic_data_arb_set; - wire [2:0] l2_cpu2_ic_elem_size_arb_set; - wire l2_cpu2_ic_excl_arb_set; - wire [2:0] l2_cpu2_ic_id_arb_set; - wire l2_cpu2_ic_ns_arb_set; - wire l2_cpu2_ic_vld_skid; - wire l2_cpu2_ic_write_arb_set; - wire [127:0] l2_cpu2_idata_r2; - wire l2_cpu2_idlb_ecc_err_r3; - wire l2_cpu2_idle_block_reqs_q; - wire l2_cpu2_idle_wakeup_q; - wire l2_cpu2_iext_err_r2; - wire l2_cpu2_iext_err_type_r2; - wire l2_cpu2_if_ccb_clken_c3; - wire l2_cpu2_if_ccb_req_c3; - wire l2_cpu2_if_ccb_resp; - wire [4:0] l2_cpu2_if_ccb_resp_id; - wire l2_cpu2_if_sync_done_q; - wire l2_cpu2_if_sync_req; - wire l2_cpu2_ifq_haz_pending; - wire l2_cpu2_isngl_ecc_err_r3; - wire l2_cpu2_ivalid_r1; - wire [1:0] l2_cpu2_l2_cache_size; - wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; - wire l2_cpu2_lrq_haz_pending; - wire l2_cpu2_ls_ccb_clken_c3; - wire l2_cpu2_ls_ccb_data_wr; - wire l2_cpu2_ls_ccb_req_c3; - wire l2_cpu2_ls_ccb_resp; - wire [4:0] l2_cpu2_ls_ccb_resp_id; - wire l2_cpu2_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; - wire l2_cpu2_ls_rd_haz_vld_arb_q; - wire l2_cpu2_ls_sync_req; - wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu2_ls_wr_data_w2a; - wire l2_cpu2_ls_wr_dirty_w2a; - wire l2_cpu2_ls_wr_err_w2a; - wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; - wire l2_cpu2_ls_wr_haz_vld_arb_q; - wire l2_cpu2_ls_wr_last_w2a; - wire l2_cpu2_ls_wr_req_w2a; - wire [2:0] l2_cpu2_ls_wr_type_w2a; - wire [12:0] l2_cpu2_mbist1_addr_b1; - wire l2_cpu2_mbist1_all_b1; - wire [3:0] l2_cpu2_mbist1_array_b1; - wire [7:0] l2_cpu2_mbist1_be_b1; - wire l2_cpu2_mbist1_en_b1; - wire l2_cpu2_mbist1_rd_en_b1; - wire l2_cpu2_mbist1_wr_en_b1; - wire l2_cpu2_no_intctrl; - wire l2_cpu2_pf_rd_vld_skid_popped; - wire l2_cpu2_pf_throttle_q; - wire [33:0] l2_cpu2_pmu_events; - wire [2:0] l2_cpu2_rbufid; - wire l2_cpu2_rd_aarch64_arb_set; - wire [44:0] l2_cpu2_rd_addr_arb_set; - wire l2_cpu2_rd_arb; - wire l2_cpu2_rd_arb_fast; - wire [15:8] l2_cpu2_rd_asid_arb_set; - wire l2_cpu2_rd_bypass_arb_set; - wire [2:0] l2_cpu2_rd_bypass_bufid_e5; - wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; - wire l2_cpu2_rd_bypass_req_can_e5; - wire l2_cpu2_rd_bypass_way_e5; - wire [2:0] l2_cpu2_rd_cache_attr_arb_set; - wire [2:0] l2_cpu2_rd_elem_size_arb_set; - wire l2_cpu2_rd_excl_arb_set; - wire [4:0] l2_cpu2_rd_id_arb_set; - wire [2:0] l2_cpu2_rd_lrq_id_arb_set; - wire [7:0] l2_cpu2_rd_page_attr_arb_set; - wire l2_cpu2_rd_prfm_arb_set; - wire l2_cpu2_rd_priv_arb_set; - wire l2_cpu2_rd_replayed_arb_set; - wire [1:0] l2_cpu2_rd_shared_arb_set; - wire [6:0] l2_cpu2_rd_type_arb_set; - wire l2_cpu2_rd_va48_arb_set; - wire l2_cpu2_rd_vld_skid; - wire l2_cpu2_rd_way_arb_set; - wire l2_cpu2_rexfail; - wire [1:0] l2_cpu2_rstate; - wire l2_cpu2_rvalid; - wire [2:0] l2_cpu2_spec_bufid; - wire l2_cpu2_spec_valid; - wire [63:0] l2_cpu2_spr_rd_data; - wire l2_cpu2_tbw_dbl_ecc_err; - wire [63:0] l2_cpu2_tbw_desc_data; - wire l2_cpu2_tbw_desc_vld; - wire l2_cpu2_tbw_ext_err; - wire l2_cpu2_tbw_ext_err_type; - wire l2_cpu2_tlb_ccb_clken_c3; - wire l2_cpu2_tlb_ccb_req_c3; - wire l2_cpu2_tlb_sync_complete; - wire l2_cpu2_tlb_sync_done_q; - wire l2_cpu2_tlb_sync_req; - wire l2_cpu2_trq_haz_pending; - wire l2_cpu2_tw_ccb_resp; - wire [4:0] l2_cpu2_tw_ccb_resp_id; - wire l2_cpu2_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu2_wr_addr_arb_set; - wire l2_cpu2_wr_arb; - wire l2_cpu2_wr_arb_fast; - wire [2:0] l2_cpu2_wr_cache_attr_arb_set; - wire [11:0] l2_cpu2_wr_cl_id_arb_set; - wire l2_cpu2_wr_clean_evict_arb_set; - wire [143:0] l2_cpu2_wr_data; - wire l2_cpu2_wr_data_stall; - wire l2_cpu2_wr_data_vld_x1_q; - wire l2_cpu2_wr_dirty_arb_set; - wire [2:0] l2_cpu2_wr_elem_size_arb_set; - wire l2_cpu2_wr_err_arb_set; - wire l2_cpu2_wr_evict_x1_q; - wire l2_cpu2_wr_ex_fail; - wire l2_cpu2_wr_ex_resp; - wire [3:0] l2_cpu2_wr_id_arb_set; - wire l2_cpu2_wr_last_arb_set; - wire [7:0] l2_cpu2_wr_page_attr_arb_set; - wire [3:0] l2_cpu2_wr_partial_dw_arb_set; - wire l2_cpu2_wr_priv_arb_set; - wire [1:0] l2_cpu2_wr_shared_arb_set; - wire [2:0] l2_cpu2_wr_type_arb_set; - wire l2_cpu2_wr_vld_skid; - wire l2_cpu2_wr_way_arb_set; - wire l2_cpu2_wrq_almost_full; - wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; - wire l2_cpu2_wrq_haz_pending; - wire l2_cpu3_arb_thrshld_timeout_en; - wire l2_cpu3_barrier_done; - wire l2_cpu3_blk_non_evict_wr; - wire l2_cpu3_ccb_dbg_req_c3; - wire [48:0] l2_cpu3_ccb_req_addr_c3; - wire [4:0] l2_cpu3_ccb_req_id_c3; - wire [23:0] l2_cpu3_ccb_req_info_c3; - wire [8:0] l2_cpu3_ccb_req_type_c3; - wire l2_cpu3_cfg_ecc_en; - wire [2:0] l2_cpu3_dbufid_r1; - wire [129:0] l2_cpu3_ddata_r2; - wire l2_cpu3_ddlb_ecc_err_r3; - wire l2_cpu3_dext_err_r2; - wire l2_cpu3_dext_err_type_r2; - wire l2_cpu3_disable_clean_evict_opt; - wire l2_cpu3_dlast_r1; - wire l2_cpu3_dsngl_ecc_err_r3; - wire [3:0] l2_cpu3_dsq_clr_id_q; - wire l2_cpu3_dsq_clr_vld_q; - wire [3:0] l2_cpu3_dsq_rd_buf_id; - wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; - wire [129:0] l2_cpu3_dsq_rd_data_q; - wire l2_cpu3_dsq_rd_en; - wire l2_cpu3_dsq_rd_en_x2; - wire l2_cpu3_dt_pmu_evt_en; - wire l2_cpu3_dvalid_r1; - wire l2_cpu3_early_rd_reqe4_e5_q; - wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; - wire l2_cpu3_flsh_if_rd_l4_dly; - wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; - wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; - wire l2_cpu3_flsh_ls_rd_l2_dly; - wire l2_cpu3_flsh_ls_rd_l4_dly; - wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_flsh_ls_wr_evict_l4_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; - wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; - wire l2_cpu3_flsh_ls_wr_l2_dly; - wire l2_cpu3_flsh_ls_wr_l4_dly; - wire l2_cpu3_flsh_tw_rd_l4_dly; - wire [1:0] l2_cpu3_ibufid_r1; - wire [15:0] l2_cpu3_ic_addr_arb_set; - wire l2_cpu3_ic_arb_fast; - wire l2_cpu3_ic_barrier_stall_q; - wire [43:18] l2_cpu3_ic_base; - wire [31:0] l2_cpu3_ic_data_arb_set; - wire [2:0] l2_cpu3_ic_elem_size_arb_set; - wire l2_cpu3_ic_excl_arb_set; - wire [2:0] l2_cpu3_ic_id_arb_set; - wire l2_cpu3_ic_ns_arb_set; - wire l2_cpu3_ic_vld_skid; - wire l2_cpu3_ic_write_arb_set; - wire [127:0] l2_cpu3_idata_r2; - wire l2_cpu3_idlb_ecc_err_r3; - wire l2_cpu3_idle_block_reqs_q; - wire l2_cpu3_idle_wakeup_q; - wire l2_cpu3_iext_err_r2; - wire l2_cpu3_iext_err_type_r2; - wire l2_cpu3_if_ccb_clken_c3; - wire l2_cpu3_if_ccb_req_c3; - wire l2_cpu3_if_ccb_resp; - wire [4:0] l2_cpu3_if_ccb_resp_id; - wire l2_cpu3_if_sync_done_q; - wire l2_cpu3_if_sync_req; - wire l2_cpu3_ifq_haz_pending; - wire l2_cpu3_isngl_ecc_err_r3; - wire l2_cpu3_ivalid_r1; - wire [1:0] l2_cpu3_l2_cache_size; - wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; - wire l2_cpu3_lrq_haz_pending; - wire l2_cpu3_ls_ccb_clken_c3; - wire l2_cpu3_ls_ccb_data_wr; - wire l2_cpu3_ls_ccb_req_c3; - wire l2_cpu3_ls_ccb_resp; - wire [4:0] l2_cpu3_ls_ccb_resp_id; - wire l2_cpu3_ls_peq_coll_l4_dly; - wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; - wire l2_cpu3_ls_rd_haz_vld_arb_q; - wire l2_cpu3_ls_sync_req; - wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; - wire [127:0] l2_cpu3_ls_wr_data_w2a; - wire l2_cpu3_ls_wr_dirty_w2a; - wire l2_cpu3_ls_wr_err_w2a; - wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; - wire l2_cpu3_ls_wr_haz_vld_arb_q; - wire l2_cpu3_ls_wr_last_w2a; - wire l2_cpu3_ls_wr_req_w2a; - wire [2:0] l2_cpu3_ls_wr_type_w2a; - wire [12:0] l2_cpu3_mbist1_addr_b1; - wire l2_cpu3_mbist1_all_b1; - wire [3:0] l2_cpu3_mbist1_array_b1; - wire [7:0] l2_cpu3_mbist1_be_b1; - wire l2_cpu3_mbist1_en_b1; - wire l2_cpu3_mbist1_rd_en_b1; - wire l2_cpu3_mbist1_wr_en_b1; - wire l2_cpu3_no_intctrl; - wire l2_cpu3_pf_rd_vld_skid_popped; - wire l2_cpu3_pf_throttle_q; - wire [33:0] l2_cpu3_pmu_events; - wire [2:0] l2_cpu3_rbufid; - wire l2_cpu3_rd_aarch64_arb_set; - wire [44:0] l2_cpu3_rd_addr_arb_set; - wire l2_cpu3_rd_arb; - wire l2_cpu3_rd_arb_fast; - wire [15:8] l2_cpu3_rd_asid_arb_set; - wire l2_cpu3_rd_bypass_arb_set; - wire [2:0] l2_cpu3_rd_bypass_bufid_e5; - wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; - wire l2_cpu3_rd_bypass_req_can_e5; - wire l2_cpu3_rd_bypass_way_e5; - wire [2:0] l2_cpu3_rd_cache_attr_arb_set; - wire [2:0] l2_cpu3_rd_elem_size_arb_set; - wire l2_cpu3_rd_excl_arb_set; - wire [4:0] l2_cpu3_rd_id_arb_set; - wire [2:0] l2_cpu3_rd_lrq_id_arb_set; - wire [7:0] l2_cpu3_rd_page_attr_arb_set; - wire l2_cpu3_rd_prfm_arb_set; - wire l2_cpu3_rd_priv_arb_set; - wire l2_cpu3_rd_replayed_arb_set; - wire [1:0] l2_cpu3_rd_shared_arb_set; - wire [6:0] l2_cpu3_rd_type_arb_set; - wire l2_cpu3_rd_va48_arb_set; - wire l2_cpu3_rd_vld_skid; - wire l2_cpu3_rd_way_arb_set; - wire l2_cpu3_rexfail; - wire [1:0] l2_cpu3_rstate; - wire l2_cpu3_rvalid; - wire [2:0] l2_cpu3_spec_bufid; - wire l2_cpu3_spec_valid; - wire [63:0] l2_cpu3_spr_rd_data; - wire l2_cpu3_tbw_dbl_ecc_err; - wire [63:0] l2_cpu3_tbw_desc_data; - wire l2_cpu3_tbw_desc_vld; - wire l2_cpu3_tbw_ext_err; - wire l2_cpu3_tbw_ext_err_type; - wire l2_cpu3_tlb_ccb_clken_c3; - wire l2_cpu3_tlb_ccb_req_c3; - wire l2_cpu3_tlb_sync_complete; - wire l2_cpu3_tlb_sync_done_q; - wire l2_cpu3_tlb_sync_req; - wire l2_cpu3_trq_haz_pending; - wire l2_cpu3_tw_ccb_resp; - wire [4:0] l2_cpu3_tw_ccb_resp_id; - wire l2_cpu3_wr_1st_replayed_arb_set; - wire [44:0] l2_cpu3_wr_addr_arb_set; - wire l2_cpu3_wr_arb; - wire l2_cpu3_wr_arb_fast; - wire [2:0] l2_cpu3_wr_cache_attr_arb_set; - wire [11:0] l2_cpu3_wr_cl_id_arb_set; - wire l2_cpu3_wr_clean_evict_arb_set; - wire [143:0] l2_cpu3_wr_data; - wire l2_cpu3_wr_data_stall; - wire l2_cpu3_wr_data_vld_x1_q; - wire l2_cpu3_wr_dirty_arb_set; - wire [2:0] l2_cpu3_wr_elem_size_arb_set; - wire l2_cpu3_wr_err_arb_set; - wire l2_cpu3_wr_evict_x1_q; - wire l2_cpu3_wr_ex_fail; - wire l2_cpu3_wr_ex_resp; - wire [3:0] l2_cpu3_wr_id_arb_set; - wire l2_cpu3_wr_last_arb_set; - wire [7:0] l2_cpu3_wr_page_attr_arb_set; - wire [3:0] l2_cpu3_wr_partial_dw_arb_set; - wire l2_cpu3_wr_priv_arb_set; - wire [1:0] l2_cpu3_wr_shared_arb_set; - wire [2:0] l2_cpu3_wr_type_arb_set; - wire l2_cpu3_wr_vld_skid; - wire l2_cpu3_wr_way_arb_set; - wire l2_cpu3_wrq_almost_full; - wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; - wire l2_cpu3_wrq_haz_pending; - wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; - wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; - wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; - wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; - wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; - wire ls_cpu0_clrexmon; - wire ls_cpu0_imp_abort_containable; - wire ls_cpu0_imp_abort_dec; - wire ls_cpu0_imp_abort_ecc; - wire ls_cpu0_imp_abort_slv; - wire ls_cpu0_raw_eae_nonsec; - wire ls_cpu0_raw_eae_secure; - wire ls_cpu1_clrexmon; - wire ls_cpu1_imp_abort_containable; - wire ls_cpu1_imp_abort_dec; - wire ls_cpu1_imp_abort_ecc; - wire ls_cpu1_imp_abort_slv; - wire ls_cpu1_raw_eae_nonsec; - wire ls_cpu1_raw_eae_secure; - wire ls_cpu2_clrexmon; - wire ls_cpu2_imp_abort_containable; - wire ls_cpu2_imp_abort_dec; - wire ls_cpu2_imp_abort_ecc; - wire ls_cpu2_imp_abort_slv; - wire ls_cpu2_raw_eae_nonsec; - wire ls_cpu2_raw_eae_secure; - wire ls_cpu3_clrexmon; - wire ls_cpu3_imp_abort_containable; - wire ls_cpu3_imp_abort_dec; - wire ls_cpu3_imp_abort_ecc; - wire ls_cpu3_imp_abort_slv; - wire ls_cpu3_raw_eae_nonsec; - wire ls_cpu3_raw_eae_secure; - wire ncommirq_cpu0_i; - wire ncommirq_cpu1_i; - wire ncommirq_cpu2_i; - wire ncommirq_cpu3_i; - wire ncorereset_cpu0_o; - wire ncorereset_cpu1_o; - wire ncorereset_cpu2_o; - wire ncorereset_cpu3_o; - wire ncpuporeset_cpu0_o; - wire ncpuporeset_cpu1_o; - wire ncpuporeset_cpu2_o; - wire ncpuporeset_cpu3_o; - wire niden_cpu0_o; - wire niden_cpu1_o; - wire niden_cpu2_o; - wire niden_cpu3_o; - wire nmbistreset_cpu0_o; - wire nmbistreset_cpu1_o; - wire nmbistreset_cpu2_o; - wire nmbistreset_cpu3_o; - wire npmuirq_cpu0_i; - wire npmuirq_cpu1_i; - wire npmuirq_cpu2_i; - wire npmuirq_cpu3_i; - wire pm_export_cpu0_i; - wire pm_export_cpu1_i; - wire pm_export_cpu2_i; - wire pm_export_cpu3_i; - wire [24:0] pmuevent_cpu0_i; - wire [24:0] pmuevent_cpu1_i; - wire [24:0] pmuevent_cpu2_i; - wire [24:0] pmuevent_cpu3_i; - wire [43:2] rvbaraddr_cpu0_o; - wire [43:2] rvbaraddr_cpu1_o; - wire [43:2] rvbaraddr_cpu2_o; - wire [43:2] rvbaraddr_cpu3_o; - wire spiden_cpu0_o; - wire spiden_cpu1_o; - wire spiden_cpu2_o; - wire spiden_cpu3_o; - wire spniden_cpu0_o; - wire spniden_cpu1_o; - wire spniden_cpu2_o; - wire spniden_cpu3_o; - wire syncreqm_cpu0_o; - wire syncreqm_cpu1_o; - wire syncreqm_cpu2_o; - wire syncreqm_cpu3_o; - wire [1:0] tm_cpu0_cnthctl_kernel; - wire [3:0] tm_cpu0_cntkctl_usr; - wire [1:0] tm_cpu1_cnthctl_kernel; - wire [3:0] tm_cpu1_cntkctl_usr; - wire [1:0] tm_cpu2_cnthctl_kernel; - wire [3:0] tm_cpu2_cntkctl_usr; - wire [1:0] tm_cpu3_cnthctl_kernel; - wire [3:0] tm_cpu3_cntkctl_usr; - wire [63:0] tsvalueb_cpu0_o; - wire [63:0] tsvalueb_cpu1_o; - wire [63:0] tsvalueb_cpu2_o; - wire [63:0] tsvalueb_cpu3_o; - wire vinithi_cpu0_o; - wire vinithi_cpu1_o; - wire vinithi_cpu2_o; - wire vinithi_cpu3_o; - - maia_cpu ucpu0( // outputs - .afreadym_cpu (afreadym_cpu0_i), - .atbytesm_cpu (atbytesm_cpu0_i[1:0]), - .atdatam_cpu (atdatam_cpu0_i[31:0]), - .atidm_cpu (atidm_cpu0_i[6:0]), - .atvalidm_cpu (atvalidm_cpu0_i), - .commrx_cpu (commrx_cpu0_i), - .commtx_cpu (commtx_cpu0_i), - .dbgack_cpu (dbgack_cpu0_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), - .dbgrstreq_cpu (dbgrstreq_cpu0_i), - .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_flush (ds_cpu0_flush), - .ds_flush_type (ds_cpu0_flush_type[5:0]), - .ds_hcr_va (ds_cpu0_hcr_va), - .ds_hcr_vf (ds_cpu0_hcr_vf), - .ds_hcr_vi (ds_cpu0_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu0_reset_req), - .ds_sev_req (ds_cpu0_sev_req), - .ds_sevl_req (ds_cpu0_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_wfe_req (ds_cpu0_wfe_req), - .ds_wfi_req (ds_cpu0_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu0_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu0_clrexmon), - .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu0_i), - .npmuirq_cpu (npmuirq_cpu0_i), - .pm_export_cpu (pm_export_cpu0_i), - .pmuevent_cpu (pmuevent_cpu0_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu0_o), - .afvalidm_cpu (afvalidm_cpu0_o), - .atclken_cpu (atclken_cpu0_o), - .atreadym_cpu (atreadym_cpu0_o), - .cfgend_cpu (cfgend_cpu0_o), - .cfgte_cpu (cfgte_cpu0_o), - .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_event_reg (ck_cpu0_event_reg), - .ck_gclkt (ck_gclkt[0]), - .ck_wfe_ack (ck_cpu0_wfe_ack), - .ck_wfi_ack (ck_cpu0_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu0_o), - .cpuid (cpuid_cpu0_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu0_o), - .dbgen_cpu (dbgen_cpu0_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), - .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), - .dftramhold_cpu (dftramhold_cpu0_o), - .dftrstdisable_cpu (dftrstdisable_cpu0_o), - .dftse_cpu (dftse_cpu0_o), - .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu0_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), - .ic_el_change_complete (ic_el_change_complete[0]), - .ic_hcr_change_complete (ic_hcr_change_complete[0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), - .ic_ich_el2_tc (ic_ich_el2_tc[0]), - .ic_nfiq (ic_nfiq[0]), - .ic_nirq (ic_nirq[0]), - .ic_nsei (ic_nsei[0]), - .ic_nvfiq (ic_nvfiq[0]), - .ic_nvirq (ic_nvirq[0]), - .ic_nvsei (ic_nvsei[0]), - .ic_p_valid (ic_p_valid[0]), - .ic_sample_spr (ic_sample_spr[0]), - .ic_scr_change_complete (ic_scr_change_complete[0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), - .ic_sra_el1s_en (ic_sra_el1s_en[0]), - .ic_sra_el2_en (ic_sra_el2_en[0]), - .ic_sra_el3_en (ic_sra_el3_en[0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu0_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu0_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu0_rexfail), - .l2_cpu_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu0_rvalid), - .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu0_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu0_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu0_o), - .ncpuporeset_cpu (ncpuporeset_cpu0_o), - .niden_cpu (niden_cpu0_o), - .nmbistreset_cpu (nmbistreset_cpu0_o), - .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), - .spiden_cpu (spiden_cpu0_o), - .spniden_cpu (spniden_cpu0_o), - .syncreqm_cpu (syncreqm_cpu0_o), - .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), - .vinithi_cpu (vinithi_cpu0_o) - ); // ucpu0 - - maia_cpu ucpu1( // outputs - .afreadym_cpu (afreadym_cpu1_i), - .atbytesm_cpu (atbytesm_cpu1_i[1:0]), - .atdatam_cpu (atdatam_cpu1_i[31:0]), - .atidm_cpu (atidm_cpu1_i[6:0]), - .atvalidm_cpu (atvalidm_cpu1_i), - .commrx_cpu (commrx_cpu1_i), - .commtx_cpu (commtx_cpu1_i), - .dbgack_cpu (dbgack_cpu1_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), - .dbgrstreq_cpu (dbgrstreq_cpu1_i), - .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_flush (ds_cpu1_flush), - .ds_flush_type (ds_cpu1_flush_type[5:0]), - .ds_hcr_va (ds_cpu1_hcr_va), - .ds_hcr_vf (ds_cpu1_hcr_vf), - .ds_hcr_vi (ds_cpu1_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu1_reset_req), - .ds_sev_req (ds_cpu1_sev_req), - .ds_sevl_req (ds_cpu1_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_wfe_req (ds_cpu1_wfe_req), - .ds_wfi_req (ds_cpu1_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu1_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu1_clrexmon), - .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu1_i), - .npmuirq_cpu (npmuirq_cpu1_i), - .pm_export_cpu (pm_export_cpu1_i), - .pmuevent_cpu (pmuevent_cpu1_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu1_o), - .afvalidm_cpu (afvalidm_cpu1_o), - .atclken_cpu (atclken_cpu1_o), - .atreadym_cpu (atreadym_cpu1_o), - .cfgend_cpu (cfgend_cpu1_o), - .cfgte_cpu (cfgte_cpu1_o), - .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_event_reg (ck_cpu1_event_reg), - .ck_gclkt (ck_gclkt[1]), - .ck_wfe_ack (ck_cpu1_wfe_ack), - .ck_wfi_ack (ck_cpu1_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu1_o), - .cpuid (cpuid_cpu1_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu1_o), - .dbgen_cpu (dbgen_cpu1_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), - .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), - .dftramhold_cpu (dftramhold_cpu1_o), - .dftrstdisable_cpu (dftrstdisable_cpu1_o), - .dftse_cpu (dftse_cpu1_o), - .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu1_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), - .ic_el_change_complete (ic_el_change_complete[1]), - .ic_hcr_change_complete (ic_hcr_change_complete[1]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), - .ic_ich_el2_tc (ic_ich_el2_tc[1]), - .ic_nfiq (ic_nfiq[1]), - .ic_nirq (ic_nirq[1]), - .ic_nsei (ic_nsei[1]), - .ic_nvfiq (ic_nvfiq[1]), - .ic_nvirq (ic_nvirq[1]), - .ic_nvsei (ic_nvsei[1]), - .ic_p_valid (ic_p_valid[1]), - .ic_sample_spr (ic_sample_spr[1]), - .ic_scr_change_complete (ic_scr_change_complete[1]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), - .ic_sra_el1s_en (ic_sra_el1s_en[1]), - .ic_sra_el2_en (ic_sra_el2_en[1]), - .ic_sra_el3_en (ic_sra_el3_en[1]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu1_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu1_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu1_rexfail), - .l2_cpu_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu1_rvalid), - .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu1_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu1_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu1_o), - .ncpuporeset_cpu (ncpuporeset_cpu1_o), - .niden_cpu (niden_cpu1_o), - .nmbistreset_cpu (nmbistreset_cpu1_o), - .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), - .spiden_cpu (spiden_cpu1_o), - .spniden_cpu (spniden_cpu1_o), - .syncreqm_cpu (syncreqm_cpu1_o), - .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), - .vinithi_cpu (vinithi_cpu1_o) - ); // ucpu1 - - maia_cpu ucpu2( // outputs - .afreadym_cpu (afreadym_cpu2_i), - .atbytesm_cpu (atbytesm_cpu2_i[1:0]), - .atdatam_cpu (atdatam_cpu2_i[31:0]), - .atidm_cpu (atidm_cpu2_i[6:0]), - .atvalidm_cpu (atvalidm_cpu2_i), - .commrx_cpu (commrx_cpu2_i), - .commtx_cpu (commtx_cpu2_i), - .dbgack_cpu (dbgack_cpu2_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), - .dbgrstreq_cpu (dbgrstreq_cpu2_i), - .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_flush (ds_cpu2_flush), - .ds_flush_type (ds_cpu2_flush_type[5:0]), - .ds_hcr_va (ds_cpu2_hcr_va), - .ds_hcr_vf (ds_cpu2_hcr_vf), - .ds_hcr_vi (ds_cpu2_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu2_reset_req), - .ds_sev_req (ds_cpu2_sev_req), - .ds_sevl_req (ds_cpu2_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_wfe_req (ds_cpu2_wfe_req), - .ds_wfi_req (ds_cpu2_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu2_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu2_clrexmon), - .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu2_i), - .npmuirq_cpu (npmuirq_cpu2_i), - .pm_export_cpu (pm_export_cpu2_i), - .pmuevent_cpu (pmuevent_cpu2_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu2_o), - .afvalidm_cpu (afvalidm_cpu2_o), - .atclken_cpu (atclken_cpu2_o), - .atreadym_cpu (atreadym_cpu2_o), - .cfgend_cpu (cfgend_cpu2_o), - .cfgte_cpu (cfgte_cpu2_o), - .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_event_reg (ck_cpu2_event_reg), - .ck_gclkt (ck_gclkt[2]), - .ck_wfe_ack (ck_cpu2_wfe_ack), - .ck_wfi_ack (ck_cpu2_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu2_o), - .cpuid (cpuid_cpu2_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu2_o), - .dbgen_cpu (dbgen_cpu2_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), - .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), - .dftramhold_cpu (dftramhold_cpu2_o), - .dftrstdisable_cpu (dftrstdisable_cpu2_o), - .dftse_cpu (dftse_cpu2_o), - .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu2_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), - .ic_el_change_complete (ic_el_change_complete[2]), - .ic_hcr_change_complete (ic_hcr_change_complete[2]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), - .ic_ich_el2_tc (ic_ich_el2_tc[2]), - .ic_nfiq (ic_nfiq[2]), - .ic_nirq (ic_nirq[2]), - .ic_nsei (ic_nsei[2]), - .ic_nvfiq (ic_nvfiq[2]), - .ic_nvirq (ic_nvirq[2]), - .ic_nvsei (ic_nvsei[2]), - .ic_p_valid (ic_p_valid[2]), - .ic_sample_spr (ic_sample_spr[2]), - .ic_scr_change_complete (ic_scr_change_complete[2]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), - .ic_sra_el1s_en (ic_sra_el1s_en[2]), - .ic_sra_el2_en (ic_sra_el2_en[2]), - .ic_sra_el3_en (ic_sra_el3_en[2]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu2_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu2_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu2_rexfail), - .l2_cpu_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu2_rvalid), - .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu2_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu2_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu2_o), - .ncpuporeset_cpu (ncpuporeset_cpu2_o), - .niden_cpu (niden_cpu2_o), - .nmbistreset_cpu (nmbistreset_cpu2_o), - .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), - .spiden_cpu (spiden_cpu2_o), - .spniden_cpu (spniden_cpu2_o), - .syncreqm_cpu (syncreqm_cpu2_o), - .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), - .vinithi_cpu (vinithi_cpu2_o) - ); // ucpu2 - - maia_cpu ucpu3( // outputs - .afreadym_cpu (afreadym_cpu3_i), - .atbytesm_cpu (atbytesm_cpu3_i[1:0]), - .atdatam_cpu (atdatam_cpu3_i[31:0]), - .atidm_cpu (atidm_cpu3_i[6:0]), - .atvalidm_cpu (atvalidm_cpu3_i), - .commrx_cpu (commrx_cpu3_i), - .commtx_cpu (commtx_cpu3_i), - .dbgack_cpu (dbgack_cpu3_i), - .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu (dbgrstreq_cpu3_i), - .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_flush (ds_cpu3_flush), - .ds_flush_type (ds_cpu3_flush_type[5:0]), - .ds_hcr_va (ds_cpu3_hcr_va), - .ds_hcr_vf (ds_cpu3_hcr_vf), - .ds_hcr_vi (ds_cpu3_hcr_vi), - .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_reset_req (ds_cpu3_reset_req), - .ds_sev_req (ds_cpu3_sev_req), - .ds_sevl_req (ds_cpu3_sevl_req), - .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_wfe_req (ds_cpu3_wfe_req), - .ds_wfi_req (ds_cpu3_wfi_req), - .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu (etclken_cpu3_i), - .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_clrexmon (ls_cpu3_clrexmon), - .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), - .ncommirq_cpu (ncommirq_cpu3_i), - .npmuirq_cpu (npmuirq_cpu3_i), - .pm_export_cpu (pm_export_cpu3_i), - .pmuevent_cpu (pmuevent_cpu3_i[24:0]), - - // inputs - .aa64naa32_cpu (aa64naa32_cpu3_o), - .afvalidm_cpu (afvalidm_cpu3_o), - .atclken_cpu (atclken_cpu3_o), - .atreadym_cpu (atreadym_cpu3_o), - .cfgend_cpu (cfgend_cpu3_o), - .cfgte_cpu (cfgte_cpu3_o), - .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_event_reg (ck_cpu3_event_reg), - .ck_gclkt (ck_gclkt[3]), - .ck_wfe_ack (ck_cpu3_wfe_ack), - .ck_wfi_ack (ck_cpu3_wfi_ack), - .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu (cp15sdisable_cpu3_o), - .cpuid (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu (cryptodisable_cpu3_o), - .dbgen_cpu (dbgen_cpu3_o), - .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), - .dftramhold_cpu (dftramhold_cpu3_o), - .dftrstdisable_cpu (dftrstdisable_cpu3_o), - .dftse_cpu (dftse_cpu3_o), - .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), - .ic_el_change_complete (ic_el_change_complete[3]), - .ic_hcr_change_complete (ic_hcr_change_complete[3]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), - .ic_ich_el2_tc (ic_ich_el2_tc[3]), - .ic_nfiq (ic_nfiq[3]), - .ic_nirq (ic_nirq[3]), - .ic_nsei (ic_nsei[3]), - .ic_nvfiq (ic_nvfiq[3]), - .ic_nvirq (ic_nvirq[3]), - .ic_nvsei (ic_nvsei[3]), - .ic_p_valid (ic_p_valid[3]), - .ic_sample_spr (ic_sample_spr[3]), - .ic_scr_change_complete (ic_scr_change_complete[3]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), - .ic_sra_el1s_en (ic_sra_el1s_en[3]), - .ic_sra_el2_en (ic_sra_el2_en[3]), - .ic_sra_el3_en (ic_sra_el3_en[3]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), - .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu_barrier_done (l2_cpu3_barrier_done), - .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu_rd_arb (l2_cpu3_rd_arb), - .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu_rexfail (l2_cpu3_rexfail), - .l2_cpu_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu_rvalid (l2_cpu3_rvalid), - .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu_spec_valid (l2_cpu3_spec_valid), - .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu_wr_arb (l2_cpu3_wr_arb), - .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .ncorereset_cpu (ncorereset_cpu3_o), - .ncpuporeset_cpu (ncpuporeset_cpu3_o), - .niden_cpu (niden_cpu3_o), - .nmbistreset_cpu (nmbistreset_cpu3_o), - .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu (spiden_cpu3_o), - .spniden_cpu (spniden_cpu3_o), - .syncreqm_cpu (syncreqm_cpu3_o), - .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu (vinithi_cpu3_o) - ); // ucpu3 - - maia_noncpu_s unoncpu( // outputs - .AFREADYM0 (AFREADYM0), - .AFREADYM1 (AFREADYM1), - .AFREADYM2 (AFREADYM2), - .AFREADYM3 (AFREADYM3), - .ARREADYS (ARREADYS), - .ATBYTESM0 (ATBYTESM0[1:0]), - .ATBYTESM1 (ATBYTESM1[1:0]), - .ATBYTESM2 (ATBYTESM2[1:0]), - .ATBYTESM3 (ATBYTESM3[1:0]), - .ATDATAM0 (ATDATAM0[31:0]), - .ATDATAM1 (ATDATAM1[31:0]), - .ATDATAM2 (ATDATAM2[31:0]), - .ATDATAM3 (ATDATAM3[31:0]), - .ATIDM0 (ATIDM0[6:0]), - .ATIDM1 (ATIDM1[6:0]), - .ATIDM2 (ATIDM2[6:0]), - .ATIDM3 (ATIDM3[6:0]), - .ATVALIDM0 (ATVALIDM0), - .ATVALIDM1 (ATVALIDM1), - .ATVALIDM2 (ATVALIDM2), - .ATVALIDM3 (ATVALIDM3), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CLREXMONACK (CLREXMONACK), - .COMMRX (COMMRX[`MAIA_CN:0]), - .COMMTX (COMMTX[`MAIA_CN:0]), - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGACK (DBGACK[`MAIA_CN:0]), - .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), - .EVENTO (EVENTO), - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .PMUEVENT0 (PMUEVENT0[24:0]), - .PMUEVENT1 (PMUEVENT1[24:0]), - .PMUEVENT2 (PMUEVENT2[24:0]), - .PMUEVENT3 (PMUEVENT3[24:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .SMPEN (SMPEN[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .WREADYS (WREADYS), - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq[`MAIA_CN:0]), - .ic_nirq (ic_nirq[`MAIA_CN:0]), - .ic_nsei (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei[`MAIA_CN:0]), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), - .ACLKENS (ACLKENS), - .AFVALIDM0 (AFVALIDM0), - .AFVALIDM1 (AFVALIDM1), - .AFVALIDM2 (AFVALIDM2), - .AFVALIDM3 (AFVALIDM3), - .AINACTS (AINACTS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .ATCLKEN (ATCLKEN), - .ATREADYM0 (ATREADYM0), - .ATREADYM1 (ATREADYM1), - .ATREADYM2 (ATREADYM2), - .ATREADYM3 (ATREADYM3), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .CFGEND (CFGEND[`MAIA_CN:0]), - .CFGTE (CFGTE[`MAIA_CN:0]), - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLK (CLK), - .CLKEN (CLKEN), - .CLREXMONREQ (CLREXMONREQ), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DBGROMADDR (DBGROMADDR[43:12]), - .DBGROMADDRV (DBGROMADDRV), - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .EVENTI (EVENTI), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NIDEN (NIDEN[`MAIA_CN:0]), - .NODEID (NODEID[6:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PERIPHBASE (PERIPHBASE[43:18]), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .RREADYS (RREADYS), - .RVBARADDR0 (RVBARADDR0[43:2]), - .RVBARADDR1 (RVBARADDR1[43:2]), - .RVBARADDR2 (RVBARADDR2[43:2]), - .RVBARADDR3 (RVBARADDR3[43:2]), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SINACT (SINACT), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .SYNCREQM0 (SYNCREQM0), - .SYNCREQM1 (SYNCREQM1), - .SYNCREQM2 (SYNCREQM2), - .SYNCREQM3 (SYNCREQM3), - .SYSBARDISABLE (SYSBARDISABLE), - .TSVALUEB (TSVALUEB[63:0]), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .VINITHI (VINITHI[`MAIA_CN:0]), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .nPRESETDBG (nPRESETDBG), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) - ); // unoncpu -endmodule // MAIA_s - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v deleted file mode 100644 index 97ad653c68..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v +++ /dev/null @@ -1,7931 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_aa64naa32; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_aa64naa32; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire STANDBYWFIL2; - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic ul2_logic( // outputs - .ACREADYM (ACREADYM), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .WACKM (WACKM), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACADDRM (ACADDRM[43:0]), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CRREADYM (CRREADYM), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .PERIPHBASE (PERIPHBASE[43:18]), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .STANDBYWFIL2 (STANDBYWFIL2), - .SYSBARDISABLE (SYSBARDISABLE), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (ACINACTM), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (1'b1), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_val.v" -`endif - -endmodule // maia_noncpu - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v deleted file mode 100644 index 84a47bdbe3..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v +++ /dev/null @@ -1,7934 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu_feq20.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu_feq20 ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, - ACLKENS, - AINACTS, -// BEGIN NO-ACP pins - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_aa64naa32; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_aa64naa32; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire STANDBYWFIL2; - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic_feq20 ul2_logic( // outputs - .ACREADYM (ACREADYM), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .WACKM (WACKM), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACADDRM (ACADDRM[43:0]), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CRREADYM (CRREADYM), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .PERIPHBASE (PERIPHBASE[43:18]), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .STANDBYWFIL2 (STANDBYWFIL2), - .SYSBARDISABLE (SYSBARDISABLE), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (ACINACTM), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (1'b1), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_feq20_val.v" -`endif - -endmodule // maia_noncpu_feq20 - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v deleted file mode 100644 index d5b5463db9..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v +++ /dev/null @@ -1,7951 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu_feq20_s.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu_feq20_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, - ACLKENS, - AINACTS, -// BEGIN NO-ACP pins - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_aa64naa32; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_aa64naa32; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_sky_link_stopped; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic_feq20_s ul2_logic( // outputs - .ARREADYS (ARREADYS), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WREADYS (WREADYS), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_sky_link_stopped (l2_sky_link_stopped), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACLKENS (ACLKENS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NODEID (NODEID[6:0]), - .PERIPHBASE (PERIPHBASE[43:18]), - .RREADYS (RREADYS), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SYSBARDISABLE (SYSBARDISABLE), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (SINACT), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (l2_sky_link_stopped), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_feq20_s_val.v" -`endif - -endmodule // maia_noncpu_feq20_s - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v deleted file mode 100644 index cf90e92932..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v +++ /dev/null @@ -1,7934 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu_feq28.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu_feq28 ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - ACLKENM, - ACINACTM, - AWREADYM, - AWVALIDM, - AWIDM, - AWADDRM, - AWLENM, - AWSIZEM, - AWBURSTM, - AWBARM, - AWDOMAINM, - AWLOCKM, - AWCACHEM, - AWPROTM, - AWSNOOPM, - AWUNIQUEM, - WRMEMATTR, - WREADYM, - WVALIDM, - WDATAM, - WSTRBM, - WIDM, - WLASTM, - BREADYM, - BVALIDM, - BIDM, - BRESPM, - ARREADYM, - ARVALIDM, - ARIDM, - ARADDRM, - ARLENM, - ARSIZEM, - ARBURSTM, - ARBARM, - ARDOMAINM, - ARLOCKM, - ARCACHEM, - ARPROTM, - ARSNOOPM, - RDMEMATTR, - RREADYM, - RVALIDM, - RIDM, - RDATAM, - RRESPM, - RLASTM, - ACREADYM, - ACVALIDM, - ACADDRM, - ACPROTM, - ACSNOOPM, - CRREADYM, - CRVALIDM, - CRRESPM, - CDREADYM, - CDVALIDM, - CDDATAM, - CDLASTM, - RACKM, - WACKM, - ACLKENS, - AINACTS, -// BEGIN NO-ACP pins - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// AMBA4 ACE Master (AXI with Coherency extensions) -//----------------------------------------------------------------------------- - input ACLKENM; // AXI Master clock enable - input ACINACTM; // ACE Snoop interface no longer active or accepting requests - -// Write Address channel signals - input AWREADYM; // Write Address ready (slave ready to accept write address) - output AWVALIDM; // Write Address valid - output [6:0] AWIDM; // Write Address ID - output [43:0] AWADDRM; // Write Address - output [7:0] AWLENM; // Write Burst Length - output [2:0] AWSIZEM; // Write Burst Size - output [1:0] AWBURSTM; // Write Burst type - output [1:0] AWBARM; // Barrier - output [1:0] AWDOMAINM; // Domain - output AWLOCKM; // Write Lock type - output [3:0] AWCACHEM; // Write Cache type - output [2:0] AWPROTM; // Write Protection type - output [2:0] AWSNOOPM; // Write Snoop Request type - output AWUNIQUEM; // Write Unique state - output [7:0] WRMEMATTR; // Write raw memory attributes - -// Write Data channel signals - input WREADYM; // Write Data ready (slave ready to accept data) - output WVALIDM; // Write Data valid - output [127:0] WDATAM; // Write Data - output [15:0] WSTRBM; // Write byte-lane strobes - output [6:0] WIDM; // Write id - output WLASTM; // Write Data last transfer indicator - -// Write Response channel signals - output BREADYM; // Write Response ready (master ready to accept response) - input BVALIDM; // Write Response Valid - input [6:0] BIDM; // Write Response ID - input [1:0] BRESPM; // Write Response - -// Read Address channel signals - input ARREADYM; // Read Address ready (slave ready to accept read address) - output ARVALIDM; // Read Address valid - output [6:0] ARIDM; // Read Address ID - output [43:0] ARADDRM; // Read Address - output [7:0] ARLENM; // Read Burst Length - output [2:0] ARSIZEM; // Read Burst Size - output [1:0] ARBURSTM; // Read Burst type - output [1:0] ARBARM; // Barrier - output [1:0] ARDOMAINM; // Domain - output ARLOCKM; // Read Lock type - output [3:0] ARCACHEM; // Read Cache type - output [2:0] ARPROTM; // Read Protection type - output [3:0] ARSNOOPM; // Read Snoop Request type - output [7:0] RDMEMATTR; // Read raw memory attributes - -// Read Data channel signals - output RREADYM; // Read Data ready (master ready to accept data) - input RVALIDM; // Read Data valid - input [6:0] RIDM; // Read Data ID - input [127:0] RDATAM; // Read Data - input [3:0] RRESPM; // Read Data response - input RLASTM; // Read Data last transfer indicator - -// Coherency Address channel signals - output ACREADYM; // master ready to accept snoop address - input ACVALIDM; // Snoop Address valid - input [43:0] ACADDRM; // Snoop Address - input [2:0] ACPROTM; // Snoop Protection type - input [3:0] ACSNOOPM; // Snoop Request type - -// Coherency Response channel signals - input CRREADYM; // slave ready to accept snoop response - output CRVALIDM; // Snoop Response valid - output [4:0] CRRESPM; // Snoop Response - -// Coherency Data handshake channel signals - input CDREADYM; // slave ready to accept snoop data - output CDVALIDM; // Snoop Data valid - output [127:0] CDDATAM; // Snoop Data - output CDLASTM; // Snoop Data last transfer indicator - -// Read/Write Acknowledge signals - output RACKM; // Read Acknowledge - output WACKM; // Write Acknowledge - -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_aa64naa32; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_aa64naa32; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire STANDBYWFIL2; - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic_feq28 ul2_logic( // outputs - .ACREADYM (ACREADYM), - .ARADDRM (ARADDRM[43:0]), - .ARBARM (ARBARM[1:0]), - .ARBURSTM (ARBURSTM[1:0]), - .ARCACHEM (ARCACHEM[3:0]), - .ARDOMAINM (ARDOMAINM[1:0]), - .ARIDM (ARIDM[6:0]), - .ARLENM (ARLENM[7:0]), - .ARLOCKM (ARLOCKM), - .ARPROTM (ARPROTM[2:0]), - .ARREADYS (ARREADYS), - .ARSIZEM (ARSIZEM[2:0]), - .ARSNOOPM (ARSNOOPM[3:0]), - .ARVALIDM (ARVALIDM), - .AWADDRM (AWADDRM[43:0]), - .AWBARM (AWBARM[1:0]), - .AWBURSTM (AWBURSTM[1:0]), - .AWCACHEM (AWCACHEM[3:0]), - .AWDOMAINM (AWDOMAINM[1:0]), - .AWIDM (AWIDM[6:0]), - .AWLENM (AWLENM[7:0]), - .AWLOCKM (AWLOCKM), - .AWPROTM (AWPROTM[2:0]), - .AWREADYS (AWREADYS), - .AWSIZEM (AWSIZEM[2:0]), - .AWSNOOPM (AWSNOOPM[2:0]), - .AWUNIQUEM (AWUNIQUEM), - .AWVALIDM (AWVALIDM), - .BIDS (BIDS[4:0]), - .BREADYM (BREADYM), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .CDDATAM (CDDATAM[127:0]), - .CDLASTM (CDLASTM), - .CDVALIDM (CDVALIDM), - .CRRESPM (CRRESPM[4:0]), - .CRVALIDM (CRVALIDM), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RACKM (RACKM), - .RDATAS (RDATAS[127:0]), - .RDMEMATTR (RDMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RREADYM (RREADYM), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .WACKM (WACKM), - .WDATAM (WDATAM[127:0]), - .WIDM (WIDM[6:0]), - .WLASTM (WLASTM), - .WREADYS (WREADYS), - .WRMEMATTR (WRMEMATTR[7:0]), - .WSTRBM (WSTRBM[15:0]), - .WVALIDM (WVALIDM), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACADDRM (ACADDRM[43:0]), - .ACLKENM (ACLKENM), - .ACLKENS (ACLKENS), - .ACPROTM (ACPROTM[2:0]), - .ACSNOOPM (ACSNOOPM[3:0]), - .ACVALIDM (ACVALIDM), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARREADYM (ARREADYM), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWREADYM (AWREADYM), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BIDM (BIDM[6:0]), - .BREADYS (BREADYS), - .BRESPM (BRESPM[1:0]), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .BVALIDM (BVALIDM), - .CDREADYM (CDREADYM), - .CRREADYM (CRREADYM), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .PERIPHBASE (PERIPHBASE[43:18]), - .RDATAM (RDATAM[127:0]), - .RIDM (RIDM[6:0]), - .RLASTM (RLASTM), - .RREADYS (RREADYS), - .RRESPM (RRESPM[3:0]), - .RVALIDM (RVALIDM), - .STANDBYWFIL2 (STANDBYWFIL2), - .SYSBARDISABLE (SYSBARDISABLE), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WREADYM (WREADYM), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b0), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (ACINACTM), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (1'b1), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_feq28_val.v" -`endif - -endmodule // maia_noncpu_feq28 - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v deleted file mode 100644 index 1517a5c1ba..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v +++ /dev/null @@ -1,7951 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu_feq28_s.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu_feq28_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, - ACLKENS, - AINACTS, -// BEGIN NO-ACP pins - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests - -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_aa64naa32; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_aa64naa32; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_sky_link_stopped; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic_feq28_s ul2_logic( // outputs - .ARREADYS (ARREADYS), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WREADYS (WREADYS), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_sky_link_stopped (l2_sky_link_stopped), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACLKENS (ACLKENS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NODEID (NODEID[6:0]), - .PERIPHBASE (PERIPHBASE[43:18]), - .RREADYS (RREADYS), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SYSBARDISABLE (SYSBARDISABLE), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (SINACT), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (l2_sky_link_stopped), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_feq28_s_val.v" -`endif - -endmodule // maia_noncpu_feq28_s - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v deleted file mode 100644 index 431c8f5de9..0000000000 --- a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v +++ /dev/null @@ -1,7952 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_noncpu.v $ -// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ -// Revision : $Revision: 73443 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// -// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. -// - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -`define MAIA_CN 3 - -module maia_noncpu_s ( - CLK, - CLKEN, - nCPUPORESET, - nCORERESET, - nL2RESET, - L2RSTDISABLE, - WARMRSTREQ, - CFGEND, - VINITHI, - CFGTE, - CP15SDISABLE, - CLUSTERIDAFF1, - CLUSTERIDAFF2, - AA64nAA32, - RVBARADDR0, -// BEGIN INCLUDE FOR CPU1 - RVBARADDR1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - RVBARADDR2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - RVBARADDR3, -// END INCLUDE FOR CPU3 - CRYPTODISABLE, - nFIQ, - nIRQ, - nSEI, - nREI, - nVFIQ, - nVIRQ, - nVSEI, -// BEGIN NO-GIC pins - nVCPUMNTIRQ, -// END NO-GIC pins - PERIPHBASE, -// BEGIN NO-GIC pins - GICCDISABLE, - ICDTVALID, - ICDTREADY, - ICDTDATA, - ICDTLAST, - ICDTDEST, - ICCTVALID, - ICCTREADY, - ICCTDATA, - ICCTLAST, - ICCTID, -// END NO-GIC pins - CNTVALUEB, - CNTCLKEN, - nCNTPNSIRQ, - nCNTPSIRQ, - nCNTVIRQ, - nCNTHPIRQ, - CLREXMONREQ, - CLREXMONACK, - EVENTI, - EVENTO, - STANDBYWFI, - STANDBYWFE, - STANDBYWFIL2, - SMPEN, - CPUQACTIVE, - CPUQREQn, - CPUQACCEPTn, - CPUQDENY, - L2QACTIVE, - L2QREQn, - L2QACCEPTn, - L2QDENY, - L2FLUSHREQ, - L2FLUSHDONE, - nINTERRIRQ, - nEXTERRIRQ, - SYSBARDISABLE, - BROADCASTINNER, - BROADCASTOUTER, - BROADCASTCACHEMAINT, - SCLKEN, - SINACT, - NODEID, - TXSACTIVE, - RXSACTIVE, - TXLINKACTIVEREQ, - TXLINKACTIVEACK, - RXLINKACTIVEREQ, - RXLINKACTIVEACK, - TXREQFLITPEND, - TXREQFLITV, - TXREQFLIT, - REQMEMATTR, - TXREQLCRDV, - TXRSPFLITPEND, - TXRSPFLITV, - TXRSPFLIT, - TXRSPLCRDV, - TXDATFLITPEND, - TXDATFLITV, - TXDATFLIT, - TXDATLCRDV, - RXSNPFLITPEND, - RXSNPFLITV, - RXSNPFLIT, - RXSNPLCRDV, - RXRSPFLITPEND, - RXRSPFLITV, - RXRSPFLIT, - RXRSPLCRDV, - RXDATFLITPEND, - RXDATFLITV, - RXDATFLIT, - RXDATLCRDV, - SAMMNBASE, - SAMADDRMAP0, - SAMADDRMAP1, - SAMADDRMAP2, - SAMADDRMAP3, - SAMADDRMAP4, - SAMADDRMAP5, - SAMADDRMAP6, - SAMADDRMAP7, - SAMADDRMAP8, - SAMADDRMAP9, - SAMADDRMAP10, - SAMADDRMAP11, - SAMADDRMAP12, - SAMADDRMAP13, - SAMADDRMAP14, - SAMADDRMAP15, - SAMADDRMAP16, - SAMADDRMAP17, - SAMADDRMAP18, - SAMADDRMAP19, - SAMMNNODEID, - SAMHNI0NODEID, - SAMHNI1NODEID, - SAMHNF0NODEID, - SAMHNF1NODEID, - SAMHNF2NODEID, - SAMHNF3NODEID, - SAMHNF4NODEID, - SAMHNF5NODEID, - SAMHNF6NODEID, - SAMHNF7NODEID, - SAMHNFMODE, -// BEGIN NO-ACP pins - ACLKENS, - AINACTS, - AWREADYS, - AWVALIDS, - AWIDS, - AWADDRS, - AWLENS, - AWCACHES, - AWUSERS, - AWPROTS, - WREADYS, - WVALIDS, - WDATAS, - WSTRBS, - WLASTS, - BREADYS, - BVALIDS, - BIDS, - BRESPS, - ARREADYS, - ARVALIDS, - ARIDS, - ARADDRS, - ARLENS, - ARCACHES, - ARUSERS, - ARPROTS, - RREADYS, - RVALIDS, - RIDS, - RDATAS, - RRESPS, - RLASTS, -// END NO-ACP pins - DBGROMADDR, - DBGROMADDRV, - DBGACK, - nCOMMIRQ, - COMMRX, - COMMTX, - DBGRSTREQ, - DBGNOPWRDWN, - DBGL1RSTDISABLE, - nPMUIRQ, - PMUEVENT0, -// BEGIN INCLUDE FOR CPU1 - PMUEVENT1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - PMUEVENT2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - PMUEVENT3, -// END INCLUDE FOR CPU3 - ATCLKEN, - TSVALUEB, - ATREADYM0, - AFVALIDM0, - ATDATAM0, - ATVALIDM0, - ATBYTESM0, - AFREADYM0, - ATIDM0, - SYNCREQM0, -// BEGIN INCLUDE FOR CPU1 - ATREADYM1, - AFVALIDM1, - ATDATAM1, - ATVALIDM1, - ATBYTESM1, - AFREADYM1, - ATIDM1, - SYNCREQM1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ATREADYM2, - AFVALIDM2, - ATDATAM2, - ATVALIDM2, - ATBYTESM2, - AFREADYM2, - ATIDM2, - SYNCREQM2, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ATREADYM3, - AFVALIDM3, - ATDATAM3, - ATVALIDM3, - ATBYTESM3, - AFREADYM3, - ATIDM3, - SYNCREQM3, -// END INCLUDE FOR CPU3 - PCLKDBG, - PCLKENDBG, - nPRESETDBG, - PSELDBG, - PADDRDBG, - PADDRDBG31, - PENABLEDBG, - PWRITEDBG, - PWDATADBG, - PRDATADBG, - PREADYDBG, - PSLVERRDBG, - EDBGRQ, - PMUSNAPSHOTREQ, - PMUSNAPSHOTACK, - DBGPWRDUP, - DBGPWRUPREQ, - CTICHIN, - CTICHOUTACK, - CTICHOUT, - CTICHINACK, - CISBYPASS, - CIHSBYPASS, - CTIIRQ, - CTIIRQACK, - DBGEN, - NIDEN, - SPIDEN, - SPNIDEN, - DFTSE, - DFTRSTDISABLE, - DFTCRCLKDISABLE, - DFTL2CLKDISABLE, - DFTRAMHOLD, - DFTCLKBYPASS, - DFTMCPHOLD, - nMBISTRESET, - MBISTREQ, - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - ncpuporeset_cpu0_o, - ncorereset_cpu0_o, - - cfgend_cpu0_o, - cfgte_cpu0_o, - cp15sdisable_cpu0_o, - vinithi_cpu0_o, - clusteridaff1_cpu0_o, - clusteridaff2_cpu0_o, - cpuid_cpu0_o, - aa64naa32_cpu0_o, - rvbaraddr_cpu0_o, - cryptodisable_cpu0_o, - giccdisable_cpu0_o, - - dbgromaddr_cpu0_o, - dbgromaddrv_cpu0_o, - dbgl1rstdisable_cpu0_o, - - dbgen_cpu0_o, - niden_cpu0_o, - spiden_cpu0_o, - spniden_cpu0_o, - - tsvalueb_cpu0_o, - - atclken_cpu0_o, - afvalidm_cpu0_o, - atreadym_cpu0_o, - syncreqm_cpu0_o, - - dftse_cpu0_o, - dftrstdisable_cpu0_o, - dftcrclkdisable_cpu0_o, - dftramhold_cpu0_o, - - nmbistreset_cpu0_o, - -// BEGIN INCLUDE FOR CPU1 - ncpuporeset_cpu1_o, - ncorereset_cpu1_o, - - cfgend_cpu1_o, - cfgte_cpu1_o, - cp15sdisable_cpu1_o, - vinithi_cpu1_o, - clusteridaff1_cpu1_o, - clusteridaff2_cpu1_o, - cpuid_cpu1_o, - aa64naa32_cpu1_o, - rvbaraddr_cpu1_o, - cryptodisable_cpu1_o, - giccdisable_cpu1_o, - - dbgromaddr_cpu1_o, - dbgromaddrv_cpu1_o, - dbgl1rstdisable_cpu1_o, - - dbgen_cpu1_o, - niden_cpu1_o, - spiden_cpu1_o, - spniden_cpu1_o, - - tsvalueb_cpu1_o, - - atclken_cpu1_o, - afvalidm_cpu1_o, - atreadym_cpu1_o, - syncreqm_cpu1_o, - - dftse_cpu1_o, - dftrstdisable_cpu1_o, - dftcrclkdisable_cpu1_o, - dftramhold_cpu1_o, - - nmbistreset_cpu1_o, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ncpuporeset_cpu2_o, - ncorereset_cpu2_o, - - cfgend_cpu2_o, - cfgte_cpu2_o, - cp15sdisable_cpu2_o, - vinithi_cpu2_o, - clusteridaff1_cpu2_o, - clusteridaff2_cpu2_o, - cpuid_cpu2_o, - aa64naa32_cpu2_o, - rvbaraddr_cpu2_o, - cryptodisable_cpu2_o, - giccdisable_cpu2_o, - - dbgromaddr_cpu2_o, - dbgromaddrv_cpu2_o, - dbgl1rstdisable_cpu2_o, - - dbgen_cpu2_o, - niden_cpu2_o, - spiden_cpu2_o, - spniden_cpu2_o, - - tsvalueb_cpu2_o, - - atclken_cpu2_o, - afvalidm_cpu2_o, - atreadym_cpu2_o, - syncreqm_cpu2_o, - - dftse_cpu2_o, - dftrstdisable_cpu2_o, - dftcrclkdisable_cpu2_o, - dftramhold_cpu2_o, - - nmbistreset_cpu2_o, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ncpuporeset_cpu3_o, - ncorereset_cpu3_o, - - cfgend_cpu3_o, - cfgte_cpu3_o, - cp15sdisable_cpu3_o, - vinithi_cpu3_o, - clusteridaff1_cpu3_o, - clusteridaff2_cpu3_o, - cpuid_cpu3_o, - aa64naa32_cpu3_o, - rvbaraddr_cpu3_o, - cryptodisable_cpu3_o, - giccdisable_cpu3_o, - - dbgromaddr_cpu3_o, - dbgromaddrv_cpu3_o, - dbgl1rstdisable_cpu3_o, - - dbgen_cpu3_o, - niden_cpu3_o, - spiden_cpu3_o, - spniden_cpu3_o, - - tsvalueb_cpu3_o, - - atclken_cpu3_o, - afvalidm_cpu3_o, - atreadym_cpu3_o, - syncreqm_cpu3_o, - - dftse_cpu3_o, - dftrstdisable_cpu3_o, - dftcrclkdisable_cpu3_o, - dftramhold_cpu3_o, - - nmbistreset_cpu3_o, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - ds_cpu0_sev_req, - ds_cpu0_sevl_req, - ds_cpu0_cpuectlr_smp, - - ncommirq_cpu0_i, - commrx_cpu0_i, - commtx_cpu0_i, - dbgack_cpu0_i, - dbgrstreq_cpu0_i, - dbgnopwrdwn_cpu0_i, - - npmuirq_cpu0_i, - pmuevent_cpu0_i, - pm_export_cpu0_i, - - etclken_cpu0_i, - afreadym_cpu0_i, - atbytesm_cpu0_i, - atdatam_cpu0_i, - atidm_cpu0_i, - atvalidm_cpu0_i, - -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_sev_req, - ds_cpu1_sevl_req, - ds_cpu1_cpuectlr_smp, - - ncommirq_cpu1_i, - commrx_cpu1_i, - commtx_cpu1_i, - dbgack_cpu1_i, - dbgrstreq_cpu1_i, - dbgnopwrdwn_cpu1_i, - - npmuirq_cpu1_i, - pmuevent_cpu1_i, - pm_export_cpu1_i, - - etclken_cpu1_i, - afreadym_cpu1_i, - atbytesm_cpu1_i, - atdatam_cpu1_i, - atidm_cpu1_i, - atvalidm_cpu1_i, -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_sev_req, - ds_cpu2_sevl_req, - ds_cpu2_cpuectlr_smp, - - ncommirq_cpu2_i, - commrx_cpu2_i, - commtx_cpu2_i, - dbgack_cpu2_i, - dbgrstreq_cpu2_i, - dbgnopwrdwn_cpu2_i, - - npmuirq_cpu2_i, - pmuevent_cpu2_i, - pm_export_cpu2_i, - - etclken_cpu2_i, - afreadym_cpu2_i, - atbytesm_cpu2_i, - atdatam_cpu2_i, - atidm_cpu2_i, - atvalidm_cpu2_i, -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_sev_req, - ds_cpu3_sevl_req, - ds_cpu3_cpuectlr_smp, - - ncommirq_cpu3_i, - commrx_cpu3_i, - commtx_cpu3_i, - dbgack_cpu3_i, - dbgrstreq_cpu3_i, - dbgnopwrdwn_cpu3_i, - - npmuirq_cpu3_i, - pmuevent_cpu3_i, - pm_export_cpu3_i, - - etclken_cpu3_i, - afreadym_cpu3_i, - atbytesm_cpu3_i, - atdatam_cpu3_i, - atidm_cpu3_i, - atvalidm_cpu3_i, -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - l2_cpu0_mbist1_addr_b1, - l2_cpu0_mbist1_array_b1, - l2_cpu0_mbist1_be_b1, - l2_cpu0_mbist1_en_b1, - l2_cpu0_mbist1_rd_en_b1, - l2_cpu0_mbist1_wr_en_b1, - l2_cpu0_mbist1_all_b1, -// BEGIN INCLUDE FOR CPU1 - l2_cpu1_mbist1_addr_b1, - l2_cpu1_mbist1_array_b1, - l2_cpu1_mbist1_be_b1, - l2_cpu1_mbist1_en_b1, - l2_cpu1_mbist1_rd_en_b1, - l2_cpu1_mbist1_wr_en_b1, - l2_cpu1_mbist1_all_b1, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - l2_cpu2_mbist1_addr_b1, - l2_cpu2_mbist1_array_b1, - l2_cpu2_mbist1_be_b1, - l2_cpu2_mbist1_en_b1, - l2_cpu2_mbist1_rd_en_b1, - l2_cpu2_mbist1_wr_en_b1, - l2_cpu2_mbist1_all_b1, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - l2_cpu3_mbist1_addr_b1, - l2_cpu3_mbist1_array_b1, - l2_cpu3_mbist1_be_b1, - l2_cpu3_mbist1_en_b1, - l2_cpu3_mbist1_rd_en_b1, - l2_cpu3_mbist1_wr_en_b1, - l2_cpu3_mbist1_all_b1, -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_cfg_ecc_en, - l2_cpu0_arb_thrshld_timeout_en, - l2_cpu0_disable_clean_evict_opt, - l2_cpu0_dext_err_r2, - l2_cpu0_dext_err_type_r2, - l2_cpu0_dsngl_ecc_err_r3, - l2_cpu0_ddbl_ecc_err_r3, - l2_cpu0_ddata_r2, - l2_cpu0_barrier_done, - l2_cpu0_spec_valid, - l2_cpu0_spec_bufid, - l2_cpu0_rvalid, - l2_cpu0_rstate, - l2_cpu0_rexfail, - l2_cpu0_rbufid, - l2_cpu0_dvalid_r1, - l2_cpu0_dlast_r1, - l2_cpu0_dbufid_r1, - l2_cpu0_iext_err_r2, - l2_cpu0_iext_err_type_r2, - l2_cpu0_isngl_ecc_err_r3, - l2_cpu0_idbl_ecc_err_r3, - l2_cpu0_idata_r2, - l2_cpu0_ivalid_r1, - l2_cpu0_ibufid_r1, - l2_cpu0_ls_sync_req, - l2_cpu0_ccb_req_addr_c3, - l2_cpu0_ccb_dbg_req_c3, - l2_cpu0_ls_ccb_clken_c3, - l2_cpu0_ls_ccb_req_c3, - l2_cpu0_ccb_req_id_c3, - l2_cpu0_ccb_req_type_c3, - l2_cpu0_ccb_req_info_c3, - l2_cpu0_if_ccb_clken_c3, - l2_cpu0_if_ccb_req_c3, - l2_cpu0_if_sync_req, - l2_cpu0_tlb_ccb_clken_c3, - l2_cpu0_tlb_ccb_req_c3, - l2_cpu0_tlb_sync_req, - l2_cpu0_tlb_sync_complete, - l2_cpu0_tbw_desc_vld, - l2_cpu0_tbw_ext_err, - l2_cpu0_tbw_ext_err_type, - l2_cpu0_tbw_dbl_ecc_err, - l2_cpu0_tbw_desc_data, - l2_cpu0_spr_rd_data, - l2_cpu0_l2_cache_size, - l2_cpu0_pf_throttle_q, - - l2_cpu0_wr_ex_resp, - l2_cpu0_wr_ex_fail, - - l2_cpu0_ic_base, - l2_cpu0_no_intctrl, - - - l2_cpu0_pmu_events, - - ds_cpu0_l2_spr_en, - ds_cpu0_l2_spr_rd, - ds_cpu0_l2_spr_wr, - ds_cpu0_l2_spr_addr, - ds_cpu0_l2_spr_dw, - ds_cpu0_l2_spr_wr_data, - - l2_cpu0_wr_data_vld_x1_q, - l2_cpu0_wr_evict_x1_q, - l2_cpu0_wr_data, - l2_cpu0_ls_rd_haz_vld_arb_q, - l2_cpu0_ls_wr_haz_vld_arb_q, - l2_cpu0_dt_pmu_evt_en, - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_cfg_ecc_en, - l2_cpu1_arb_thrshld_timeout_en, - l2_cpu1_disable_clean_evict_opt, - l2_cpu1_dext_err_r2, - l2_cpu1_dext_err_type_r2, - l2_cpu1_dsngl_ecc_err_r3, - l2_cpu1_ddbl_ecc_err_r3, - l2_cpu1_ddata_r2, - l2_cpu1_barrier_done, - l2_cpu1_spec_valid, - l2_cpu1_spec_bufid, - l2_cpu1_rvalid, - l2_cpu1_rstate, - l2_cpu1_rexfail, - l2_cpu1_rbufid, - l2_cpu1_dvalid_r1, - l2_cpu1_dlast_r1, - l2_cpu1_dbufid_r1, - l2_cpu1_iext_err_r2, - l2_cpu1_iext_err_type_r2, - l2_cpu1_isngl_ecc_err_r3, - l2_cpu1_idbl_ecc_err_r3, - l2_cpu1_idata_r2, - l2_cpu1_ivalid_r1, - l2_cpu1_ibufid_r1, - l2_cpu1_ls_sync_req, - l2_cpu1_ccb_req_addr_c3, - l2_cpu1_ccb_dbg_req_c3, - l2_cpu1_ls_ccb_clken_c3, - l2_cpu1_ls_ccb_req_c3, - l2_cpu1_ccb_req_id_c3, - l2_cpu1_ccb_req_type_c3, - l2_cpu1_ccb_req_info_c3, - l2_cpu1_if_ccb_clken_c3, - l2_cpu1_if_ccb_req_c3, - l2_cpu1_if_sync_req, - l2_cpu1_tlb_ccb_clken_c3, - l2_cpu1_tlb_ccb_req_c3, - l2_cpu1_tlb_sync_req, - l2_cpu1_tlb_sync_complete, - l2_cpu1_tbw_desc_vld, - l2_cpu1_tbw_ext_err, - l2_cpu1_tbw_ext_err_type, - l2_cpu1_tbw_dbl_ecc_err, - l2_cpu1_tbw_desc_data, - l2_cpu1_spr_rd_data, - l2_cpu1_l2_cache_size, - l2_cpu1_pf_throttle_q, - - l2_cpu1_wr_ex_resp, - l2_cpu1_wr_ex_fail, - - l2_cpu1_ic_base, - l2_cpu1_no_intctrl, - - l2_cpu1_pmu_events, - - ds_cpu1_l2_spr_en, - ds_cpu1_l2_spr_rd, - ds_cpu1_l2_spr_wr, - ds_cpu1_l2_spr_addr, - ds_cpu1_l2_spr_dw, - ds_cpu1_l2_spr_wr_data, - - l2_cpu1_wr_data_vld_x1_q, - l2_cpu1_wr_evict_x1_q, - l2_cpu1_wr_data, - l2_cpu1_ls_rd_haz_vld_arb_q, - l2_cpu1_ls_wr_haz_vld_arb_q, - l2_cpu1_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_cfg_ecc_en, - l2_cpu2_arb_thrshld_timeout_en, - l2_cpu2_disable_clean_evict_opt, - l2_cpu2_dext_err_r2, - l2_cpu2_dext_err_type_r2, - l2_cpu2_dsngl_ecc_err_r3, - l2_cpu2_ddbl_ecc_err_r3, - l2_cpu2_ddata_r2, - l2_cpu2_barrier_done, - l2_cpu2_spec_valid, - l2_cpu2_spec_bufid, - l2_cpu2_rvalid, - l2_cpu2_rstate, - l2_cpu2_rexfail, - l2_cpu2_rbufid, - l2_cpu2_dvalid_r1, - l2_cpu2_dlast_r1, - l2_cpu2_dbufid_r1, - l2_cpu2_iext_err_r2, - l2_cpu2_iext_err_type_r2, - l2_cpu2_isngl_ecc_err_r3, - l2_cpu2_idbl_ecc_err_r3, - l2_cpu2_idata_r2, - l2_cpu2_ivalid_r1, - l2_cpu2_ibufid_r1, - l2_cpu2_ls_sync_req, - l2_cpu2_ccb_req_addr_c3, - l2_cpu2_ccb_dbg_req_c3, - l2_cpu2_ls_ccb_clken_c3, - l2_cpu2_ls_ccb_req_c3, - l2_cpu2_ccb_req_id_c3, - l2_cpu2_ccb_req_type_c3, - l2_cpu2_ccb_req_info_c3, - l2_cpu2_if_ccb_clken_c3, - l2_cpu2_if_ccb_req_c3, - l2_cpu2_if_sync_req, - l2_cpu2_tlb_ccb_clken_c3, - l2_cpu2_tlb_ccb_req_c3, - l2_cpu2_tlb_sync_req, - l2_cpu2_tlb_sync_complete, - l2_cpu2_tbw_desc_vld, - l2_cpu2_tbw_ext_err, - l2_cpu2_tbw_ext_err_type, - l2_cpu2_tbw_dbl_ecc_err, - l2_cpu2_tbw_desc_data, - l2_cpu2_spr_rd_data, - l2_cpu2_l2_cache_size, - l2_cpu2_pf_throttle_q, - - l2_cpu2_wr_ex_resp, - l2_cpu2_wr_ex_fail, - - l2_cpu2_ic_base, - l2_cpu2_no_intctrl, - - l2_cpu2_pmu_events, - - ds_cpu2_l2_spr_en, - ds_cpu2_l2_spr_rd, - ds_cpu2_l2_spr_wr, - ds_cpu2_l2_spr_addr, - ds_cpu2_l2_spr_dw, - ds_cpu2_l2_spr_wr_data, - - l2_cpu2_wr_data_vld_x1_q, - l2_cpu2_wr_evict_x1_q, - l2_cpu2_wr_data, - l2_cpu2_ls_rd_haz_vld_arb_q, - l2_cpu2_ls_wr_haz_vld_arb_q, - l2_cpu2_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_cfg_ecc_en, - l2_cpu3_arb_thrshld_timeout_en, - l2_cpu3_disable_clean_evict_opt, - l2_cpu3_dext_err_r2, - l2_cpu3_dext_err_type_r2, - l2_cpu3_dsngl_ecc_err_r3, - l2_cpu3_ddbl_ecc_err_r3, - l2_cpu3_ddata_r2, - l2_cpu3_barrier_done, - l2_cpu3_spec_valid, - l2_cpu3_spec_bufid, - l2_cpu3_rvalid, - l2_cpu3_rstate, - l2_cpu3_rexfail, - l2_cpu3_rbufid, - l2_cpu3_dvalid_r1, - l2_cpu3_dlast_r1, - l2_cpu3_dbufid_r1, - l2_cpu3_iext_err_r2, - l2_cpu3_iext_err_type_r2, - l2_cpu3_isngl_ecc_err_r3, - l2_cpu3_idbl_ecc_err_r3, - l2_cpu3_idata_r2, - l2_cpu3_ivalid_r1, - l2_cpu3_ibufid_r1, - l2_cpu3_ls_sync_req, - l2_cpu3_ccb_req_addr_c3, - l2_cpu3_ccb_dbg_req_c3, - l2_cpu3_ls_ccb_clken_c3, - l2_cpu3_ls_ccb_req_c3, - l2_cpu3_ccb_req_id_c3, - l2_cpu3_ccb_req_type_c3, - l2_cpu3_ccb_req_info_c3, - l2_cpu3_if_ccb_clken_c3, - l2_cpu3_if_ccb_req_c3, - l2_cpu3_if_sync_req, - l2_cpu3_tlb_ccb_clken_c3, - l2_cpu3_tlb_ccb_req_c3, - l2_cpu3_tlb_sync_req, - l2_cpu3_tlb_sync_complete, - l2_cpu3_tbw_desc_vld, - l2_cpu3_tbw_ext_err, - l2_cpu3_tbw_ext_err_type, - l2_cpu3_tbw_dbl_ecc_err, - l2_cpu3_tbw_desc_data, - l2_cpu3_spr_rd_data, - l2_cpu3_l2_cache_size, - l2_cpu3_pf_throttle_q, - - l2_cpu3_wr_ex_resp, - l2_cpu3_wr_ex_fail, - - l2_cpu3_ic_base, - l2_cpu3_no_intctrl, - - l2_cpu3_pmu_events, - - ds_cpu3_l2_spr_en, - ds_cpu3_l2_spr_rd, - ds_cpu3_l2_spr_wr, - ds_cpu3_l2_spr_addr, - ds_cpu3_l2_spr_dw, - ds_cpu3_l2_spr_wr_data, - - l2_cpu3_wr_data_vld_x1_q, - l2_cpu3_wr_evict_x1_q, - l2_cpu3_wr_data, - l2_cpu3_ls_rd_haz_vld_arb_q, - l2_cpu3_ls_wr_haz_vld_arb_q, - l2_cpu3_dt_pmu_evt_en, - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_l2_dly, - l2_cpu0_flsh_ls_wr_l2_dly, - - l2_cpu0_wr_data_stall, - - l2_cpu1_flsh_ls_rd_l2_dly, - l2_cpu1_flsh_ls_wr_l2_dly, - - l2_cpu1_wr_data_stall, - - l2_cpu2_flsh_ls_rd_l2_dly, - l2_cpu2_flsh_ls_wr_l2_dly, - - l2_cpu2_wr_data_stall, - - l2_cpu3_flsh_ls_rd_l2_dly, - l2_cpu3_flsh_ls_wr_l2_dly, - - l2_cpu3_wr_data_stall, - - l2_cpu0_flsh_ls_rd_id_l2_dly, - l2_cpu0_flsh_ls_wr_id_l2_dly, - - l2_cpu1_flsh_ls_rd_id_l2_dly, - l2_cpu1_flsh_ls_wr_id_l2_dly, - - l2_cpu2_flsh_ls_rd_id_l2_dly, - l2_cpu2_flsh_ls_wr_id_l2_dly, - - l2_cpu3_flsh_ls_rd_id_l2_dly, - l2_cpu3_flsh_ls_wr_id_l2_dly, - - l2_cpu0_flsh_ls_rd_l4_dly, - l2_cpu0_flsh_if_rd_l4_dly, - l2_cpu0_flsh_tw_rd_l4_dly, - l2_cpu0_flsh_ls_wr_l4_dly, - - l2_cpu1_flsh_ls_rd_l4_dly, - l2_cpu1_flsh_if_rd_l4_dly, - l2_cpu1_flsh_tw_rd_l4_dly, - l2_cpu1_flsh_ls_wr_l4_dly, - - l2_cpu2_flsh_ls_rd_l4_dly, - l2_cpu2_flsh_if_rd_l4_dly, - l2_cpu2_flsh_tw_rd_l4_dly, - l2_cpu2_flsh_ls_wr_l4_dly, - - l2_cpu3_flsh_ls_rd_l4_dly, - l2_cpu3_flsh_if_rd_l4_dly, - l2_cpu3_flsh_tw_rd_l4_dly, - l2_cpu3_flsh_ls_wr_l4_dly, - - l2_cpu0_flsh_ls_rd_id_l4_dly, - l2_cpu0_flsh_if_rd_id_l4_dly, - l2_cpu0_flsh_ls_wr_id_l4_dly, - l2_cpu0_flsh_ls_wr_evict_l4_dly, - - l2_cpu1_flsh_ls_rd_id_l4_dly, - l2_cpu1_flsh_if_rd_id_l4_dly, - l2_cpu1_flsh_ls_wr_id_l4_dly, - l2_cpu1_flsh_ls_wr_evict_l4_dly, - - l2_cpu2_flsh_ls_rd_id_l4_dly, - l2_cpu2_flsh_if_rd_id_l4_dly, - l2_cpu2_flsh_ls_wr_id_l4_dly, - l2_cpu2_flsh_ls_wr_evict_l4_dly, - - l2_cpu3_flsh_ls_rd_id_l4_dly, - l2_cpu3_flsh_if_rd_id_l4_dly, - l2_cpu3_flsh_ls_wr_id_l4_dly, - l2_cpu3_flsh_ls_wr_evict_l4_dly, - - l2_cpu0_lrq_haz_pending, - l2_cpu1_lrq_haz_pending, - l2_cpu2_lrq_haz_pending, - l2_cpu3_lrq_haz_pending, - - l2_cpu0_ifq_haz_pending, - l2_cpu1_ifq_haz_pending, - l2_cpu2_ifq_haz_pending, - l2_cpu3_ifq_haz_pending, - - l2_cpu0_trq_haz_pending, - l2_cpu1_trq_haz_pending, - l2_cpu2_trq_haz_pending, - l2_cpu3_trq_haz_pending, - - l2_cpu0_wrq_haz_pending, - l2_cpu1_wrq_haz_pending, - l2_cpu2_wrq_haz_pending, - l2_cpu3_wrq_haz_pending, - - l2_cpu0_idle_block_reqs_q, - l2_cpu1_idle_block_reqs_q, - l2_cpu2_idle_block_reqs_q, - l2_cpu3_idle_block_reqs_q, - - l2_cpu0_ls_peq_coll_l4_dly, - l2_cpu1_ls_peq_coll_l4_dly, - l2_cpu2_ls_peq_coll_l4_dly, - l2_cpu3_ls_peq_coll_l4_dly, - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, - l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_trq_clr_l4_dly2_q, - l2_tbnk0_cpu1_trq_clr_l4_dly2_q, - l2_tbnk0_cpu2_trq_clr_l4_dly2_q, - l2_tbnk0_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_trq_clr_l4_dly2_q, - l2_tbnk1_cpu1_trq_clr_l4_dly2_q, - l2_tbnk1_cpu2_trq_clr_l4_dly2_q, - l2_tbnk1_cpu3_trq_clr_l4_dly2_q, - - l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, - - l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, - l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, - - l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, - l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - l2_cpu0_dsq_rd_data_q, - l2_cpu0_dsq_rd_byte_strb_q, - l2_cpu1_dsq_rd_data_q, - l2_cpu1_dsq_rd_byte_strb_q, - l2_cpu2_dsq_rd_data_q, - l2_cpu2_dsq_rd_byte_strb_q, - l2_cpu3_dsq_rd_data_q, - l2_cpu3_dsq_rd_byte_strb_q, - - l2_cpu0_dsq_clr_vld_q, - l2_cpu0_dsq_clr_id_q, - l2_cpu0_dsq_rd_en, - l2_cpu0_dsq_rd_en_x2, - l2_cpu0_dsq_rd_buf_id, - l2_cpu1_dsq_clr_vld_q, - l2_cpu1_dsq_clr_id_q, - l2_cpu1_dsq_rd_en, - l2_cpu1_dsq_rd_en_x2, - l2_cpu1_dsq_rd_buf_id, - l2_cpu2_dsq_clr_vld_q, - l2_cpu2_dsq_clr_id_q, - l2_cpu2_dsq_rd_en, - l2_cpu2_dsq_rd_en_x2, - l2_cpu2_dsq_rd_buf_id, - l2_cpu3_dsq_clr_vld_q, - l2_cpu3_dsq_rd_en, - l2_cpu3_dsq_rd_en_x2, - l2_cpu3_dsq_clr_id_q, - l2_cpu3_dsq_rd_buf_id, - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - l2_cpu0_rd_vld_skid, - l2_cpu1_rd_vld_skid, - l2_cpu2_rd_vld_skid, - l2_cpu3_rd_vld_skid, - - l2_cpu0_pf_rd_vld_skid_popped, - l2_cpu1_pf_rd_vld_skid_popped, - l2_cpu2_pf_rd_vld_skid_popped, - l2_cpu3_pf_rd_vld_skid_popped, - - l2_cpu0_rd_arb, - l2_cpu1_rd_arb, - l2_cpu2_rd_arb, - l2_cpu3_rd_arb, - - l2_cpu0_wr_vld_skid, - l2_cpu1_wr_vld_skid, - l2_cpu2_wr_vld_skid, - l2_cpu3_wr_vld_skid, - - l2_cpu0_wr_arb, - l2_cpu1_wr_arb, - l2_cpu2_wr_arb, - l2_cpu3_wr_arb, - - l2_cpu0_ic_vld_skid, - l2_cpu1_ic_vld_skid, - l2_cpu2_ic_vld_skid, - l2_cpu3_ic_vld_skid, - - l2_cpu0_ic_barrier_stall_q, - l2_cpu1_ic_barrier_stall_q, - l2_cpu2_ic_barrier_stall_q, - l2_cpu3_ic_barrier_stall_q, - - l2_cpu0_blk_non_evict_wr, - l2_cpu1_blk_non_evict_wr, - l2_cpu2_blk_non_evict_wr, - l2_cpu3_blk_non_evict_wr, - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - l2_cpu0_idle_wakeup_q, - l2_cpu0_rd_arb_fast, - l2_cpu0_rd_id_arb_set, - l2_cpu0_rd_lrq_id_arb_set, - l2_cpu0_rd_type_arb_set, - l2_cpu0_rd_cache_attr_arb_set, - l2_cpu0_rd_page_attr_arb_set, - l2_cpu0_rd_elem_size_arb_set, - l2_cpu0_rd_way_arb_set, - l2_cpu0_rd_replayed_arb_set, - l2_cpu0_rd_excl_arb_set, - l2_cpu0_rd_priv_arb_set, - l2_cpu0_rd_shared_arb_set, - l2_cpu0_rd_va48_arb_set, - l2_cpu0_rd_aarch64_arb_set, - l2_cpu0_rd_asid_arb_set, - l2_cpu0_rd_prfm_arb_set, - l2_cpu0_rd_addr_arb_set, - l2_cpu0_rd_bypass_arb_set, - l2_cpu0_rd_bypass_req_can_e5, - l2_cpu0_early_rd_reqe4_e5_q, - l2_cpu0_rd_bypass_way_e5, - l2_cpu0_rd_bypass_bufid_e5, - l2_cpu0_rd_bypass_lrq_id_e5, - - l2_cpu0_wr_arb_fast, - l2_cpu0_wr_id_arb_set, - l2_cpu0_wr_partial_dw_arb_set, - l2_cpu0_wr_cache_attr_arb_set, - l2_cpu0_wr_page_attr_arb_set, - l2_cpu0_wr_elem_size_arb_set, - l2_cpu0_wr_type_arb_set, - l2_cpu0_wr_cl_id_arb_set, - l2_cpu0_wr_priv_arb_set, - l2_cpu0_wr_shared_arb_set, - l2_cpu0_wr_last_arb_set, - l2_cpu0_wr_clean_evict_arb_set, - l2_cpu0_wr_err_arb_set, - l2_cpu0_wr_way_arb_set, - l2_cpu0_wr_dirty_arb_set, - l2_cpu0_wr_1st_replayed_arb_set, - l2_cpu0_wr_addr_arb_set, - l2_cpu0_ic_arb_fast, - l2_cpu0_ic_id_arb_set, - l2_cpu0_ic_write_arb_set, - l2_cpu0_ic_excl_arb_set, - l2_cpu0_ic_elem_size_arb_set, - l2_cpu0_ic_ns_arb_set, - l2_cpu0_ic_addr_arb_set, - l2_cpu0_ic_data_arb_set, - - l2_cpu0_wrq_almost_full, - - l2_cpu0_ls_wr_req_w2a, - l2_cpu0_ls_wr_last_w2a, - l2_cpu0_ls_wr_dirty_w2a, - l2_cpu0_ls_wr_err_w2a, - l2_cpu0_ls_wr_type_w2a, - l2_cpu0_ls_wr_ccb_id_w2a, - l2_cpu0_ls_wr_data_w2a, - - l2_cpu0_ls_ccb_resp, - l2_cpu0_ls_ccb_resp_id, - l2_cpu0_ls_ccb_data_wr, - - l2_cpu0_if_ccb_resp, - l2_cpu0_if_ccb_resp_id, - - l2_cpu0_tw_ccb_resp, - l2_cpu0_tw_ccb_resp_id, - - l2_cpu0_if_sync_done_q, - l2_cpu0_tlb_sync_done_q, - - l2_cpu0_lrq_haz_clr_id_dcd_q, - l2_cpu0_wrq_haz_clr_id_dcd_q, - l2_cpu0_ls_rd_haz_id_arb_q, - l2_cpu0_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - l2_cpu1_idle_wakeup_q, - l2_cpu1_rd_arb_fast, - l2_cpu1_rd_id_arb_set, - l2_cpu1_rd_lrq_id_arb_set, - l2_cpu1_rd_type_arb_set, - l2_cpu1_rd_cache_attr_arb_set, - l2_cpu1_rd_page_attr_arb_set, - l2_cpu1_rd_elem_size_arb_set, - l2_cpu1_rd_way_arb_set, - l2_cpu1_rd_replayed_arb_set, - l2_cpu1_rd_excl_arb_set, - l2_cpu1_rd_priv_arb_set, - l2_cpu1_rd_shared_arb_set, - l2_cpu1_rd_va48_arb_set, - l2_cpu1_rd_aarch64_arb_set, - l2_cpu1_rd_asid_arb_set, - l2_cpu1_rd_prfm_arb_set, - l2_cpu1_rd_addr_arb_set, - l2_cpu1_rd_bypass_arb_set, - l2_cpu1_rd_bypass_req_can_e5, - l2_cpu1_early_rd_reqe4_e5_q, - l2_cpu1_rd_bypass_way_e5, - l2_cpu1_rd_bypass_bufid_e5, - l2_cpu1_rd_bypass_lrq_id_e5, - - l2_cpu1_wr_arb_fast, - l2_cpu1_wr_id_arb_set, - l2_cpu1_wr_partial_dw_arb_set, - l2_cpu1_wr_cache_attr_arb_set, - l2_cpu1_wr_page_attr_arb_set, - l2_cpu1_wr_elem_size_arb_set, - l2_cpu1_wr_type_arb_set, - l2_cpu1_wr_cl_id_arb_set, - l2_cpu1_wr_priv_arb_set, - l2_cpu1_wr_shared_arb_set, - l2_cpu1_wr_last_arb_set, - l2_cpu1_wr_clean_evict_arb_set, - l2_cpu1_wr_err_arb_set, - l2_cpu1_wr_way_arb_set, - l2_cpu1_wr_dirty_arb_set, - l2_cpu1_wr_1st_replayed_arb_set, - l2_cpu1_wr_addr_arb_set, - l2_cpu1_ic_arb_fast, - l2_cpu1_ic_id_arb_set, - l2_cpu1_ic_write_arb_set, - l2_cpu1_ic_excl_arb_set, - l2_cpu1_ic_elem_size_arb_set, - l2_cpu1_ic_ns_arb_set, - l2_cpu1_ic_addr_arb_set, - l2_cpu1_ic_data_arb_set, - - l2_cpu1_wrq_almost_full, - - l2_cpu1_ls_wr_req_w2a, - l2_cpu1_ls_wr_last_w2a, - l2_cpu1_ls_wr_dirty_w2a, - l2_cpu1_ls_wr_err_w2a, - l2_cpu1_ls_wr_type_w2a, - l2_cpu1_ls_wr_ccb_id_w2a, - l2_cpu1_ls_wr_data_w2a, - - l2_cpu1_ls_ccb_resp, - l2_cpu1_ls_ccb_resp_id, - l2_cpu1_ls_ccb_data_wr, - - l2_cpu1_if_ccb_resp, - l2_cpu1_if_ccb_resp_id, - - l2_cpu1_tw_ccb_resp, - l2_cpu1_tw_ccb_resp_id, - - l2_cpu1_if_sync_done_q, - l2_cpu1_tlb_sync_done_q, - - l2_cpu1_lrq_haz_clr_id_dcd_q, - l2_cpu1_wrq_haz_clr_id_dcd_q, - l2_cpu1_ls_rd_haz_id_arb_q, - l2_cpu1_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - l2_cpu2_idle_wakeup_q, - l2_cpu2_rd_arb_fast, - l2_cpu2_rd_id_arb_set, - l2_cpu2_rd_lrq_id_arb_set, - l2_cpu2_rd_type_arb_set, - l2_cpu2_rd_cache_attr_arb_set, - l2_cpu2_rd_page_attr_arb_set, - l2_cpu2_rd_elem_size_arb_set, - l2_cpu2_rd_way_arb_set, - l2_cpu2_rd_replayed_arb_set, - l2_cpu2_rd_excl_arb_set, - l2_cpu2_rd_priv_arb_set, - l2_cpu2_rd_shared_arb_set, - l2_cpu2_rd_va48_arb_set, - l2_cpu2_rd_aarch64_arb_set, - l2_cpu2_rd_asid_arb_set, - l2_cpu2_rd_prfm_arb_set, - l2_cpu2_rd_addr_arb_set, - l2_cpu2_rd_bypass_arb_set, - l2_cpu2_rd_bypass_req_can_e5, - l2_cpu2_early_rd_reqe4_e5_q, - l2_cpu2_rd_bypass_way_e5, - l2_cpu2_rd_bypass_bufid_e5, - l2_cpu2_rd_bypass_lrq_id_e5, - - l2_cpu2_wr_arb_fast, - l2_cpu2_wr_id_arb_set, - l2_cpu2_wr_partial_dw_arb_set, - l2_cpu2_wr_cache_attr_arb_set, - l2_cpu2_wr_page_attr_arb_set, - l2_cpu2_wr_elem_size_arb_set, - l2_cpu2_wr_type_arb_set, - l2_cpu2_wr_cl_id_arb_set, - l2_cpu2_wr_priv_arb_set, - l2_cpu2_wr_shared_arb_set, - l2_cpu2_wr_last_arb_set, - l2_cpu2_wr_clean_evict_arb_set, - l2_cpu2_wr_err_arb_set, - l2_cpu2_wr_way_arb_set, - l2_cpu2_wr_dirty_arb_set, - l2_cpu2_wr_1st_replayed_arb_set, - l2_cpu2_wr_addr_arb_set, - l2_cpu2_ic_arb_fast, - l2_cpu2_ic_id_arb_set, - l2_cpu2_ic_write_arb_set, - l2_cpu2_ic_excl_arb_set, - l2_cpu2_ic_elem_size_arb_set, - l2_cpu2_ic_ns_arb_set, - l2_cpu2_ic_addr_arb_set, - l2_cpu2_ic_data_arb_set, - - l2_cpu2_wrq_almost_full, - - l2_cpu2_ls_wr_req_w2a, - l2_cpu2_ls_wr_last_w2a, - l2_cpu2_ls_wr_dirty_w2a, - l2_cpu2_ls_wr_err_w2a, - l2_cpu2_ls_wr_type_w2a, - l2_cpu2_ls_wr_ccb_id_w2a, - l2_cpu2_ls_wr_data_w2a, - - l2_cpu2_ls_ccb_resp, - l2_cpu2_ls_ccb_resp_id, - l2_cpu2_ls_ccb_data_wr, - - l2_cpu2_if_ccb_resp, - l2_cpu2_if_ccb_resp_id, - - l2_cpu2_tw_ccb_resp, - l2_cpu2_tw_ccb_resp_id, - - l2_cpu2_if_sync_done_q, - l2_cpu2_tlb_sync_done_q, - - l2_cpu2_lrq_haz_clr_id_dcd_q, - l2_cpu2_wrq_haz_clr_id_dcd_q, - l2_cpu2_ls_rd_haz_id_arb_q, - l2_cpu2_ls_wr_haz_id_arb_q, - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - l2_cpu3_idle_wakeup_q, - l2_cpu3_rd_arb_fast, - l2_cpu3_rd_id_arb_set, - l2_cpu3_rd_lrq_id_arb_set, - l2_cpu3_rd_type_arb_set, - l2_cpu3_rd_cache_attr_arb_set, - l2_cpu3_rd_page_attr_arb_set, - l2_cpu3_rd_elem_size_arb_set, - l2_cpu3_rd_way_arb_set, - l2_cpu3_rd_replayed_arb_set, - l2_cpu3_rd_excl_arb_set, - l2_cpu3_rd_priv_arb_set, - l2_cpu3_rd_shared_arb_set, - l2_cpu3_rd_va48_arb_set, - l2_cpu3_rd_aarch64_arb_set, - l2_cpu3_rd_asid_arb_set, - l2_cpu3_rd_prfm_arb_set, - l2_cpu3_rd_addr_arb_set, - l2_cpu3_rd_bypass_arb_set, - l2_cpu3_rd_bypass_req_can_e5, - l2_cpu3_early_rd_reqe4_e5_q, - l2_cpu3_rd_bypass_way_e5, - l2_cpu3_rd_bypass_bufid_e5, - l2_cpu3_rd_bypass_lrq_id_e5, - - l2_cpu3_wr_arb_fast, - l2_cpu3_wr_id_arb_set, - l2_cpu3_wr_partial_dw_arb_set, - l2_cpu3_wr_cache_attr_arb_set, - l2_cpu3_wr_page_attr_arb_set, - l2_cpu3_wr_elem_size_arb_set, - l2_cpu3_wr_type_arb_set, - l2_cpu3_wr_cl_id_arb_set, - l2_cpu3_wr_priv_arb_set, - l2_cpu3_wr_shared_arb_set, - l2_cpu3_wr_last_arb_set, - l2_cpu3_wr_clean_evict_arb_set, - l2_cpu3_wr_err_arb_set, - l2_cpu3_wr_way_arb_set, - l2_cpu3_wr_dirty_arb_set, - l2_cpu3_wr_1st_replayed_arb_set, - l2_cpu3_wr_addr_arb_set, - l2_cpu3_ic_arb_fast, - l2_cpu3_ic_id_arb_set, - l2_cpu3_ic_write_arb_set, - l2_cpu3_ic_excl_arb_set, - l2_cpu3_ic_elem_size_arb_set, - l2_cpu3_ic_ns_arb_set, - l2_cpu3_ic_addr_arb_set, - l2_cpu3_ic_data_arb_set, - - l2_cpu3_wrq_almost_full, - - l2_cpu3_ls_wr_req_w2a, - l2_cpu3_ls_wr_last_w2a, - l2_cpu3_ls_wr_dirty_w2a, - l2_cpu3_ls_wr_err_w2a, - l2_cpu3_ls_wr_type_w2a, - l2_cpu3_ls_wr_ccb_id_w2a, - l2_cpu3_ls_wr_data_w2a, - - l2_cpu3_ls_ccb_resp, - l2_cpu3_ls_ccb_resp_id, - l2_cpu3_ls_ccb_data_wr, - - l2_cpu3_if_ccb_resp, - l2_cpu3_if_ccb_resp_id, - - l2_cpu3_tw_ccb_resp, - l2_cpu3_tw_ccb_resp_id, - - l2_cpu3_if_sync_done_q, - l2_cpu3_tlb_sync_done_q, - - l2_cpu3_lrq_haz_clr_id_dcd_q, - l2_cpu3_wrq_haz_clr_id_dcd_q, - l2_cpu3_ls_rd_haz_id_arb_q, - l2_cpu3_ls_wr_haz_id_arb_q, - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - tm_cpu0_cntkctl_usr, - tm_cpu0_cnthctl_kernel, - - tm_cpu1_cntkctl_usr, - tm_cpu1_cnthctl_kernel, - - tm_cpu2_cntkctl_usr, - tm_cpu2_cnthctl_kernel, - - tm_cpu3_cntkctl_usr, - tm_cpu3_cnthctl_kernel, -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - ls_cpu0_imp_abort_slv, - ls_cpu0_imp_abort_ecc, - ls_cpu0_imp_abort_dec, - ls_cpu0_imp_abort_containable, - ls_cpu0_raw_eae_nonsec, - ls_cpu0_raw_eae_secure, - - ds_cpu0_ic_cpsr_mode, - ds_cpu0_ic_sample_spr, - ds_cpu0_ic_aa64naa32, - ds_cpu0_ic_hcr_change, - ds_cpu0_ic_scr_change, -// BEGIN INCLUDE FOR CPU1 - ds_cpu1_ic_cpsr_mode, - ds_cpu1_ic_sample_spr, - ds_cpu1_ic_aa64naa32, - ds_cpu1_ic_hcr_change, - ds_cpu1_ic_scr_change, - ls_cpu1_imp_abort_slv, - ls_cpu1_imp_abort_ecc, - ls_cpu1_imp_abort_dec, - ls_cpu1_imp_abort_containable, - ls_cpu1_raw_eae_nonsec, - ls_cpu1_raw_eae_secure, -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - ds_cpu2_ic_cpsr_mode, - ds_cpu2_ic_sample_spr, - ds_cpu2_ic_aa64naa32, - ds_cpu2_ic_hcr_change, - ds_cpu2_ic_scr_change, - ls_cpu2_imp_abort_slv, - ls_cpu2_imp_abort_ecc, - ls_cpu2_imp_abort_dec, - ls_cpu2_imp_abort_containable, - ls_cpu2_raw_eae_nonsec, - ls_cpu2_raw_eae_secure, -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - ds_cpu3_ic_cpsr_mode, - ds_cpu3_ic_sample_spr, - ds_cpu3_ic_aa64naa32, - ds_cpu3_ic_hcr_change, - ds_cpu3_ic_scr_change, - ls_cpu3_imp_abort_slv, - ls_cpu3_imp_abort_ecc, - ls_cpu3_imp_abort_dec, - ls_cpu3_imp_abort_containable, - ls_cpu3_raw_eae_nonsec, - ls_cpu3_raw_eae_secure, -// END INCLUDE FOR CPU3 - - ic_nfiq, - ic_nirq, - ic_nsei, - ic_nvfiq, - ic_nvirq, - ic_nvsei, - ic_p_valid, - - ic_sample_spr, - ic_hcr_change_complete, - ic_scr_change_complete, - ic_el_change_complete, - ic_ich_el2_tc, - ic_ich_el2_tall0, - ic_ich_el2_tall1, - ic_sra_el3_en, - ic_sra_el1s_en, - ic_sra_el2_en, - ic_sra_el1ns_en, - ic_sre_el1ns_hyp_trap, - ic_sre_el1ns_mon_trap, - ic_sre_el1s_mon_trap, - ic_sre_el2_mon_trap, - ic_block_eoi_sgi_wr, - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - dt_cpu0_et_oslock_gclk, - dt_cpu0_os_double_lock_gclk, - dt_cpu0_halt_ack_gclk, - dt_cpu0_coredbg_in_reset_gclk, - dt_cpu0_wfx_dbg_req_gclk, - dt_cpu0_hlt_dbgevt_ok_gclk, - dt_cpu0_dbif_ack_gclk, - dt_cpu0_dbif_err_gclk, - dt_cpu0_dbif_rddata_gclk, - - dt_cpu0_dbif_addr_pclk, - dt_cpu0_dbif_locked_pclk, - dt_cpu0_dbif_req_pclk, - dt_cpu0_dbif_wrdata_pclk, - dt_cpu0_dbif_write_pclk, - dt_cpu0_edecr_osuce_pclk, - dt_cpu0_edecr_rce_pclk, - dt_cpu0_edecr_ss_pclk, - dt_cpu0_edbgrq_pclk, - dt_cpu0_edacr_frc_idleack_pclk, - dt_cpu0_edprcr_corepurq_pclk, - - dt_cpu0_pmusnapshot_ack_gclk, - dt_cpu0_pmusnapshot_req_pclk, - - dt_cpu0_cti_trigin_7to4_gclk, - dt_cpu0_cti_trigin_1to0_gclk, - dt_cpu0_cti_trigoutack_7to4_gclk, - dt_cpu0_cti_trigoutack_bit1_gclk, - - dt_cpu0_cti_trigout_7to4_pclk, - dt_cpu0_cti_trigout_1to0_pclk, - dt_cpu0_cti_triginack_7to4_pclk, - dt_cpu0_cti_triginack_1to0_pclk, - - dt_cpu0_wfx_wakeup_pclk, - dt_cpu0_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - dt_cpu1_et_oslock_gclk, - dt_cpu1_os_double_lock_gclk, - dt_cpu1_halt_ack_gclk, - dt_cpu1_coredbg_in_reset_gclk, - dt_cpu1_wfx_dbg_req_gclk, - dt_cpu1_hlt_dbgevt_ok_gclk, - dt_cpu1_dbif_ack_gclk, - dt_cpu1_dbif_err_gclk, - dt_cpu1_dbif_rddata_gclk, - - dt_cpu1_dbif_addr_pclk, - dt_cpu1_dbif_locked_pclk, - dt_cpu1_dbif_req_pclk, - dt_cpu1_dbif_wrdata_pclk, - dt_cpu1_dbif_write_pclk, - dt_cpu1_edecr_osuce_pclk, - dt_cpu1_edecr_rce_pclk, - dt_cpu1_edecr_ss_pclk, - dt_cpu1_edbgrq_pclk, - dt_cpu1_edacr_frc_idleack_pclk, - dt_cpu1_edprcr_corepurq_pclk, - - dt_cpu1_pmusnapshot_ack_gclk, - dt_cpu1_pmusnapshot_req_pclk, - - dt_cpu1_cti_trigin_7to4_gclk, - dt_cpu1_cti_trigin_1to0_gclk, - dt_cpu1_cti_trigoutack_7to4_gclk, - dt_cpu1_cti_trigoutack_bit1_gclk, - - dt_cpu1_cti_trigout_7to4_pclk, - dt_cpu1_cti_trigout_1to0_pclk, - dt_cpu1_cti_triginack_7to4_pclk, - dt_cpu1_cti_triginack_1to0_pclk, - - dt_cpu1_wfx_wakeup_pclk, - dt_cpu1_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - dt_cpu2_et_oslock_gclk, - dt_cpu2_os_double_lock_gclk, - dt_cpu2_halt_ack_gclk, - dt_cpu2_coredbg_in_reset_gclk, - dt_cpu2_wfx_dbg_req_gclk, - dt_cpu2_hlt_dbgevt_ok_gclk, - dt_cpu2_dbif_ack_gclk, - dt_cpu2_dbif_err_gclk, - dt_cpu2_dbif_rddata_gclk, - - dt_cpu2_dbif_addr_pclk, - dt_cpu2_dbif_locked_pclk, - dt_cpu2_dbif_req_pclk, - dt_cpu2_dbif_wrdata_pclk, - dt_cpu2_dbif_write_pclk, - dt_cpu2_edecr_osuce_pclk, - dt_cpu2_edecr_rce_pclk, - dt_cpu2_edecr_ss_pclk, - dt_cpu2_edbgrq_pclk, - dt_cpu2_edacr_frc_idleack_pclk, - dt_cpu2_edprcr_corepurq_pclk, - - dt_cpu2_pmusnapshot_ack_gclk, - dt_cpu2_pmusnapshot_req_pclk, - - dt_cpu2_cti_trigin_7to4_gclk, - dt_cpu2_cti_trigin_1to0_gclk, - dt_cpu2_cti_trigoutack_7to4_gclk, - dt_cpu2_cti_trigoutack_bit1_gclk, - - dt_cpu2_cti_trigout_7to4_pclk, - dt_cpu2_cti_trigout_1to0_pclk, - dt_cpu2_cti_triginack_7to4_pclk, - dt_cpu2_cti_triginack_1to0_pclk, - - dt_cpu2_wfx_wakeup_pclk, - dt_cpu2_noclkstop_pclk, -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - dt_cpu3_et_oslock_gclk, - dt_cpu3_os_double_lock_gclk, - dt_cpu3_halt_ack_gclk, - dt_cpu3_coredbg_in_reset_gclk, - dt_cpu3_wfx_dbg_req_gclk, - dt_cpu3_hlt_dbgevt_ok_gclk, - dt_cpu3_dbif_ack_gclk, - dt_cpu3_dbif_err_gclk, - dt_cpu3_dbif_rddata_gclk, - - dt_cpu3_dbif_addr_pclk, - dt_cpu3_dbif_locked_pclk, - dt_cpu3_dbif_req_pclk, - dt_cpu3_dbif_wrdata_pclk, - dt_cpu3_dbif_write_pclk, - dt_cpu3_edecr_osuce_pclk, - dt_cpu3_edecr_rce_pclk, - dt_cpu3_edecr_ss_pclk, - dt_cpu3_edbgrq_pclk, - dt_cpu3_edacr_frc_idleack_pclk, - dt_cpu3_edprcr_corepurq_pclk, - - dt_cpu3_pmusnapshot_ack_gclk, - dt_cpu3_pmusnapshot_req_pclk, - - dt_cpu3_cti_trigin_7to4_gclk, - dt_cpu3_cti_trigin_1to0_gclk, - dt_cpu3_cti_trigoutack_7to4_gclk, - dt_cpu3_cti_trigoutack_bit1_gclk, - - dt_cpu3_cti_trigout_7to4_pclk, - dt_cpu3_cti_trigout_1to0_pclk, - dt_cpu3_cti_triginack_7to4_pclk, - dt_cpu3_cti_triginack_1to0_pclk, - - dt_cpu3_wfx_wakeup_pclk, - dt_cpu3_noclkstop_pclk, -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - ds_cpu0_reset_req, - ds_cpu0_wfi_req, - ds_cpu0_wfe_req, - ds_cpu0_flush, - ds_cpu0_flush_type, - ds_cpu0_imp_abrt_wfi_qual, - ds_cpu0_irq_wfi_qual, - ds_cpu0_fiq_wfi_qual, - ds_cpu0_vimp_abrt_wfi_qual, - ds_cpu0_virq_wfi_qual, - ds_cpu0_vfiq_wfi_qual, - ds_cpu0_imp_abrt_wfe_qual, - ds_cpu0_irq_wfe_qual, - ds_cpu0_fiq_wfe_qual, - ds_cpu0_vimp_abrt_wfe_qual, - ds_cpu0_virq_wfe_qual, - ds_cpu0_vfiq_wfe_qual, - ds_cpu0_hcr_va, - ds_cpu0_hcr_vi, - ds_cpu0_hcr_vf, - ds_cpu0_cpuectlr_ret, - ck_cpu0_event_reg, - ck_cpu0_wfi_ack, - ck_cpu0_wfe_ack, - ck_cpu0_crcx_clk_en_n, - - ds_cpu1_reset_req, - ds_cpu1_wfi_req, - ds_cpu1_wfe_req, - ds_cpu1_flush, - ds_cpu1_flush_type, - ds_cpu1_imp_abrt_wfi_qual, - ds_cpu1_irq_wfi_qual, - ds_cpu1_fiq_wfi_qual, - ds_cpu1_vimp_abrt_wfi_qual, - ds_cpu1_virq_wfi_qual, - ds_cpu1_vfiq_wfi_qual, - ds_cpu1_imp_abrt_wfe_qual, - ds_cpu1_irq_wfe_qual, - ds_cpu1_fiq_wfe_qual, - ds_cpu1_vimp_abrt_wfe_qual, - ds_cpu1_virq_wfe_qual, - ds_cpu1_vfiq_wfe_qual, - ds_cpu1_hcr_va, - ds_cpu1_hcr_vi, - ds_cpu1_hcr_vf, - ds_cpu1_cpuectlr_ret, - ck_cpu1_event_reg, - ck_cpu1_wfi_ack, - ck_cpu1_wfe_ack, - ck_cpu1_crcx_clk_en_n, - - ds_cpu2_reset_req, - ds_cpu2_wfi_req, - ds_cpu2_wfe_req, - ds_cpu2_flush, - ds_cpu2_flush_type, - ds_cpu2_imp_abrt_wfi_qual, - ds_cpu2_irq_wfi_qual, - ds_cpu2_fiq_wfi_qual, - ds_cpu2_vimp_abrt_wfi_qual, - ds_cpu2_virq_wfi_qual, - ds_cpu2_vfiq_wfi_qual, - ds_cpu2_imp_abrt_wfe_qual, - ds_cpu2_irq_wfe_qual, - ds_cpu2_fiq_wfe_qual, - ds_cpu2_vimp_abrt_wfe_qual, - ds_cpu2_virq_wfe_qual, - ds_cpu2_vfiq_wfe_qual, - ds_cpu2_hcr_va, - ds_cpu2_hcr_vi, - ds_cpu2_hcr_vf, - ds_cpu2_cpuectlr_ret, - ck_cpu2_event_reg, - ck_cpu2_wfi_ack, - ck_cpu2_wfe_ack, - ck_cpu2_crcx_clk_en_n, - - ds_cpu3_reset_req, - ds_cpu3_wfi_req, - ds_cpu3_wfe_req, - ds_cpu3_flush, - ds_cpu3_flush_type, - ds_cpu3_imp_abrt_wfi_qual, - ds_cpu3_irq_wfi_qual, - ds_cpu3_fiq_wfi_qual, - ds_cpu3_vimp_abrt_wfi_qual, - ds_cpu3_virq_wfi_qual, - ds_cpu3_vfiq_wfi_qual, - ds_cpu3_imp_abrt_wfe_qual, - ds_cpu3_irq_wfe_qual, - ds_cpu3_fiq_wfe_qual, - ds_cpu3_vimp_abrt_wfe_qual, - ds_cpu3_virq_wfe_qual, - ds_cpu3_vfiq_wfe_qual, - ds_cpu3_hcr_va, - ds_cpu3_hcr_vi, - ds_cpu3_hcr_vf, - ds_cpu3_cpuectlr_ret, - ck_cpu3_event_reg, - ck_cpu3_wfi_ack, - ck_cpu3_wfe_ack, - ck_cpu3_crcx_clk_en_n, - - ls_cpu0_clrexmon, - ls_cpu1_clrexmon, - ls_cpu2_clrexmon, - ls_cpu3_clrexmon, -// END CK-CPU interface - - ck_gclkt -); - -//# -//# Interface Signals -//# ================= -//# - -//----------------------------------------------------------------------------- -// Clock and Reset Signals -//----------------------------------------------------------------------------- - input CLK; // Fast Clock - input CLKEN; // Fast Clock Enable - - input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset - input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) - input nL2RESET; // L2 reset - input L2RSTDISABLE; // L2 RAMs hardware reset disable - output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request -//See also nPRESETDBG; // Debug APB reset (PCLK) - -//----------------------------------------------------------------------------- -// Static Configuration Signals -//----------------------------------------------------------------------------- -// Static configuration signals that should be tied off and not change dynamically. -// Many of the initial values specified by these inputs -// may be overridden in software using CP15 registers. - - input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) - input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors - input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) - input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers - - input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] - input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] - - input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) - input [43:2] RVBARADDR0; // RVBAR address -// BEGIN INCLUDE FOR CPU1 - input [43:2] RVBARADDR1; // RVBAR address -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input [43:2] RVBARADDR2; // RVBAR address -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input [43:2] RVBARADDR3; // RVBAR address -// END INCLUDE FOR CPU3 - input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension - -//----------------------------------------------------------------------------- -// Interrupt Controller Signals -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] nFIQ; // Fast Interrupt request - input [`MAIA_CN:0] nIRQ; // Interrupt request - input [`MAIA_CN:0] nSEI; // System Error Interrupt - input [`MAIA_CN:0] nREI; // RAM Error Interrupt - input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request - input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request - input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt - -// BEGIN NO-GIC pins - output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output -// END NO-GIC pins - - input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers -// BEGIN NO-GIC pins - input GICCDISABLE; // Put GIC into bypass mode - - input ICDTVALID; // Distrubuter AXI4 SP Message Valid - output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message - input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data - input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet - input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID - - output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid - input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message - output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data - output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet - output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID -// END NO-GIC pins - -//----------------------------------------------------------------------------- -// Timer Signals -//----------------------------------------------------------------------------- - input [63:0] CNTVALUEB; // Counter value in binary - input CNTCLKEN; // Counter clock enable - output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event - output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event - output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event - output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event - -//----------------------------------------------------------------------------- -// Power Management Signals -//----------------------------------------------------------------------------- - input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) - output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) - input EVENTI; // Event input for processor wake-up from WFE state - output EVENTO; // Event output, signal is active when SEV instruction is executed - output [`MAIA_CN:0] STANDBYWFI; // WFI mode - output [`MAIA_CN:0] STANDBYWFE; // WFE mode - output STANDBYWFIL2; // WFI mode for L2 - output [`MAIA_CN:0] SMPEN; // CPU SMP bit - - output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE - input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn - output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn - output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY - - output L2QACTIVE; // L2 Q-channel QACTIVE - input L2QREQn; // L2 Q-channel QREQn - output L2QACCEPTn; // L2 Q-channel QACCEPTn - output L2QDENY; // L2 Q-channel QDENY - - input L2FLUSHREQ; // L2 hardware flush request - output L2FLUSHDONE; // L2 hardware flush done - -//----------------------------------------------------------------------------- -// Asynchronous Error Signals -//----------------------------------------------------------------------------- - output nINTERRIRQ; // L2 RAM dbl-bit ECC error - output nEXTERRIRQ; // Write transaction error - -//----------------------------------------------------------------------------- -// Bus Configuration Signals -//----------------------------------------------------------------------------- - input SYSBARDISABLE; // Disable broadcast of barriers - input BROADCASTINNER; // Extend Inner Shared Domain - input BROADCASTOUTER; // Extend Outer Shared Domain - input BROADCASTCACHEMAINT; // Broadcast cache maint ops - -//----------------------------------------------------------------------------- -// Skyros RN-F Interface -//----------------------------------------------------------------------------- - input SCLKEN; // Skyros clock enable - input SINACT; // Skyros snoop inactive - - input [6:0] NODEID; // Skyros requestor NodeID - - output TXSACTIVE; // Skyros active - indicates pending activity on pins - input RXSACTIVE; // Skyros active - indicates pending activity on pins - - output TXLINKACTIVEREQ; // Skyros transmit link active request - input TXLINKACTIVEACK; // SKyros transmit link active acknowledge - - input RXLINKACTIVEREQ; // SKyros receive link active request - output RXLINKACTIVEACK; // Skyros receive link active acknowledge - -// TXREQ - outbound requests - output TXREQFLITPEND; // Skyros TXREQ FLIT pending - output TXREQFLITV; // Skyros TXREQ FLIT valid - output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload - output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes - input TXREQLCRDV; // Skyros TXREQ link-layer credit valid - -// TXRSP - outbound response - output TXRSPFLITPEND; // Skyros TXRSP FLIT pending - output TXRSPFLITV; // Skyros TXRSP FLIT valid - output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload - input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid - -// TXDAT - outbound data - output TXDATFLITPEND; // Skyros TXDAT FLIT pending - output TXDATFLITV; // Skyros TXDAT FLIT valid - output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload - input TXDATLCRDV; // Skyros TXDAT link-layer credit valid - -// RXSNP - inbound snoops - input RXSNPFLITPEND; // Skyros RXSNP FLIT pending - input RXSNPFLITV; // Skyros RXSNP FLIT valid - input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload - output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid - -// RXRSP - inbound response - input RXRSPFLITPEND; // Skyros RXRSP FLIT pending - input RXRSPFLITV; // Skyros RXRSP FLIT valid - input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload - output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid - -// RXDAT - inbound data - input RXDATFLITPEND; // Skyros RXDAT FLIT pending - input RXDATFLITV; // Skyros RXDAT FLIT valid - input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload - output RXDATLCRDV; // Skyros RXDAT link-layer credit valid - - input [43:24] SAMMNBASE; // Skyros SAM MN base address - input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping - input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping - input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping - input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping - input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping - input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping - input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping - input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping - input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping - input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping - input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping - input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping - input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping - input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping - input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping - input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping - input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping - input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping - input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping - input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping - input [6:0] SAMMNNODEID; // Skyros SAM MN target ID - input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID - input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID - input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID - input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID - input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID - input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID - input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID - input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID - input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID - input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID - input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode - -// BEGIN NO-ACP pins -//----------------------------------------------------------------------------- -// ACP AXI Slave -//----------------------------------------------------------------------------- - input ACLKENS; // AXI slave clock enable - input AINACTS; // AXI slave interface no longer active or accepting requests -// Write Address channel signals - output AWREADYS; // Write Address ready (slave ready to accept write address) - input AWVALIDS; // Write Address valid - input [4:0] AWIDS; // Write Address ID - input [43:0] AWADDRS; // Write Address - input [7:0] AWLENS; // Write Burst Length - input [3:0] AWCACHES; // Write Cache type - input [1:0] AWUSERS; // Write inner & outer shareability - input [2:0] AWPROTS; // Write Protection type - -// Write Data channel signals - output WREADYS; // Write Data ready (slave ready to accept data) - input WVALIDS; // Write Data valid - input [127:0] WDATAS; // Write Data - input [15:0] WSTRBS; // Write byte-lane strobes - input WLASTS; // Write Data last transfer indicator - -// Write Response channel signals - input BREADYS; // Write Response ready (master ready to accept response) - output BVALIDS; // Write Response Valid - output [4:0] BIDS; // Write Response ID tag - output [1:0] BRESPS; // Write Response - -// Read Address channel signals - output ARREADYS; // Read Address ready (slave ready to accept read address) - input ARVALIDS; // Read Address valid - input [4:0] ARIDS; // Read Address ID - input [43:0] ARADDRS; // Read Address - input [7:0] ARLENS; // Read Burst Length - input [3:0] ARCACHES; // Read Cache type - input [1:0] ARUSERS; // Read inner & outer shareability - input [2:0] ARPROTS; // Read Protection type - -// Read Data channel signals - input RREADYS; // Read Data ready (master ready to accept data) - output RVALIDS; // Read Data valid - output [4:0] RIDS; // Read Data ID - output [127:0] RDATAS; // Read Data - output [1:0] RRESPS; // Read Data response - output RLASTS; // Read Data last transfer indicator -// END NO-ACP pins - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (CLK) -//----------------------------------------------------------------------------- -// Debug CLK interface - input [43:12] DBGROMADDR; // Debug ROM base address - input DBGROMADDRV; // Debug ROM base address valid - - output [`MAIA_CN:0] DBGACK; // Debug acknowledge - output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt - output [`MAIA_CN:0] COMMRX; // Comms channel receive - output [`MAIA_CN:0] COMMTX; // Comms channel transmit - - output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request - output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request - - input DBGL1RSTDISABLE; // L1 DCache hardware reset disable - -// PMU CLK interface - output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request - output [24:0] PMUEVENT0; // PMU Event bus -// BEGIN INCLUDE FOR CPU1 - output [24:0] PMUEVENT1; // PMU Event bus -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - output [24:0] PMUEVENT2; // PMU Event bus -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - output [24:0] PMUEVENT3; // PMU Event bus -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (ATCLK) -//----------------------------------------------------------------------------- -// ETM ATB interface and Misc signals - input ATCLKEN; // ATB Clock Enable - input [63:0] TSVALUEB; // ATB Timestamp in binary - - input ATREADYM0; // ATDATA can be accepted - input AFVALIDM0; // ATB Fifo Flush Request - output [31:0] ATDATAM0; // ATB Data - output ATVALIDM0; // ATB Data Valid - output [1:0] ATBYTESM0; // ATB Data Size - output AFREADYM0; // ATB Fifo Flush Finished - output [6:0] ATIDM0; // ATB Trace Source ID - input SYNCREQM0; // ATB External synchronization request - -// BEGIN INCLUDE FOR CPU1 - input ATREADYM1; // ATDATA can be accepted - input AFVALIDM1; // ATB Fifo Flush Request - output [31:0] ATDATAM1; // ATB Data - output ATVALIDM1; // ATB Data Valid - output [1:0] ATBYTESM1; // ATB Data Size - output AFREADYM1; // ATB Fifo Flush Finished - output [6:0] ATIDM1; // ATB Trace Source ID - input SYNCREQM1; // ATB External synchronization request -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ATREADYM2; // ATDATA can be accepted - input AFVALIDM2; // ATB Fifo Flush Request - output [31:0] ATDATAM2; // ATB Data - output ATVALIDM2; // ATB Data Valid - output [1:0] ATBYTESM2; // ATB Data Size - output AFREADYM2; // ATB Fifo Flush Finished - output [6:0] ATIDM2; // ATB Trace Source ID - input SYNCREQM2; // ATB External synchronization request -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ATREADYM3; // ATDATA can be accepted - input AFVALIDM3; // ATB Fifo Flush Request - output [31:0] ATDATAM3; // ATB Data - output ATVALIDM3; // ATB Data Valid - output [1:0] ATBYTESM3; // ATB Data Size - output AFREADYM3; // ATB Fifo Flush Finished - output [6:0] ATIDM3; // ATB Trace Source ID - input SYNCREQM3; // ATB External synchronization request -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Debug/ETM/PMU Interface (PCLK) -//----------------------------------------------------------------------------- -// Debug-APBv3 port (APB) - input PCLKDBG; // APB Clock - input PCLKENDBG; // APB Clock Enable - input nPRESETDBG; // APB Reset - input PSELDBG; // Debug bus access - input [21:2] PADDRDBG; // APB address - input PADDRDBG31; // APB address bit[31] - input PENABLEDBG; // APB transfer complete flag - input PWRITEDBG; // APB read/write indicator - input [31:0] PWDATADBG; // APB write data - output [31:0] PRDATADBG; // APB read data - output PREADYDBG; // APB slave ready, used to extend a transfer - output PSLVERRDBG; // APB slave transfer error - -// Misc interface - input [`MAIA_CN:0] EDBGRQ; // External debug request - -// PMU Snapshot interface - input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request - output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge - -// Power-related interface - input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status - output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request - -// CTI interface - input [3:0] CTICHIN; // Channel In - input [3:0] CTICHOUTACK; // Channel Out acknowledge - output [3:0] CTICHOUT; // Channel Out - output [3:0] CTICHINACK; // Channel In acknowledge - input CISBYPASS; // Channel interface sync bypass - input [3:0] CIHSBYPASS; // Channel interface H/S bypass - output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt - input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge - -//----------------------------------------------------------------------------- -// Debug Authentication Interface (CLK & PCLK) -//----------------------------------------------------------------------------- - input [`MAIA_CN:0] DBGEN; // Invasive debug enable - input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable - input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable - input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable - -//----------------------------------------------------------------------------- -// DFT Signals -//----------------------------------------------------------------------------- - input DFTSE; // Scan enable - input DFTRSTDISABLE; // Disable reset to cells during scan shift - input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr - input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 - input DFTRAMHOLD; // Holds data in RAMs - input DFTCLKBYPASS; // L2 RAM strobe clock bypass - input DFTMCPHOLD; // Disable multi-cycle RAM paths - -//----------------------------------------------------------------------------- -// MBIST Interface -//----------------------------------------------------------------------------- - input nMBISTRESET; // MBIST reset - input MBISTREQ; // MBIST mode request - -//----------------------------------------------------------------------------- -// Signals from maia -> maia_cpu_io -> maia_cpu -//----------------------------------------------------------------------------- -// Outputs to maia_cpu - output ncpuporeset_cpu0_o; - output ncorereset_cpu0_o; - - output cfgend_cpu0_o; - output cfgte_cpu0_o; - output cp15sdisable_cpu0_o; - output vinithi_cpu0_o; - output [7:0] clusteridaff1_cpu0_o; - output [7:0] clusteridaff2_cpu0_o; - output [1:0] cpuid_cpu0_o; - output aa64naa32_cpu0_o; - output [43:2] rvbaraddr_cpu0_o; - output cryptodisable_cpu0_o; - output giccdisable_cpu0_o; - - output [43:12] dbgromaddr_cpu0_o; - output dbgromaddrv_cpu0_o; - output dbgl1rstdisable_cpu0_o; - - output dbgen_cpu0_o; - output niden_cpu0_o; - output spiden_cpu0_o; - output spniden_cpu0_o; - - output [63:0] tsvalueb_cpu0_o; - - output atclken_cpu0_o; - output afvalidm_cpu0_o; - output atreadym_cpu0_o; - output syncreqm_cpu0_o; - - output dftse_cpu0_o; - output dftrstdisable_cpu0_o; - output dftcrclkdisable_cpu0_o; - output dftramhold_cpu0_o; - output nmbistreset_cpu0_o; - -// BEGIN INCLUDE FOR CPU1 - output ncpuporeset_cpu1_o; - output ncorereset_cpu1_o; - - output cfgend_cpu1_o; - output cfgte_cpu1_o; - output cp15sdisable_cpu1_o; - output vinithi_cpu1_o; - output [7:0] clusteridaff1_cpu1_o; - output [7:0] clusteridaff2_cpu1_o; - output [1:0] cpuid_cpu1_o; - output aa64naa32_cpu1_o; - output [43:2] rvbaraddr_cpu1_o; - output cryptodisable_cpu1_o; - output giccdisable_cpu1_o; - - output [43:12] dbgromaddr_cpu1_o; - output dbgromaddrv_cpu1_o; - output dbgl1rstdisable_cpu1_o; - - output dbgen_cpu1_o; - output niden_cpu1_o; - output spiden_cpu1_o; - output spniden_cpu1_o; - - output [63:0] tsvalueb_cpu1_o; - - output atclken_cpu1_o; - output afvalidm_cpu1_o; - output atreadym_cpu1_o; - output syncreqm_cpu1_o; - - output dftse_cpu1_o; - output dftrstdisable_cpu1_o; - output dftcrclkdisable_cpu1_o; - output dftramhold_cpu1_o; - output nmbistreset_cpu1_o; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output ncpuporeset_cpu2_o; - output ncorereset_cpu2_o; - - output cfgend_cpu2_o; - output cfgte_cpu2_o; - output cp15sdisable_cpu2_o; - output vinithi_cpu2_o; - output [7:0] clusteridaff1_cpu2_o; - output [7:0] clusteridaff2_cpu2_o; - output [1:0] cpuid_cpu2_o; - output aa64naa32_cpu2_o; - output [43:2] rvbaraddr_cpu2_o; - output cryptodisable_cpu2_o; - output giccdisable_cpu2_o; - - output [43:12] dbgromaddr_cpu2_o; - output dbgromaddrv_cpu2_o; - output dbgl1rstdisable_cpu2_o; - - output dbgen_cpu2_o; - output niden_cpu2_o; - output spiden_cpu2_o; - output spniden_cpu2_o; - - output [63:0] tsvalueb_cpu2_o; - - output atclken_cpu2_o; - output afvalidm_cpu2_o; - output atreadym_cpu2_o; - output syncreqm_cpu2_o; - - output dftse_cpu2_o; - output dftrstdisable_cpu2_o; - output dftcrclkdisable_cpu2_o; - output dftramhold_cpu2_o; - output nmbistreset_cpu2_o; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output ncpuporeset_cpu3_o; - output ncorereset_cpu3_o; - - output cfgend_cpu3_o; - output cfgte_cpu3_o; - output cp15sdisable_cpu3_o; - output vinithi_cpu3_o; - output [7:0] clusteridaff1_cpu3_o; - output [7:0] clusteridaff2_cpu3_o; - output [1:0] cpuid_cpu3_o; - output aa64naa32_cpu3_o; - output [43:2] rvbaraddr_cpu3_o; - output cryptodisable_cpu3_o; - output giccdisable_cpu3_o; - - output [43:12] dbgromaddr_cpu3_o; - output dbgromaddrv_cpu3_o; - output dbgl1rstdisable_cpu3_o; - - output dbgen_cpu3_o; - output niden_cpu3_o; - output spiden_cpu3_o; - output spniden_cpu3_o; - - output [63:0] tsvalueb_cpu3_o; - - output atclken_cpu3_o; - output afvalidm_cpu3_o; - output atreadym_cpu3_o; - output syncreqm_cpu3_o; - - output dftse_cpu3_o; - output dftrstdisable_cpu3_o; - output dftcrclkdisable_cpu3_o; - output dftramhold_cpu3_o; - output nmbistreset_cpu3_o; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// Signals from maia_cpu -> maia_cpu_io -> maia -//----------------------------------------------------------------------------- -// Inputs from maia_cpu - input ds_cpu0_sev_req; - input ds_cpu0_sevl_req; - input ds_cpu0_cpuectlr_smp; - - input ncommirq_cpu0_i; - input commrx_cpu0_i; - input commtx_cpu0_i; - input dbgack_cpu0_i; - input dbgrstreq_cpu0_i; - input dbgnopwrdwn_cpu0_i; - - input npmuirq_cpu0_i; - input [24:0] pmuevent_cpu0_i; - input pm_export_cpu0_i; - - input etclken_cpu0_i; - input afreadym_cpu0_i; - input [1:0] atbytesm_cpu0_i; - input [31:0] atdatam_cpu0_i; - input [6:0] atidm_cpu0_i; - input atvalidm_cpu0_i; - -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_sev_req; - input ds_cpu1_sevl_req; - input ds_cpu1_cpuectlr_smp; - - input ncommirq_cpu1_i; - input commrx_cpu1_i; - input commtx_cpu1_i; - input dbgack_cpu1_i; - input dbgrstreq_cpu1_i; - input dbgnopwrdwn_cpu1_i; - - input npmuirq_cpu1_i; - input [24:0] pmuevent_cpu1_i; - input pm_export_cpu1_i; - - input etclken_cpu1_i; - input afreadym_cpu1_i; - input [1:0] atbytesm_cpu1_i; - input [31:0] atdatam_cpu1_i; - input [6:0] atidm_cpu1_i; - input atvalidm_cpu1_i; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_sev_req; - input ds_cpu2_sevl_req; - input ds_cpu2_cpuectlr_smp; - - input ncommirq_cpu2_i; - input commrx_cpu2_i; - input commtx_cpu2_i; - input dbgack_cpu2_i; - input dbgrstreq_cpu2_i; - input dbgnopwrdwn_cpu2_i; - - input npmuirq_cpu2_i; - input [24:0] pmuevent_cpu2_i; - input pm_export_cpu2_i; - - input etclken_cpu2_i; - input afreadym_cpu2_i; - input [1:0] atbytesm_cpu2_i; - input [31:0] atdatam_cpu2_i; - input [6:0] atidm_cpu2_i; - input atvalidm_cpu2_i; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_sev_req; - input ds_cpu3_sevl_req; - input ds_cpu3_cpuectlr_smp; - - input ncommirq_cpu3_i; - input commrx_cpu3_i; - input commtx_cpu3_i; - input dbgack_cpu3_i; - input dbgrstreq_cpu3_i; - input dbgnopwrdwn_cpu3_i; - - input npmuirq_cpu3_i; - input [24:0] pmuevent_cpu3_i; - input pm_export_cpu3_i; - - input etclken_cpu3_i; - input afreadym_cpu3_i; - input [1:0] atbytesm_cpu3_i; - input [31:0] atdatam_cpu3_i; - input [6:0] atidm_cpu3_i; - input atvalidm_cpu3_i; -// END INCLUDE FOR CPU3 - -//----------------------------------------------------------------------------- -// L2 interface -//----------------------------------------------------------------------------- - output [12:0] l2_cpu0_mbist1_addr_b1; - output [3:0] l2_cpu0_mbist1_array_b1; - output [7:0] l2_cpu0_mbist1_be_b1; - output l2_cpu0_mbist1_en_b1; - output l2_cpu0_mbist1_rd_en_b1; - output l2_cpu0_mbist1_wr_en_b1; - output l2_cpu0_mbist1_all_b1; - -// BEGIN INCLUDE FOR CPU1 - output [12:0] l2_cpu1_mbist1_addr_b1; - output [3:0] l2_cpu1_mbist1_array_b1; - output [7:0] l2_cpu1_mbist1_be_b1; - output l2_cpu1_mbist1_en_b1; - output l2_cpu1_mbist1_rd_en_b1; - output l2_cpu1_mbist1_wr_en_b1; - output l2_cpu1_mbist1_all_b1; -// END INCLUDE FOR CPU1 - -// BEGIN INCLUDE FOR CPU2 - output [12:0] l2_cpu2_mbist1_addr_b1; - output [3:0] l2_cpu2_mbist1_array_b1; - output [7:0] l2_cpu2_mbist1_be_b1; - output l2_cpu2_mbist1_en_b1; - output l2_cpu2_mbist1_rd_en_b1; - output l2_cpu2_mbist1_wr_en_b1; - output l2_cpu2_mbist1_all_b1; -// END INCLUDE FOR CPU2 - -// BEGIN INCLUDE FOR CPU3 - output [12:0] l2_cpu3_mbist1_addr_b1; - output [3:0] l2_cpu3_mbist1_array_b1; - output [7:0] l2_cpu3_mbist1_be_b1; - output l2_cpu3_mbist1_en_b1; - output l2_cpu3_mbist1_rd_en_b1; - output l2_cpu3_mbist1_wr_en_b1; - output l2_cpu3_mbist1_all_b1; -// END INCLUDE FOR CPU3 - -// BEGIN L2-CPU interface - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output l2_cpu0_cfg_ecc_en; - output l2_cpu0_arb_thrshld_timeout_en; - output l2_cpu0_disable_clean_evict_opt; - output l2_cpu0_dext_err_r2; // LS external error - output l2_cpu0_dext_err_type_r2; // LS external error type - output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu0_ddata_r2; // LS read data - output l2_cpu0_barrier_done; // LS barrier complete - output l2_cpu0_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id - output l2_cpu0_rvalid; // LS read response valid - output [1:0] l2_cpu0_rstate; // LS read response state - output l2_cpu0_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu0_rbufid; // LS read response buffer id - output l2_cpu0_dvalid_r1; // LS read data valid - output l2_cpu0_dlast_r1; // LS read last indicator - output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id - output l2_cpu0_iext_err_r2; // IF external error - output l2_cpu0_iext_err_type_r2; // IF external error type - output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu0_idata_r2; // IF read data - output l2_cpu0_ivalid_r1; // IF read data valid - output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id - output l2_cpu0_ls_sync_req; // LS sync req - output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu0_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info - output l2_cpu0_if_ccb_clken_c3; // IF ccb clken - output l2_cpu0_if_ccb_req_c3; // IF ccb req - output l2_cpu0_if_sync_req; // IF sync req - output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu0_tlb_sync_req; // TLB sync req - output l2_cpu0_tlb_sync_complete; // TLB sync complete - output l2_cpu0_tbw_desc_vld; // TBW descriptor valid - output l2_cpu0_tbw_ext_err; // TBW descriptor external error - output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu0_spr_rd_data; // DS spr read data - output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size - output l2_cpu0_pf_throttle_q; // PF throttling - - output l2_cpu0_wr_ex_resp; // store exclusive response - output l2_cpu0_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu0_ic_base; // PERIPHBASE - output l2_cpu0_no_intctrl; // INTCTLR not present - - - output [33:0] l2_cpu0_pmu_events; // L2 PMU events - - input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables - input ds_cpu0_l2_spr_rd; // cpu0 spr read op - input ds_cpu0_l2_spr_wr; // cpu0 spr write op - input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address - input ds_cpu0_l2_spr_dw; // cpu0 spr access dw - input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data - - input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage - input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage - input [143:0] l2_cpu0_wr_data; - input l2_cpu0_ls_rd_haz_vld_arb_q; - input l2_cpu0_ls_wr_haz_vld_arb_q; - input l2_cpu0_dt_pmu_evt_en; // PMU enabled. - - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output l2_cpu1_cfg_ecc_en; - output l2_cpu1_arb_thrshld_timeout_en; - output l2_cpu1_disable_clean_evict_opt; - output l2_cpu1_dext_err_r2; // LS external error - output l2_cpu1_dext_err_type_r2; // LS external error type - output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu1_ddata_r2; // LS read data - output l2_cpu1_barrier_done; // LS barrier complete - output l2_cpu1_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id - output l2_cpu1_rvalid; // LS read response valid - output [1:0] l2_cpu1_rstate; // LS read response state - output l2_cpu1_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu1_rbufid; // LS read response buffer id - output l2_cpu1_dvalid_r1; // LS read data valid - output l2_cpu1_dlast_r1; // LS read last indicator - output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id - output l2_cpu1_iext_err_r2; // IF external error - output l2_cpu1_iext_err_type_r2; // IF external error type - output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu1_idata_r2; // IF read data - output l2_cpu1_ivalid_r1; // IF read data valid - output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id - output l2_cpu1_ls_sync_req; // LS sync req - output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu1_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info - output l2_cpu1_if_ccb_clken_c3; // IF ccb clken - output l2_cpu1_if_ccb_req_c3; // IF ccb req - output l2_cpu1_if_sync_req; // IF sync req - output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken - output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu1_tlb_sync_req; // TLB sync req - output l2_cpu1_tlb_sync_complete; // TLB sync complete - output l2_cpu1_tbw_desc_vld; // TBW descriptor valid - output l2_cpu1_tbw_ext_err; // TBW descriptor external error - output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu1_spr_rd_data; // DS spr read data - output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size - output l2_cpu1_pf_throttle_q; // PF throttling - - output l2_cpu1_wr_ex_resp; // store exclusive response - output l2_cpu1_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu1_ic_base; // PERIPHBASE - output l2_cpu1_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu1_pmu_events; // L2 PMU events - - input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables - input ds_cpu1_l2_spr_rd; // cpu1 spr read op - input ds_cpu1_l2_spr_wr; // cpu1 spr write op - input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address - input ds_cpu1_l2_spr_dw; // cpu1 spr access dw - input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data - - input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage - input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage - input [143:0] l2_cpu1_wr_data; - input l2_cpu1_ls_rd_haz_vld_arb_q; - input l2_cpu1_ls_wr_haz_vld_arb_q; - input l2_cpu1_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output l2_cpu2_cfg_ecc_en; - output l2_cpu2_arb_thrshld_timeout_en; - output l2_cpu2_disable_clean_evict_opt; - output l2_cpu2_dext_err_r2; // LS external error - output l2_cpu2_dext_err_type_r2; // LS external error type - output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu2_ddata_r2; // LS read data - output l2_cpu2_barrier_done; // LS barrier complete - output l2_cpu2_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id - output l2_cpu2_rvalid; // LS read response valid - output [1:0] l2_cpu2_rstate; // LS read response state - output l2_cpu2_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu2_rbufid; // LS read response buffer id - output l2_cpu2_dvalid_r1; // LS read data valid - output l2_cpu2_dlast_r1; // LS read last indicator - output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id - output l2_cpu2_iext_err_r2; // IF external error - output l2_cpu2_iext_err_type_r2; // IF external error type - output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu2_idata_r2; // IF read data - output l2_cpu2_ivalid_r1; // IF read data valid - output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id - output l2_cpu2_ls_sync_req; // LS sync req - output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu2_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info - output l2_cpu2_if_ccb_clken_c3; // IF ccb clken - output l2_cpu2_if_ccb_req_c3; // IF ccb req - output l2_cpu2_if_sync_req; // IF sync req - output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu2_tlb_sync_req; // TLB sync req - output l2_cpu2_tlb_sync_complete; // TLB sync complete - output l2_cpu2_tbw_desc_vld; // TBW descriptor valid - output l2_cpu2_tbw_ext_err; // TBW descriptor external error - output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu2_spr_rd_data; // DS spr read data - output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size - output l2_cpu2_pf_throttle_q; // PF throttling - - output l2_cpu2_wr_ex_resp; // store exclusive response - output l2_cpu2_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu2_ic_base; // PERIPHBASE - output l2_cpu2_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu2_pmu_events; // L2 PMU events - - input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables - input ds_cpu2_l2_spr_rd; // cpu2 spr read op - input ds_cpu2_l2_spr_wr; // cpu2 spr write op - input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address - input ds_cpu2_l2_spr_dw; // cpu2 spr access dw - input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data - - input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage - input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage - input [143:0] l2_cpu2_wr_data; - input l2_cpu2_ls_rd_haz_vld_arb_q; - input l2_cpu2_ls_wr_haz_vld_arb_q; - input l2_cpu2_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output l2_cpu3_cfg_ecc_en; - output l2_cpu3_arb_thrshld_timeout_en; - output l2_cpu3_disable_clean_evict_opt; - output l2_cpu3_dext_err_r2; // LS external error - output l2_cpu3_dext_err_type_r2; // LS external error type - output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error - output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error - output [129:0] l2_cpu3_ddata_r2; // LS read data - output l2_cpu3_barrier_done; // LS barrier complete - output l2_cpu3_spec_valid; // LS read speculative response valid - output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id - output l2_cpu3_rvalid; // LS read response valid - output [1:0] l2_cpu3_rstate; // LS read response state - output l2_cpu3_rexfail; // LS read response exclusive fail - output [2:0] l2_cpu3_rbufid; // LS read response buffer id - output l2_cpu3_dvalid_r1; // LS read data valid - output l2_cpu3_dlast_r1; // LS read last indicator - output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id - output l2_cpu3_iext_err_r2; // IF external error - output l2_cpu3_iext_err_type_r2; // IF external error type - output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error - output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error - output [127:0] l2_cpu3_idata_r2; // IF read data - output l2_cpu3_ivalid_r1; // IF read data valid - output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id - output l2_cpu3_ls_sync_req; // LS sync req - output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr - output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd - output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken - output l2_cpu3_ls_ccb_req_c3; // LS ccb req - output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id - output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type - output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info - output l2_cpu3_if_ccb_clken_c3; // IF ccb clken - output l2_cpu3_if_ccb_req_c3; // IF ccb req - output l2_cpu3_if_sync_req; // IF sync req - output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken - output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req - output l2_cpu3_tlb_sync_req; // TLB sync req - output l2_cpu3_tlb_sync_complete; // TLB sync complete - output l2_cpu3_tbw_desc_vld; // TBW descriptor valid - output l2_cpu3_tbw_ext_err; // TBW descriptor external error - output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type - output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error - output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data - output [63:0] l2_cpu3_spr_rd_data; // DS spr read data - output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size - output l2_cpu3_pf_throttle_q; // PF throttling - - output l2_cpu3_wr_ex_resp; // store exclusive response - output l2_cpu3_wr_ex_fail; // store exclusive failed - - output [43:18] l2_cpu3_ic_base; // PERIPHBASE - output l2_cpu3_no_intctrl; // INTCTLR not present - - output [33:0] l2_cpu3_pmu_events; // L2 PMU events - - input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables - input ds_cpu3_l2_spr_rd; // cpu3 spr read op - input ds_cpu3_l2_spr_wr; // cpu3 spr write op - input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address - input ds_cpu3_l2_spr_dw; // cpu3 spr access dw - input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data - - input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage - input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage - input [143:0] l2_cpu3_wr_data; - input l2_cpu3_ls_rd_haz_vld_arb_q; - input l2_cpu3_ls_wr_haz_vld_arb_q; - input l2_cpu3_dt_pmu_evt_en; // PMU enabled. - -//----------------------------------------------------------------------------- -// tag_pipe / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush - output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush - - output l2_cpu0_wr_data_stall; // cpu0 write data stall - - output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush - output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush - - output l2_cpu1_wr_data_stall; // cpu1 write data stall - - output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush - output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush - - output l2_cpu2_wr_data_stall; // cpu2 write data stall - - output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush - output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush - - output l2_cpu3_wr_data_stall; // cpu3 write data stall - - output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush - - output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush - - output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush - - output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush - - output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush - output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush - output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush - output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush - - output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush - output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush - output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush - output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush - - output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush - output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush - output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush - output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush - - output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush - output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush - output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush - output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush - - output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush - output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush - output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush - output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard - - output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush - output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush - output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush - output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard - - output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush - output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush - output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush - output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard - - output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush - output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush - output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush - output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard - - output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending - output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending - output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending - output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending - - output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending - output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending - output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending - output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending - - output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending - output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending - output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending - output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending - - output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending - output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending - output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending - output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending - - output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests - output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests - output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests - output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests - - output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected - output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected - output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected - output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected - -//----------------------------------------------------------------------------- -// tag_pipe -//----------------------------------------------------------------------------- - output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry - output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry - output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry - output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry - - output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry - output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry - output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry - output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry - - output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry - output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry - output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry - output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry - - output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry - output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry - output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry - output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry - - output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry - output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry - output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry - output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry - - output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry - output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry - output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry - output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry - - output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry - output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry - output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry - output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry - - output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry - output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry - output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry - output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry - - -//----------------------------------------------------------------------------- -// cpu_logic / cpu slave -//----------------------------------------------------------------------------- - output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active - output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active - - output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active - output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active - - output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active - output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active - - output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active - output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active - - -//----------------------------------------------------------------------------- -// feq / cpu slave -//----------------------------------------------------------------------------- - input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data - input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes - input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data - input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes - input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data - input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes - input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data - input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes - - output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry - output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id - output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable - output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 - output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select - output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry - output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id - output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable - output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 - output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select - output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry - output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id - output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable - output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 - output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select - output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry - output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable - output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 - output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id - output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select - -//----------------------------------------------------------------------------- -// arbitration -//----------------------------------------------------------------------------- - output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid - output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid - output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid - output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid - - output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped - output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped - output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped - output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped - - output l2_cpu0_rd_arb; // - output l2_cpu1_rd_arb; // - output l2_cpu2_rd_arb; // - output l2_cpu3_rd_arb; // - - output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid - output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid - output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid - output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid - - output l2_cpu0_wr_arb; // - output l2_cpu1_wr_arb; // - output l2_cpu2_wr_arb; // - output l2_cpu3_wr_arb; // - - output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid - output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid - output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid - output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid - - output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall - output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall - output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall - output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall - - output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating - output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating - output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating - output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating - -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup - input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request - input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type - input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes - input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes - input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size - input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way - input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed - input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive - input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv - input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared - input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 - input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid - input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm - input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address - input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass - input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request - input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way - input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid - input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid - - input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request - input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw - input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator - input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes - input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes - input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size - input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type - input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv - input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared - input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last - input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction - input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error - input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way - input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty - input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator - input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address - input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request - input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id - input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator - input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator - input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size - input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure - input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address - input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data - - input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator - - input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request - input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator - input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator - input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator - input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type - input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id - input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data - - input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp - input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id - input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer - - input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp - input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id - - input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp - input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id - - input l2_cpu0_if_sync_done_q; // cpu0 sync response - input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response - - input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id - input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id - input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id - input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup - input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request - input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type - input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes - input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes - input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size - input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way - input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed - input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive - input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv - input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared - input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 - input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 - input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid - input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm - input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address - input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass - input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request - input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way - input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid - input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid - - input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request - input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw - input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator - input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes - input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes - input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size - input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type - input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv - input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared - input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last - input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction - input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error - input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way - input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty - input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator - input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address - input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request - input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id - input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator - input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator - input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size - input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure - input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address - input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data - - input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator - - input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request - input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator - input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator - input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator - input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type - input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id - input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data - - input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp - input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id - input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer - - input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp - input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id - - input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp - input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id - - input l2_cpu1_if_sync_done_q; // cpu1 sync response - input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response - - input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id - input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id - input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id - input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup - input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request - input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type - input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes - input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes - input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size - input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way - input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed - input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive - input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv - input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared - input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 - input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 - input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid - input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm - input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address - input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass - input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request - input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way - input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid - input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid - - input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request - input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw - input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator - input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes - input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes - input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size - input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type - input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv - input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared - input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last - input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction - input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error - input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way - input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty - input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator - input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address - input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request - input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id - input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator - input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator - input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size - input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure - input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address - input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data - - input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator - - input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request - input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator - input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator - input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator - input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type - input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id - input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data - - input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp - input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id - input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer - - input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp - input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id - - input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp - input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id - - input l2_cpu2_if_sync_done_q; // cpu2 sync response - input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response - - input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id - input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id - input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id - input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup - input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request - input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator - input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type - input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes - input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes - input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size - input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way - input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed - input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive - input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv - input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared - input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 - input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 - input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid - input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm - input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address - input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass - input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request - input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way - input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid - input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid - - input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request - input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw - input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator - input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes - input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes - input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size - input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type - input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws - input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv - input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared - input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last - input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction - input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error - input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way - input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty - input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator - input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address - input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request - input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id - input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator - input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator - input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size - input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure - input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address - input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data - - input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator - - input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request - input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator - input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator - input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator - input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type - input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id - input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data - - input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp - input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id - input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer - - input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp - input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id - - input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp - input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id - - input l2_cpu3_if_sync_done_q; // cpu3 sync response - input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response - - input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id - input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id - input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id - input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id - -// END L2-CPU interface - -//------------------------------------------------------------------- -// TM interface -//------------------------------------------------------------------- -// BEGIN TIMER-CPU interface - output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> - - output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> - output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> -// END TIMER-CPU interface - -//----------------------------------------------------------------------------- -// IC interface -//----------------------------------------------------------------------------- - input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu0_raw_eae_secure; // LS S LPAE to IC - - input ds_cpu0_ic_sample_spr; - input [4:0] ds_cpu0_ic_cpsr_mode; - input ds_cpu0_ic_aa64naa32; - input ds_cpu0_ic_hcr_change; - input ds_cpu0_ic_scr_change; -// BEGIN INCLUDE FOR CPU1 - input ds_cpu1_ic_sample_spr; - input [4:0] ds_cpu1_ic_cpsr_mode; - input ds_cpu1_ic_aa64naa32; - input ds_cpu1_ic_hcr_change; - input ds_cpu1_ic_scr_change; - input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu1_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU1 -// BEGIN INCLUDE FOR CPU2 - input ds_cpu2_ic_sample_spr; - input [4:0] ds_cpu2_ic_cpsr_mode; - input ds_cpu2_ic_hcr_change; - input ds_cpu2_ic_scr_change; - input ds_cpu2_ic_aa64naa32; - input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu2_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU2 -// BEGIN INCLUDE FOR CPU3 - input ds_cpu3_ic_sample_spr; - input [4:0] ds_cpu3_ic_cpsr_mode; - input ds_cpu3_ic_hcr_change; - input ds_cpu3_ic_scr_change; - input ds_cpu3_ic_aa64naa32; - input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI - input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI - input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC - input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable - input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC - input ls_cpu3_raw_eae_secure; // LS S LPAE to IC -// END INCLUDE FOR CPU3 - - output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ - output [`MAIA_CN:0] ic_nirq; // IC physical IRQ - output [`MAIA_CN:0] ic_nsei; // IC physical SEI - output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ - output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ - output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI - output [`MAIA_CN:0] ic_p_valid; // IC is present - - output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals - output [`MAIA_CN:0] ic_hcr_change_complete; - output [`MAIA_CN:0] ic_scr_change_complete; - output [`MAIA_CN:0] ic_el_change_complete; - output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common - output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 - output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 - output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 - output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S - output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 - output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS - output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses - output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses - output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses - output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses - -//----------------------------------------------------------------------------- -// DT interface -//----------------------------------------------------------------------------- -// BEGIN DT-CPU interface -//----------------------------------------------------------------------------- -// ucpu0 -//----------------------------------------------------------------------------- - output dt_cpu0_dbif_req_pclk; // Debug Interface Req - output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu0_edbgrq_pclk; // External Debug Request - output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu0_et_oslock_gclk; // ETM OS Lock - input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu0_halt_ack_gclk; // Core Halted - input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu0_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu1 -//----------------------------------------------------------------------------- - output dt_cpu1_dbif_req_pclk; // Debug Interface Req - output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu1_edbgrq_pclk; // External Debug Request - output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu1_et_oslock_gclk; // ETM OS Lock - input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu1_halt_ack_gclk; // Core Halted - input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu1_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu2 -//----------------------------------------------------------------------------- - output dt_cpu2_dbif_req_pclk; // Debug Interface Req - output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu2_edbgrq_pclk; // External Debug Request - output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu2_et_oslock_gclk; // ETM OS Lock - input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu2_halt_ack_gclk; // Core Halted - input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu2_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK - -//----------------------------------------------------------------------------- -// ucpu3 -//----------------------------------------------------------------------------- - output dt_cpu3_dbif_req_pclk; // Debug Interface Req - output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read - output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value - output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data - output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr - output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit - output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit - output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit - output dt_cpu3_edbgrq_pclk; // External Debug Request - output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack - output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request - - input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge - output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request - - input dt_cpu3_et_oslock_gclk; // ETM OS Lock - input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock - input dt_cpu3_halt_ack_gclk; // Core Halted - input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state - input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode - input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe - input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack - input dt_cpu3_dbif_err_gclk; // Debug Interface Error - input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data - - output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu - output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu - output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu - output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu - - input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu - input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu - input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu - input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu - - output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event - output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK -// END DT-CPU interface - -//----------------------------------------------------------------------------- -// CK interface -//----------------------------------------------------------------------------- -// BEGIN CK-CPU interface - input ds_cpu0_reset_req; // Warm Reset request - input ds_cpu0_wfi_req; // WFI request - input ds_cpu0_wfe_req; // WFI request - input ds_cpu0_flush; // flush for exception rtn - input [5:0] ds_cpu0_flush_type; // flush type - input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu0_hcr_va; // virtual abort - input ds_cpu0_hcr_vi; // virtual IRQ - input ds_cpu0_hcr_vf; // virtual FIQ - input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control - output ck_cpu0_event_reg; // WFE event reg - output ck_cpu0_wfi_ack; // WFI acknowledge to DS - output ck_cpu0_wfe_ack; // WFE acknowledge to DS - output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu1_reset_req; // Warm Reset request - input ds_cpu1_wfi_req; // WFI request - input ds_cpu1_wfe_req; // WFI request - input ds_cpu1_flush; // flush for exception rtn - input [5:0] ds_cpu1_flush_type; // flush type - input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu1_hcr_va; // virtual abort - input ds_cpu1_hcr_vi; // virtual IRQ - input ds_cpu1_hcr_vf; // virtual FIQ - input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control - output ck_cpu1_event_reg; // WFE event reg - output ck_cpu1_wfi_ack; // WFI acknowledge to DS - output ck_cpu1_wfe_ack; // WFE acknowledge to DS - output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu2_reset_req; // Warm Reset request - input ds_cpu2_wfi_req; // WFI request - input ds_cpu2_wfe_req; // WFI request - input ds_cpu2_flush; // flush for exception rtn - input [5:0] ds_cpu2_flush_type; // flush type - input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu2_hcr_va; // virtual abort - input ds_cpu2_hcr_vi; // virtual IRQ - input ds_cpu2_hcr_vf; // virtual FIQ - input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control - output ck_cpu2_event_reg; // WFE event reg - output ck_cpu2_wfi_ack; // WFI acknowledge to DS - output ck_cpu2_wfe_ack; // WFE acknowledge to DS - output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ds_cpu3_reset_req; // Warm Reset request - input ds_cpu3_wfi_req; // WFI request - input ds_cpu3_wfe_req; // WFI request - input ds_cpu3_flush; // flush for exception rtn - input [5:0] ds_cpu3_flush_type; // flush type - input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI - input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI - input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI - input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI - input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI - input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI - input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE - input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE - input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE - input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE - input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE - input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE - input ds_cpu3_hcr_va; // virtual abort - input ds_cpu3_hcr_vi; // virtual IRQ - input ds_cpu3_hcr_vf; // virtual FIQ - input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control - output ck_cpu3_event_reg; // WFE event reg - output ck_cpu3_wfi_ack; // WFI acknowledge to DS - output ck_cpu3_wfe_ack; // WFE acknowledge to DS - output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable - - input ls_cpu0_clrexmon; // LS global exclusive monitor - input ls_cpu1_clrexmon; // LS global exclusive monitor - input ls_cpu2_clrexmon; // LS global exclusive monitor - input ls_cpu3_clrexmon; // LS global exclusive monitor - -// END CK-CPU interface - - output [`MAIA_CN:0] ck_gclkt; - - - - // wires - wire ck_areset_l2; - wire ck_cpu0_areset_l2cpu; - wire ck_cpu0_areset_l2dt; - wire ck_cpu0_commrx; - wire ck_cpu0_commtx; - wire ck_cpu0_crcx_clk_en_n_ic; - wire ck_cpu0_dbgnopwrdwn; - wire ck_cpu0_dbgrstreq; - wire ck_cpu0_dt_standbywfx; - wire ck_cpu0_dt_wfx_ack; - wire ck_cpu0_l2_standbywfi; - wire ck_cpu0_l2_standbywfx; - wire ck_cpu0_ncommirq; - wire ck_cpu0_npmuirq; - wire ck_cpu0_poreset_status; - wire ck_cpu0_reset1_n_l2cpu; - wire ck_cpu0_reset1_n_l2dt; - wire ck_cpu1_areset_l2cpu; - wire ck_cpu1_areset_l2dt; - wire ck_cpu1_commrx; - wire ck_cpu1_commtx; - wire ck_cpu1_crcx_clk_en_n_ic; - wire ck_cpu1_dbgnopwrdwn; - wire ck_cpu1_dbgrstreq; - wire ck_cpu1_dt_standbywfx; - wire ck_cpu1_dt_wfx_ack; - wire ck_cpu1_l2_standbywfi; - wire ck_cpu1_l2_standbywfx; - wire ck_cpu1_ncommirq; - wire ck_cpu1_npmuirq; - wire ck_cpu1_poreset_status; - wire ck_cpu1_reset1_n_l2cpu; - wire ck_cpu1_reset1_n_l2dt; - wire ck_cpu2_areset_l2cpu; - wire ck_cpu2_areset_l2dt; - wire ck_cpu2_commrx; - wire ck_cpu2_commtx; - wire ck_cpu2_crcx_clk_en_n_ic; - wire ck_cpu2_dbgnopwrdwn; - wire ck_cpu2_dbgrstreq; - wire ck_cpu2_dt_standbywfx; - wire ck_cpu2_dt_wfx_ack; - wire ck_cpu2_l2_standbywfi; - wire ck_cpu2_l2_standbywfx; - wire ck_cpu2_ncommirq; - wire ck_cpu2_npmuirq; - wire ck_cpu2_poreset_status; - wire ck_cpu2_reset1_n_l2cpu; - wire ck_cpu2_reset1_n_l2dt; - wire ck_cpu3_areset_l2cpu; - wire ck_cpu3_areset_l2dt; - wire ck_cpu3_commrx; - wire ck_cpu3_commtx; - wire ck_cpu3_crcx_clk_en_n_ic; - wire ck_cpu3_dbgnopwrdwn; - wire ck_cpu3_dbgrstreq; - wire ck_cpu3_dt_standbywfx; - wire ck_cpu3_dt_wfx_ack; - wire ck_cpu3_l2_standbywfi; - wire ck_cpu3_l2_standbywfx; - wire ck_cpu3_ncommirq; - wire ck_cpu3_npmuirq; - wire ck_cpu3_poreset_status; - wire ck_cpu3_reset1_n_l2cpu; - wire ck_cpu3_reset1_n_l2dt; - wire ck_dt_cpu0_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; - wire ck_dt_cpu0_et_oslock_gclk; - wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu0_os_double_lock_gclk; - wire ck_dt_cpu0_pmusnapshot_ack_gclk; - wire ck_dt_cpu0_wfx_dbg_req_gclk; - wire ck_dt_cpu1_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; - wire ck_dt_cpu1_et_oslock_gclk; - wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu1_os_double_lock_gclk; - wire ck_dt_cpu1_pmusnapshot_ack_gclk; - wire ck_dt_cpu1_wfx_dbg_req_gclk; - wire ck_dt_cpu2_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; - wire ck_dt_cpu2_et_oslock_gclk; - wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu2_os_double_lock_gclk; - wire ck_dt_cpu2_pmusnapshot_ack_gclk; - wire ck_dt_cpu2_wfx_dbg_req_gclk; - wire ck_dt_cpu3_coredbg_in_reset_gclk; - wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; - wire ck_dt_cpu3_et_oslock_gclk; - wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; - wire ck_dt_cpu3_os_double_lock_gclk; - wire ck_dt_cpu3_pmusnapshot_ack_gclk; - wire ck_dt_cpu3_wfx_dbg_req_gclk; - wire ck_gclkb0; - wire ck_gclkb1; - wire ck_gclkfr; - wire ck_gclkl2; - wire ck_gclktl2; - wire ck_l2_ace_inactive; - wire ck_l2_acp_inactive; - wire ck_l2_logic_clk_en; - wire ck_l2_sky_link_deactivate; - wire ck_l2_tbnk0_clk_en; - wire ck_l2_tbnk1_clk_en; - wire ck_reset1_n_l2; - wire clrexmon_c1; - wire ds_cpu0_ic_aa64naa32_i; - wire [4:0] ds_cpu0_ic_cpsr_mode_i; - wire ds_cpu0_ic_hcr_change_i; - wire ds_cpu0_ic_sample_spr_i; - wire ds_cpu0_ic_scr_change_i; - wire ds_cpu1_ic_aa64naa32_i; - wire [4:0] ds_cpu1_ic_cpsr_mode_i; - wire ds_cpu1_ic_hcr_change_i; - wire ds_cpu1_ic_sample_spr_i; - wire ds_cpu1_ic_scr_change_i; - wire ds_cpu2_ic_aa64naa32_i; - wire [4:0] ds_cpu2_ic_cpsr_mode_i; - wire ds_cpu2_ic_hcr_change_i; - wire ds_cpu2_ic_sample_spr_i; - wire ds_cpu2_ic_scr_change_i; - wire ds_cpu3_ic_aa64naa32_i; - wire [4:0] ds_cpu3_ic_cpsr_mode_i; - wire ds_cpu3_ic_hcr_change_i; - wire ds_cpu3_ic_sample_spr_i; - wire ds_cpu3_ic_scr_change_i; - wire dt_cpu0_apb_active_pclk; - wire dt_cpu0_poreset_status_ack_pclk; - wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu0_wfx_wakeup_pclk; - wire dt_cpu1_apb_active_pclk; - wire dt_cpu1_poreset_status_ack_pclk; - wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu1_wfx_wakeup_pclk; - wire dt_cpu2_apb_active_pclk; - wire dt_cpu2_poreset_status_ack_pclk; - wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu2_wfx_wakeup_pclk; - wire dt_cpu3_apb_active_pclk; - wire dt_cpu3_poreset_status_ack_pclk; - wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; - wire dt_cpu3_wfx_wakeup_pclk; - wire eventi_sev; - wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; - wire ic_cpu0_l2_dsb_block; - wire [63:0] ic_cpu0_spr_rd_data; - wire ic_cpu1_l2_dsb_block; - wire [63:0] ic_cpu1_spr_rd_data; - wire ic_cpu2_l2_dsb_block; - wire [63:0] ic_cpu2_spr_rd_data; - wire ic_cpu3_l2_dsb_block; - wire [63:0] ic_cpu3_spr_rd_data; - wire [`MAIA_CN:0] ic_el_change_complete_o; - wire [`MAIA_CN:0] ic_hcr_change_complete_o; - wire [`MAIA_CN:0] ic_ich_el2_tall0_o; - wire [`MAIA_CN:0] ic_ich_el2_tall1_o; - wire [`MAIA_CN:0] ic_ich_el2_tc_o; - wire [`MAIA_CN:0] ic_nfiq_o; - wire [`MAIA_CN:0] ic_nirq_o; - wire [`MAIA_CN:0] ic_nsei_o; - wire [`MAIA_CN:0] ic_nvfiq_o; - wire [`MAIA_CN:0] ic_nvirq_o; - wire [`MAIA_CN:0] ic_nvsei_o; - wire [31:0] ic_p_rdata; - wire ic_p_rdata_valid; - wire ic_p_ready; - wire [`MAIA_CN:0] ic_sample_spr_o; - wire [`MAIA_CN:0] ic_scr_change_complete_o; - wire [`MAIA_CN:0] ic_sra_el1ns_en_o; - wire [`MAIA_CN:0] ic_sra_el1s_en_o; - wire [`MAIA_CN:0] ic_sra_el2_en_o; - wire [`MAIA_CN:0] ic_sra_el3_en_o; - wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; - wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; - wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; - wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; - wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; - wire l2_acp_rd_haz_vld_l2_dly_q; - wire l2_acp_wr_haz_vld_l2_dly_q; - wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; - wire l2_actlr_disable_setway_opt; - wire l2_actlr_ncpu_rcg_enable; - wire l2_actlr_plru_dynamic; - wire l2_actlr_plru_en; - wire [1:0] l2_actlr_plru_mode; - wire l2_actlr_writeunique_disable; - wire l2_cfg_broadcastinner; - wire l2_cfg_broadcastouter; - wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu0_snp_active; - wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu0_wr_decerr_q; - wire l2_cpu0_wr_slverr_q; - wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu1_snp_active; - wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu1_wr_decerr_q; - wire l2_cpu1_wr_slverr_q; - wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu2_snp_active; - wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu2_wr_decerr_q; - wire l2_cpu2_wr_slverr_q; - wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; - wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; - wire l2_cpu3_snp_active; - wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; - wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; - wire l2_cpu3_wr_decerr_q; - wire l2_cpu3_wr_slverr_q; - wire l2_ctlr_x1_wr_q; - wire [9:0] l2_ctlr_x2_ns; - wire l2_idle; - wire [`MAIA_CN:0] l2_mbist1_en_b1; - wire [16:0] l2_mbist2_tbnk0_addr_b1; - wire l2_mbist2_tbnk0_all_b1; - wire [2:0] l2_mbist2_tbnk0_array_b1; - wire [17:0] l2_mbist2_tbnk0_be_b1; - wire l2_mbist2_tbnk0_en_b1; - wire [143:0] l2_mbist2_tbnk0_indata_b1; - wire [143:0] l2_mbist2_tbnk0_outdata_b3; - wire l2_mbist2_tbnk0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; - wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; - wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; - wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; - wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk0_snp3_sel_b1; - wire l2_mbist2_tbnk0_wr_en_b1; - wire [16:0] l2_mbist2_tbnk1_addr_b1; - wire l2_mbist2_tbnk1_all_b1; - wire [2:0] l2_mbist2_tbnk1_array_b1; - wire [17:0] l2_mbist2_tbnk1_be_b1; - wire l2_mbist2_tbnk1_en_b1; - wire [143:0] l2_mbist2_tbnk1_indata_b1; - wire [143:0] l2_mbist2_tbnk1_outdata_b3; - wire l2_mbist2_tbnk1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; - wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp0_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; - wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp1_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; - wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp2_sel_b1; - wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; - wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; - wire l2_mbist2_tbnk1_snp3_sel_b1; - wire l2_mbist2_tbnk1_wr_en_b1; - wire l2_no_ram_acc_nxt_cycle; - wire [13:0] l2_p_addr; - wire [1:0] l2_p_cpu; - wire l2_p_nsecure; - wire [2:0] l2_p_sel; - wire [31:0] l2_p_wdata; - wire l2_p_write; - wire l2_reset3; - wire l2_rstdisable_x1_q; - wire l2_sky_link_stopped; - wire l2_tbnk0_addr44_l3_q; - wire [44:0] l2_tbnk0_addr_l1; - wire [5:2] l2_tbnk0_addr_l6; - wire l2_tbnk0_all_tag_incl_active_l3; - wire l2_tbnk0_asq_cmp_evict_l3_q; - wire l2_tbnk0_asq_full_flsh; - wire l2_tbnk0_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk0_cache_attr_l1; - wire l2_tbnk0_cfg_ecc_en; - wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu0_hit_l4; - wire l2_tbnk0_cpu0_l2_inv_l4_dly2; - wire l2_tbnk0_cpu0_l2hit_e_l4; - wire l2_tbnk0_cpu0_l2hit_s_l4; - wire l2_tbnk0_cpu0_peq_full_q; - wire l2_tbnk0_cpu0_peq_hit_q; - wire l2_tbnk0_cpu0_peq_self_evict_l3_q; - wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu0_rd_access_l4_dly; - wire l2_tbnk0_cpu0_self_evict_l4_dly_q; - wire l2_tbnk0_cpu0_single_ecc_err_l7_q; - wire l2_tbnk0_cpu0_snp_hit_e_l3; - wire l2_tbnk0_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; - wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu0_vld_nxt_l5; - wire l2_tbnk0_cpu0_wr_access_l4_dly; - wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu1_hit_l4; - wire l2_tbnk0_cpu1_l2_inv_l4_dly2; - wire l2_tbnk0_cpu1_l2hit_e_l4; - wire l2_tbnk0_cpu1_l2hit_s_l4; - wire l2_tbnk0_cpu1_peq_full_q; - wire l2_tbnk0_cpu1_peq_hit_q; - wire l2_tbnk0_cpu1_peq_self_evict_l3_q; - wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu1_rd_access_l4_dly; - wire l2_tbnk0_cpu1_self_evict_l4_dly_q; - wire l2_tbnk0_cpu1_single_ecc_err_l7_q; - wire l2_tbnk0_cpu1_snp_hit_e_l3; - wire l2_tbnk0_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; - wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu1_vld_nxt_l5; - wire l2_tbnk0_cpu1_wr_access_l4_dly; - wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu2_hit_l4; - wire l2_tbnk0_cpu2_l2_inv_l4_dly2; - wire l2_tbnk0_cpu2_l2hit_e_l4; - wire l2_tbnk0_cpu2_l2hit_s_l4; - wire l2_tbnk0_cpu2_peq_full_q; - wire l2_tbnk0_cpu2_peq_hit_q; - wire l2_tbnk0_cpu2_peq_self_evict_l3_q; - wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu2_rd_access_l4_dly; - wire l2_tbnk0_cpu2_self_evict_l4_dly_q; - wire l2_tbnk0_cpu2_single_ecc_err_l7_q; - wire l2_tbnk0_cpu2_snp_hit_e_l3; - wire l2_tbnk0_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; - wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu2_vld_nxt_l5; - wire l2_tbnk0_cpu2_wr_access_l4_dly; - wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk0_cpu3_hit_l4; - wire l2_tbnk0_cpu3_l2_inv_l4_dly2; - wire l2_tbnk0_cpu3_l2hit_e_l4; - wire l2_tbnk0_cpu3_l2hit_s_l4; - wire l2_tbnk0_cpu3_peq_full_q; - wire l2_tbnk0_cpu3_peq_hit_q; - wire l2_tbnk0_cpu3_peq_self_evict_l3_q; - wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk0_cpu3_rd_access_l4_dly; - wire l2_tbnk0_cpu3_self_evict_l4_dly_q; - wire l2_tbnk0_cpu3_single_ecc_err_l7_q; - wire l2_tbnk0_cpu3_snp_hit_e_l3; - wire l2_tbnk0_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; - wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk0_cpu3_vld_nxt_l5; - wire l2_tbnk0_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; - wire l2_tbnk0_crit_qw_nxt_l5; - wire [143:0] l2_tbnk0_data_corrected_l7_q; - wire [127:0] l2_tbnk0_data_l6; - wire l2_tbnk0_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; - wire l2_tbnk0_dirty_l1; - wire l2_tbnk0_dirty_l3_q; - wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk0_double_ecc_err_l7_q; - wire l2_tbnk0_early_rvalid_l4_q; - wire l2_tbnk0_ecc_fixup_blk_arb; - wire l2_tbnk0_ecc_fixup_inprog_dly_q; - wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; - wire l2_tbnk0_evict_special_hazard_l3_q; - wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk0_excl_l1; - wire l2_tbnk0_excl_l4_q; - wire [44:6] l2_tbnk0_feq_addr_upd; - wire l2_tbnk0_feq_alloc_failed_l4; - wire l2_tbnk0_feq_axi_wr_vld_not_popped; - wire l2_tbnk0_feq_clr_l4; - wire [15:0] l2_tbnk0_feq_frc_incl_l3a; - wire l2_tbnk0_feq_kill_l3; - wire [4:0] l2_tbnk0_feq_last_id_q; - wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk0_feq_tbnk_id_update_or_l3; - wire l2_tbnk0_full_miss_l4_q; - wire l2_tbnk0_hit_l4; - wire l2_tbnk0_hit_l7_q; - wire [3:0] l2_tbnk0_hit_way_l4_q; - wire [9:0] l2_tbnk0_id_l1; - wire [9:0] l2_tbnk0_id_l6_q; - wire [9:0] l2_tbnk0_id_nxt_l5; - wire l2_tbnk0_idle; - wire l2_tbnk0_init_req_l1; - wire l2_tbnk0_kill_l2; - wire l2_tbnk0_l2bb_fake_wr_l1; - wire l2_tbnk0_l2bb_wr_l1; - wire l2_tbnk0_l2hit_e_l4; - wire l2_tbnk0_l2hit_s_l4; - wire l2_tbnk0_l2v_s_q; - wire l2_tbnk0_l2v_vld_q; - wire l2_tbnk0_last_qw_l1; - wire l2_tbnk0_last_qw_l6_q; - wire l2_tbnk0_last_qw_nxt_l5; - wire [2:0] l2_tbnk0_lock_l1; - wire [2:0] l2_tbnk0_lock_l4; - wire [32:0] l2_tbnk0_merrsr_data; - wire [9:0] l2_tbnk0_page_attr_l1; - wire l2_tbnk0_partial_dw_wr_l1; - wire l2_tbnk0_pf_cnt_dec_l4_dly; - wire l2_tbnk0_pf_hazard_l3; - wire l2_tbnk0_pf_req_sel_for_fwd_l4; - wire l2_tbnk0_prfm_l1; - wire l2_tbnk0_prfm_nxt_l5; - wire [3:0] l2_tbnk0_prot_l1; - wire [3:0] l2_tbnk0_prot_l4_q; - wire [1:0] l2_tbnk0_qw_cnt_l1; - wire [1:0] l2_tbnk0_qw_cnt_l3_q; - wire l2_tbnk0_raw_hit_l4_q; - wire [2:0] l2_tbnk0_rbufid_nxt_l5; - wire l2_tbnk0_rd_en_nxt_l5; - wire l2_tbnk0_rd_fail_hazchk_feq_l3; - wire l2_tbnk0_rwvic_axi_read_err_l1; - wire l2_tbnk0_rwvic_axi_read_err_l3_q; - wire l2_tbnk0_rwvic_ccb_dirty_l6_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; - wire l2_tbnk0_rwvic_cmo_clean_l1; - wire l2_tbnk0_rwvic_cmo_inv_l1; - wire l2_tbnk0_rwvic_cmo_inv_l7_q; - wire l2_tbnk0_rwvic_cmo_l7_q; - wire l2_tbnk0_rwvic_cmo_pou_l1; - wire l2_tbnk0_rwvic_cmo_pou_l6_q; - wire l2_tbnk0_rwvic_cmo_setway_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; - wire l2_tbnk0_rwvic_ddi_l6_q; - wire l2_tbnk0_rwvic_feq_cmp_l3_q; - wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk0_rwvic_l2hit_e_l1; - wire l2_tbnk0_rwvic_l2hit_e_l3_q; - wire l2_tbnk0_rwvic_l2hit_e_l7_q; - wire l2_tbnk0_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk0_rwvic_l2v_vld_l6_q; - wire l2_tbnk0_rwvic_mesi_sh_l1; - wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk0_rwvic_owner_l1; - wire [2:0] l2_tbnk0_rwvic_owner_l7_q; - wire l2_tbnk0_rwvic_rd_type_l6_q; - wire l2_tbnk0_rwvic_snp_clr_dirty_l1; - wire l2_tbnk0_rwvic_snp_inv_l1; - wire l2_tbnk0_rwvic_snp_l1; - wire l2_tbnk0_rwvic_snp_l3_q; - wire l2_tbnk0_rwvic_snp_l6_q; - wire l2_tbnk0_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk0_rwvic_type_l1; - wire l2_tbnk0_rwvic_wa_l1; - wire l2_tbnk0_rwvic_wa_l6_q; - wire [13:0] l2_tbnk0_sel_l1; - wire [2:0] l2_tbnk0_size_l1; - wire [2:0] l2_tbnk0_size_l4_q; - wire l2_tbnk0_snp_byp_peq_haz_pending_q; - wire l2_tbnk0_snp_dvm_cmpl_l1; - wire l2_tbnk0_snp_hit_e_l4_q; - wire l2_tbnk0_snp_hit_feq_evict_l4_dly; - wire l2_tbnk0_snp_hit_s_l4_q; - wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk0_special_evict_hazard_l3; - wire l2_tbnk0_special_hazard_l3_q; - wire l2_tbnk0_sync_l1; - wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk0_tag_ecc_err_cpu0_l4; - wire l2_tbnk0_tag_ecc_err_cpu1_l4; - wire l2_tbnk0_tag_ecc_err_cpu2_l4; - wire l2_tbnk0_tag_ecc_err_cpu3_l4; - wire l2_tbnk0_tag_ecc_err_l4; - wire [6:0] l2_tbnk0_type_l1; - wire [1:0] l2_tbnk0_ulen_l1; - wire [1:0] l2_tbnk0_ulen_l4_q; - wire l2_tbnk0_vld_init_l6_q; - wire l2_tbnk0_vld_l6_q; - wire l2_tbnk0_way_l1; - wire l2_tbnk0_way_l4_q; - wire l2_tbnk0_way_nxt_l3a; - wire [143:0] l2_tbnk0_wr_data_l3; - wire [127:0] l2_tbnk0_wr_data_l3a_q; - wire l2_tbnk0_wr_data_l4_en; - wire l2_tbnk0_wr_err_l1; - wire l2_tbnk0_wr_fail_feq_full_l3; - wire l2_tbnk0_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk0_wr_non_crit_id_l1; - wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; - wire l2_tbnk1_addr44_l3_q; - wire [44:0] l2_tbnk1_addr_l1; - wire [5:2] l2_tbnk1_addr_l6; - wire l2_tbnk1_all_tag_incl_active_l3; - wire l2_tbnk1_asq_cmp_evict_l3_q; - wire l2_tbnk1_asq_full_flsh; - wire l2_tbnk1_asq_nc_so_dev_limit; - wire [2:0] l2_tbnk1_cache_attr_l1; - wire l2_tbnk1_cfg_ecc_en; - wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; - wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu0_hit_l4; - wire l2_tbnk1_cpu0_l2_inv_l4_dly2; - wire l2_tbnk1_cpu0_l2hit_e_l4; - wire l2_tbnk1_cpu0_l2hit_s_l4; - wire l2_tbnk1_cpu0_peq_full_q; - wire l2_tbnk1_cpu0_peq_hit_q; - wire l2_tbnk1_cpu0_peq_self_evict_l3_q; - wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu0_rd_access_l4_dly; - wire l2_tbnk1_cpu0_self_evict_l4_dly_q; - wire l2_tbnk1_cpu0_single_ecc_err_l7_q; - wire l2_tbnk1_cpu0_snp_hit_e_l3; - wire l2_tbnk1_cpu0_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; - wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu0_vld_nxt_l5; - wire l2_tbnk1_cpu0_wr_access_l4_dly; - wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu1_hit_l4; - wire l2_tbnk1_cpu1_l2_inv_l4_dly2; - wire l2_tbnk1_cpu1_l2hit_e_l4; - wire l2_tbnk1_cpu1_l2hit_s_l4; - wire l2_tbnk1_cpu1_peq_full_q; - wire l2_tbnk1_cpu1_peq_hit_q; - wire l2_tbnk1_cpu1_peq_self_evict_l3_q; - wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu1_rd_access_l4_dly; - wire l2_tbnk1_cpu1_self_evict_l4_dly_q; - wire l2_tbnk1_cpu1_single_ecc_err_l7_q; - wire l2_tbnk1_cpu1_snp_hit_e_l3; - wire l2_tbnk1_cpu1_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; - wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu1_vld_nxt_l5; - wire l2_tbnk1_cpu1_wr_access_l4_dly; - wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu2_hit_l4; - wire l2_tbnk1_cpu2_l2_inv_l4_dly2; - wire l2_tbnk1_cpu2_l2hit_e_l4; - wire l2_tbnk1_cpu2_l2hit_s_l4; - wire l2_tbnk1_cpu2_peq_full_q; - wire l2_tbnk1_cpu2_peq_hit_q; - wire l2_tbnk1_cpu2_peq_self_evict_l3_q; - wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu2_rd_access_l4_dly; - wire l2_tbnk1_cpu2_self_evict_l4_dly_q; - wire l2_tbnk1_cpu2_single_ecc_err_l7_q; - wire l2_tbnk1_cpu2_snp_hit_e_l3; - wire l2_tbnk1_cpu2_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; - wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu2_vld_nxt_l5; - wire l2_tbnk1_cpu2_wr_access_l4_dly; - wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; - wire l2_tbnk1_cpu3_hit_l4; - wire l2_tbnk1_cpu3_l2_inv_l4_dly2; - wire l2_tbnk1_cpu3_l2hit_e_l4; - wire l2_tbnk1_cpu3_l2hit_s_l4; - wire l2_tbnk1_cpu3_peq_full_q; - wire l2_tbnk1_cpu3_peq_hit_q; - wire l2_tbnk1_cpu3_peq_self_evict_l3_q; - wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; - wire l2_tbnk1_cpu3_rd_access_l4_dly; - wire l2_tbnk1_cpu3_self_evict_l4_dly_q; - wire l2_tbnk1_cpu3_single_ecc_err_l7_q; - wire l2_tbnk1_cpu3_snp_hit_e_l3; - wire l2_tbnk1_cpu3_snp_hit_s_l3; - wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; - wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; - wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; - wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; - wire l2_tbnk1_cpu3_vld_nxt_l5; - wire l2_tbnk1_cpu3_wr_access_l4_dly; - wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; - wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; - wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; - wire l2_tbnk1_crit_qw_nxt_l5; - wire [143:0] l2_tbnk1_data_corrected_l7_q; - wire [127:0] l2_tbnk1_data_l6; - wire l2_tbnk1_dbg_ram_acc_l5a; - wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; - wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; - wire l2_tbnk1_dirty_l1; - wire l2_tbnk1_dirty_l3_q; - wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; - wire l2_tbnk1_double_ecc_err_l7_q; - wire l2_tbnk1_early_rvalid_l4_q; - wire l2_tbnk1_ecc_fixup_blk_arb; - wire l2_tbnk1_ecc_fixup_inprog_dly_q; - wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; - wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; - wire l2_tbnk1_evict_special_hazard_l3_q; - wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; - wire l2_tbnk1_excl_l1; - wire l2_tbnk1_excl_l4_q; - wire [44:6] l2_tbnk1_feq_addr_upd; - wire l2_tbnk1_feq_alloc_failed_l4; - wire l2_tbnk1_feq_axi_wr_vld_not_popped; - wire l2_tbnk1_feq_clr_l4; - wire [15:0] l2_tbnk1_feq_frc_incl_l3a; - wire l2_tbnk1_feq_kill_l3; - wire [4:0] l2_tbnk1_feq_last_id_q; - wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; - wire l2_tbnk1_feq_tbnk_id_update_or_l3; - wire l2_tbnk1_full_miss_l4_q; - wire l2_tbnk1_hit_l4; - wire l2_tbnk1_hit_l7_q; - wire [3:0] l2_tbnk1_hit_way_l4_q; - wire [9:0] l2_tbnk1_id_l1; - wire [9:0] l2_tbnk1_id_l6_q; - wire [9:0] l2_tbnk1_id_nxt_l5; - wire l2_tbnk1_idle; - wire l2_tbnk1_init_req_l1; - wire l2_tbnk1_kill_l2; - wire l2_tbnk1_l2bb_fake_wr_l1; - wire l2_tbnk1_l2bb_wr_l1; - wire l2_tbnk1_l2hit_e_l4; - wire l2_tbnk1_l2hit_s_l4; - wire l2_tbnk1_l2v_s_q; - wire l2_tbnk1_l2v_vld_q; - wire l2_tbnk1_last_qw_l1; - wire l2_tbnk1_last_qw_l6_q; - wire l2_tbnk1_last_qw_nxt_l5; - wire [2:0] l2_tbnk1_lock_l1; - wire [2:0] l2_tbnk1_lock_l4; - wire [32:0] l2_tbnk1_merrsr_data; - wire [9:0] l2_tbnk1_page_attr_l1; - wire l2_tbnk1_partial_dw_wr_l1; - wire l2_tbnk1_pf_cnt_dec_l4_dly; - wire l2_tbnk1_pf_hazard_l3; - wire l2_tbnk1_pf_req_sel_for_fwd_l4; - wire l2_tbnk1_prfm_l1; - wire l2_tbnk1_prfm_nxt_l5; - wire [3:0] l2_tbnk1_prot_l1; - wire [3:0] l2_tbnk1_prot_l4_q; - wire [1:0] l2_tbnk1_qw_cnt_l1; - wire [1:0] l2_tbnk1_qw_cnt_l3_q; - wire l2_tbnk1_raw_hit_l4_q; - wire [2:0] l2_tbnk1_rbufid_nxt_l5; - wire l2_tbnk1_rd_en_nxt_l5; - wire l2_tbnk1_rd_fail_hazchk_feq_l3; - wire l2_tbnk1_rwvic_axi_read_err_l1; - wire l2_tbnk1_rwvic_axi_read_err_l3_q; - wire l2_tbnk1_rwvic_ccb_dirty_l6_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; - wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; - wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; - wire l2_tbnk1_rwvic_cmo_clean_l1; - wire l2_tbnk1_rwvic_cmo_inv_l1; - wire l2_tbnk1_rwvic_cmo_inv_l7_q; - wire l2_tbnk1_rwvic_cmo_l7_q; - wire l2_tbnk1_rwvic_cmo_pou_l1; - wire l2_tbnk1_rwvic_cmo_pou_l6_q; - wire l2_tbnk1_rwvic_cmo_setway_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; - wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; - wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; - wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; - wire l2_tbnk1_rwvic_ddi_l6_q; - wire l2_tbnk1_rwvic_feq_cmp_l3_q; - wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; - wire l2_tbnk1_rwvic_l2hit_e_l1; - wire l2_tbnk1_rwvic_l2hit_e_l3_q; - wire l2_tbnk1_rwvic_l2hit_e_l7_q; - wire l2_tbnk1_rwvic_l2v_dirty_l7_q; - wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; - wire l2_tbnk1_rwvic_l2v_vld_l6_q; - wire l2_tbnk1_rwvic_mesi_sh_l1; - wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; - wire [2:0] l2_tbnk1_rwvic_owner_l1; - wire [2:0] l2_tbnk1_rwvic_owner_l7_q; - wire l2_tbnk1_rwvic_rd_type_l6_q; - wire l2_tbnk1_rwvic_snp_clr_dirty_l1; - wire l2_tbnk1_rwvic_snp_inv_l1; - wire l2_tbnk1_rwvic_snp_l1; - wire l2_tbnk1_rwvic_snp_l3_q; - wire l2_tbnk1_rwvic_snp_l6_q; - wire l2_tbnk1_rwvic_tag_wr_l0; - wire [3:0] l2_tbnk1_rwvic_type_l1; - wire l2_tbnk1_rwvic_wa_l1; - wire l2_tbnk1_rwvic_wa_l6_q; - wire [13:0] l2_tbnk1_sel_l1; - wire [2:0] l2_tbnk1_size_l1; - wire [2:0] l2_tbnk1_size_l4_q; - wire l2_tbnk1_snp_byp_peq_haz_pending_q; - wire l2_tbnk1_snp_dvm_cmpl_l1; - wire l2_tbnk1_snp_hit_e_l4_q; - wire l2_tbnk1_snp_hit_feq_evict_l4_dly; - wire l2_tbnk1_snp_hit_s_l4_q; - wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; - wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; - wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; - wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; - wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; - wire l2_tbnk1_special_evict_hazard_l3; - wire l2_tbnk1_special_hazard_l3_q; - wire l2_tbnk1_sync_l1; - wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; - wire l2_tbnk1_tag_ecc_err_cpu0_l4; - wire l2_tbnk1_tag_ecc_err_cpu1_l4; - wire l2_tbnk1_tag_ecc_err_cpu2_l4; - wire l2_tbnk1_tag_ecc_err_cpu3_l4; - wire l2_tbnk1_tag_ecc_err_l4; - wire [6:0] l2_tbnk1_type_l1; - wire [1:0] l2_tbnk1_ulen_l1; - wire [1:0] l2_tbnk1_ulen_l4_q; - wire l2_tbnk1_vld_init_l6_q; - wire l2_tbnk1_vld_l6_q; - wire l2_tbnk1_way_l1; - wire l2_tbnk1_way_l4_q; - wire l2_tbnk1_way_nxt_l3a; - wire [143:0] l2_tbnk1_wr_data_l3; - wire [127:0] l2_tbnk1_wr_data_l3a_q; - wire l2_tbnk1_wr_data_l4_en; - wire l2_tbnk1_wr_err_l1; - wire l2_tbnk1_wr_fail_feq_full_l3; - wire l2_tbnk1_wr_fail_hazchk_feq_l3; - wire [11:0] l2_tbnk1_wr_non_crit_id_l1; - wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; - wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; - wire l2_tbnk_hwrst_done_x2; - wire [13:0] l2_tbnk_hwrst_idx_x1_q; - wire [8:0] tm_cntpct_q; - wire tm_cpu0_event_sev; - wire [63:0] tm_cpu0_spr_rd_data; - wire tm_cpu1_event_sev; - wire [63:0] tm_cpu1_spr_rd_data; - wire tm_cpu2_event_sev; - wire [63:0] tm_cpu2_spr_rd_data; - wire tm_cpu3_event_sev; - wire [63:0] tm_cpu3_spr_rd_data; - wire [63:0] tm_tval_cpu0_spr_rd_data; - wire [63:0] tm_tval_cpu1_spr_rd_data; - wire [63:0] tm_tval_cpu2_spr_rd_data; - wire [63:0] tm_tval_cpu3_spr_rd_data; - - maia_timer utm( // outputs - .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), - .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), - .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), - .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), - .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), - .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), - .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), - .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), - .tm_cpu3_event_sev (tm_cpu3_event_sev), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), - - // inputs - .CNTCLKEN (CNTCLKEN), - .CNTVALUEB (CNTVALUEB[63:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .eventi_sev (eventi_sev), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) - ); // utm - - maia_l2_logic_s ul2_logic( // outputs - .ARREADYS (ARREADYS), - .AWREADYS (AWREADYS), - .BIDS (BIDS[4:0]), - .BRESPS (BRESPS[1:0]), - .BVALIDS (BVALIDS), - .L2FLUSHDONE (L2FLUSHDONE), - .L2QACCEPTn (L2QACCEPTn), - .L2QACTIVE (L2QACTIVE), - .L2QDENY (L2QDENY), - .RDATAS (RDATAS[127:0]), - .REQMEMATTR (REQMEMATTR[7:0]), - .RIDS (RIDS[4:0]), - .RLASTS (RLASTS), - .RRESPS (RRESPS[1:0]), - .RVALIDS (RVALIDS), - .RXDATLCRDV (RXDATLCRDV), - .RXLINKACTIVEACK (RXLINKACTIVEACK), - .RXRSPLCRDV (RXRSPLCRDV), - .RXSNPLCRDV (RXSNPLCRDV), - .TXDATFLIT (TXDATFLIT[193:0]), - .TXDATFLITPEND (TXDATFLITPEND), - .TXDATFLITV (TXDATFLITV), - .TXLINKACTIVEREQ (TXLINKACTIVEREQ), - .TXREQFLIT (TXREQFLIT[99:0]), - .TXREQFLITPEND (TXREQFLITPEND), - .TXREQFLITV (TXREQFLITV), - .TXRSPFLIT (TXRSPFLIT[44:0]), - .TXRSPFLITPEND (TXRSPFLITPEND), - .TXRSPFLITV (TXRSPFLITV), - .TXSACTIVE (TXSACTIVE), - .WREADYS (WREADYS), - .ck_areset_l2 (ck_areset_l2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), - .l2_cpu0_barrier_done (l2_cpu0_barrier_done), - .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), - .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), - .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), - .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), - .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), - .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), - .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), - .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), - .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), - .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), - .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), - .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), - .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), - .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), - .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), - .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), - .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), - .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), - .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), - .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), - .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), - .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), - .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), - .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), - .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), - .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), - .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), - .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), - .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), - .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), - .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), - .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), - .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), - .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), - .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), - .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), - .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), - .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), - .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), - .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), - .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), - .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), - .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), - .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), - .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), - .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), - .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), - .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), - .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), - .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), - .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), - .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), - .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), - .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), - .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), - .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), - .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), - .l2_cpu0_rd_arb (l2_cpu0_rd_arb), - .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), - .l2_cpu0_rexfail (l2_cpu0_rexfail), - .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), - .l2_cpu0_rvalid (l2_cpu0_rvalid), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), - .l2_cpu0_spec_valid (l2_cpu0_spec_valid), - .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), - .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), - .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), - .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), - .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), - .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), - .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), - .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), - .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), - .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), - .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), - .l2_cpu0_wr_arb (l2_cpu0_wr_arb), - .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), - .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), - .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), - .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), - .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), - .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), - .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), - .l2_cpu1_barrier_done (l2_cpu1_barrier_done), - .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), - .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), - .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), - .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), - .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), - .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), - .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), - .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), - .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), - .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), - .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), - .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), - .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), - .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), - .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), - .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), - .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), - .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), - .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), - .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), - .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), - .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), - .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), - .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), - .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), - .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), - .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), - .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), - .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), - .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), - .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), - .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), - .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), - .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), - .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), - .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), - .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), - .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), - .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), - .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), - .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), - .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), - .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), - .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), - .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), - .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), - .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), - .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), - .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), - .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), - .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), - .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), - .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), - .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), - .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), - .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), - .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), - .l2_cpu1_rd_arb (l2_cpu1_rd_arb), - .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), - .l2_cpu1_rexfail (l2_cpu1_rexfail), - .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), - .l2_cpu1_rvalid (l2_cpu1_rvalid), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), - .l2_cpu1_spec_valid (l2_cpu1_spec_valid), - .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), - .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), - .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), - .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), - .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), - .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), - .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), - .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), - .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), - .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), - .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), - .l2_cpu1_wr_arb (l2_cpu1_wr_arb), - .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), - .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), - .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), - .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), - .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), - .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), - .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), - .l2_cpu2_barrier_done (l2_cpu2_barrier_done), - .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), - .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), - .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), - .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), - .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), - .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), - .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), - .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), - .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), - .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), - .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), - .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), - .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), - .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), - .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), - .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), - .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), - .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), - .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), - .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), - .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), - .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), - .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), - .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), - .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), - .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), - .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), - .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), - .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), - .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), - .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), - .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), - .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), - .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), - .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), - .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), - .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), - .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), - .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), - .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), - .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), - .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), - .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), - .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), - .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), - .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), - .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), - .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), - .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), - .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), - .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), - .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), - .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), - .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), - .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), - .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), - .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), - .l2_cpu2_rd_arb (l2_cpu2_rd_arb), - .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), - .l2_cpu2_rexfail (l2_cpu2_rexfail), - .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), - .l2_cpu2_rvalid (l2_cpu2_rvalid), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), - .l2_cpu2_spec_valid (l2_cpu2_spec_valid), - .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), - .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), - .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), - .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), - .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), - .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), - .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), - .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), - .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), - .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), - .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), - .l2_cpu2_wr_arb (l2_cpu2_wr_arb), - .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), - .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), - .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), - .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), - .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), - .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), - .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), - .l2_cpu3_barrier_done (l2_cpu3_barrier_done), - .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), - .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), - .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), - .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), - .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), - .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), - .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), - .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), - .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), - .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), - .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), - .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), - .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), - .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), - .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), - .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), - .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), - .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), - .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), - .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), - .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), - .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), - .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), - .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), - .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), - .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), - .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), - .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), - .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), - .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), - .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), - .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), - .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), - .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), - .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), - .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), - .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), - .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), - .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), - .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), - .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), - .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), - .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), - .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), - .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), - .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), - .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), - .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), - .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), - .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), - .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), - .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), - .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), - .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), - .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), - .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), - .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), - .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), - .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), - .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), - .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), - .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), - .l2_cpu3_rd_arb (l2_cpu3_rd_arb), - .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), - .l2_cpu3_rexfail (l2_cpu3_rexfail), - .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), - .l2_cpu3_rvalid (l2_cpu3_rvalid), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), - .l2_cpu3_spec_valid (l2_cpu3_spec_valid), - .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), - .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), - .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), - .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), - .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), - .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), - .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), - .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), - .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), - .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), - .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), - .l2_cpu3_wr_arb (l2_cpu3_wr_arb), - .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), - .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), - .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), - .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), - .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), - .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .l2_reset3 (l2_reset3), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_sky_link_stopped (l2_sky_link_stopped), - .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), - .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), - .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), - .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), - .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .nEXTERRIRQ (nEXTERRIRQ), - .nINTERRIRQ (nINTERRIRQ), - - // inputs - .ACLKENS (ACLKENS), - .ARADDRS (ARADDRS[43:0]), - .ARCACHES (ARCACHES[3:0]), - .ARIDS (ARIDS[4:0]), - .ARLENS (ARLENS[7:0]), - .ARPROTS (ARPROTS[2:0]), - .ARUSERS (ARUSERS[1:0]), - .ARVALIDS (ARVALIDS), - .AWADDRS (AWADDRS[43:0]), - .AWCACHES (AWCACHES[3:0]), - .AWIDS (AWIDS[4:0]), - .AWLENS (AWLENS[7:0]), - .AWPROTS (AWPROTS[2:0]), - .AWUSERS (AWUSERS[1:0]), - .AWVALIDS (AWVALIDS), - .BREADYS (BREADYS), - .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), - .BROADCASTINNER (BROADCASTINNER), - .BROADCASTOUTER (BROADCASTOUTER), - .DBGL1RSTDISABLE (DBGL1RSTDISABLE), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .L2FLUSHREQ (L2FLUSHREQ), - .L2QREQn (L2QREQn), - .L2RSTDISABLE (L2RSTDISABLE), - .MBISTREQ (MBISTREQ), - .NODEID (NODEID[6:0]), - .PERIPHBASE (PERIPHBASE[43:18]), - .RREADYS (RREADYS), - .RXDATFLIT (RXDATFLIT[193:0]), - .RXDATFLITPEND (RXDATFLITPEND), - .RXDATFLITV (RXDATFLITV), - .RXLINKACTIVEREQ (RXLINKACTIVEREQ), - .RXRSPFLIT (RXRSPFLIT[44:0]), - .RXRSPFLITPEND (RXRSPFLITPEND), - .RXRSPFLITV (RXRSPFLITV), - .RXSACTIVE (RXSACTIVE), - .RXSNPFLIT (RXSNPFLIT[64:0]), - .RXSNPFLITPEND (RXSNPFLITPEND), - .RXSNPFLITV (RXSNPFLITV), - .SAMADDRMAP0 (SAMADDRMAP0[1:0]), - .SAMADDRMAP1 (SAMADDRMAP1[1:0]), - .SAMADDRMAP10 (SAMADDRMAP10[1:0]), - .SAMADDRMAP11 (SAMADDRMAP11[1:0]), - .SAMADDRMAP12 (SAMADDRMAP12[1:0]), - .SAMADDRMAP13 (SAMADDRMAP13[1:0]), - .SAMADDRMAP14 (SAMADDRMAP14[1:0]), - .SAMADDRMAP15 (SAMADDRMAP15[1:0]), - .SAMADDRMAP16 (SAMADDRMAP16[1:0]), - .SAMADDRMAP17 (SAMADDRMAP17[1:0]), - .SAMADDRMAP18 (SAMADDRMAP18[1:0]), - .SAMADDRMAP19 (SAMADDRMAP19[1:0]), - .SAMADDRMAP2 (SAMADDRMAP2[1:0]), - .SAMADDRMAP3 (SAMADDRMAP3[1:0]), - .SAMADDRMAP4 (SAMADDRMAP4[1:0]), - .SAMADDRMAP5 (SAMADDRMAP5[1:0]), - .SAMADDRMAP6 (SAMADDRMAP6[1:0]), - .SAMADDRMAP7 (SAMADDRMAP7[1:0]), - .SAMADDRMAP8 (SAMADDRMAP8[1:0]), - .SAMADDRMAP9 (SAMADDRMAP9[1:0]), - .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), - .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), - .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), - .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), - .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), - .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), - .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), - .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), - .SAMHNFMODE (SAMHNFMODE[2:0]), - .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), - .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), - .SAMMNBASE (SAMMNBASE[43:24]), - .SAMMNNODEID (SAMMNNODEID[6:0]), - .SCLKEN (SCLKEN), - .SYSBARDISABLE (SYSBARDISABLE), - .TXDATLCRDV (TXDATLCRDV), - .TXLINKACTIVEACK (TXLINKACTIVEACK), - .TXREQLCRDV (TXREQLCRDV), - .TXRSPLCRDV (TXRSPLCRDV), - .WDATAS (WDATAS[127:0]), - .WLASTS (WLASTS), - .WSTRBS (WSTRBS[15:0]), - .WVALIDS (WVALIDS), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), - .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), - .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), - .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), - .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), - .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), - .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), - .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), - .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), - .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), - .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), - .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), - .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), - .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), - .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), - .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), - .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), - .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), - .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), - .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), - .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), - .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), - .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), - .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), - .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), - .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), - .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), - .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), - .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), - .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), - .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), - .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), - .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), - .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), - .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), - .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), - .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), - .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), - .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), - .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), - .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), - .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), - .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), - .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), - .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), - .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), - .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), - .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), - .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), - .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), - .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), - .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), - .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), - .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), - .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), - .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), - .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), - .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), - .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), - .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), - .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), - .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), - .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), - .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), - .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), - .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), - .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), - .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), - .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), - .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), - .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), - .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), - .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), - .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), - .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), - .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), - .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), - .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), - .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), - .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), - .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), - .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), - .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), - .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), - .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), - .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), - .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), - .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), - .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), - .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), - .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), - .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), - .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), - .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), - .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), - .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), - .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), - .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), - .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), - .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), - .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), - .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), - .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), - .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), - .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), - .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), - .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), - .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), - .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), - .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), - .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), - .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), - .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), - .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), - .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), - .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), - .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), - .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), - .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), - .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), - .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), - .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), - .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), - .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), - .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), - .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), - .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), - .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), - .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), - .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), - .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), - .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), - .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), - .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), - .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), - .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), - .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), - .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), - .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), - .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), - .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), - .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), - .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), - .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), - .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), - .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), - .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), - .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), - .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), - .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), - .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), - .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), - .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), - .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), - .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), - .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), - .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), - .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), - .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), - .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), - .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), - .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), - .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), - .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), - .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), - .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), - .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), - .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), - .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), - .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), - .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), - .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), - .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), - .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), - .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), - .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), - .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), - .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), - .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), - .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), - .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), - .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), - .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), - .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), - .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), - .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), - .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), - .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), - .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), - .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), - .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), - .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), - .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), - .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), - .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), - .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), - .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), - .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), - .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), - .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), - .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), - .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), - .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), - .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), - .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), - .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), - .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), - .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), - .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), - .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), - .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), - .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), - .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), - .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), - .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), - .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), - .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), - .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), - .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), - .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), - .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), - .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), - .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), - .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), - .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), - .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), - .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), - .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), - .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), - .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), - .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), - .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), - .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), - .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), - .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), - .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), - .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), - .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), - .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), - .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), - .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), - .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), - .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), - .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), - .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), - .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), - .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), - .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), - .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), - .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), - .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), - .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), - .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), - .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), - .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), - .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), - .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), - .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), - .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), - .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), - .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), - .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), - .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), - .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), - .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), - .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), - .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), - .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), - .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), - .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), - .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), - .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), - .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), - .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), - .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), - .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), - .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), - .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), - .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), - .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), - .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), - .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), - .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), - .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), - .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), - .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), - .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), - .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), - .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), - .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), - .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), - .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), - .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), - .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), - .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), - .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk0_idle (l2_tbnk0_idle), - .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk1_idle (l2_tbnk1_idle), - .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), - .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), - .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), - .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), - .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), - .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), - .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), - .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) - ); // ul2_logic - - maia_l2_tbnk ul2_tbnk0( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk0_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb0), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk0_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk0 - - maia_l2_tbnk ul2_tbnk1( // outputs - .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), - .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), - .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), - .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), - .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), - .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), - .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), - .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), - .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), - .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), - .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), - .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), - .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), - .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), - .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), - .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), - .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), - .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), - .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), - .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), - .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), - .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), - .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), - .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), - .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), - .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), - .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), - .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), - .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), - .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), - .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), - .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), - .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), - .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), - .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), - .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), - .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), - .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), - .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), - .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), - .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), - .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), - .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), - .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), - .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), - .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), - .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), - .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), - .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), - .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), - .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), - .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), - .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), - .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), - .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), - .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), - .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), - .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), - .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), - .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), - .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), - .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), - .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), - .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), - .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), - .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), - .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), - .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), - .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), - .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), - .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), - .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), - .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), - .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), - .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), - .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), - .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), - .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), - .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), - .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), - .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), - .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), - .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), - .l2_tbnk_idle (l2_tbnk1_idle), - .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), - .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), - .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), - .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), - .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), - .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), - .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), - .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), - .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), - .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), - .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), - .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), - .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), - .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), - .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), - .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), - .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), - .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), - .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), - .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), - .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), - .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), - .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), - .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), - .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), - .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), - .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), - .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), - .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), - .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), - .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), - .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), - .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), - .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), - .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), - .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), - .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), - .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), - .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), - .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), - .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), - .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), - .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), - .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), - .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), - .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), - .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), - .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), - .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), - .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), - .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), - .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), - .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), - .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), - .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), - .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), - .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), - .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), - - // inputs - .DFTCLKBYPASS (DFTCLKBYPASS), - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRAMHOLD (DFTRAMHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ), - .ck_areset_l2 (ck_areset_l2), - .ck_gclkl2 (ck_gclkb1), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), - .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), - .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), - .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), - .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), - .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), - .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), - .l2_actlr_plru_en (l2_actlr_plru_en), - .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), - .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), - .l2_cfg_broadcastinner (l2_cfg_broadcastinner), - .l2_cfg_broadcastouter (l2_cfg_broadcastouter), - .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), - .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), - .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), - .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), - .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), - .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), - .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), - .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), - .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), - .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), - .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), - .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), - .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), - .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), - .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), - .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), - .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), - .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), - .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), - .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), - .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), - .l2_rstdisable_x1_q (l2_rstdisable_x1_q), - .l2_skyros_intf (1'b1), - .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), - .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), - .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), - .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), - .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), - .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), - .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), - .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), - .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), - .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), - .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), - .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), - .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), - .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), - .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), - .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), - .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), - .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), - .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), - .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), - .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), - .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), - .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), - .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), - .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), - .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), - .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), - .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), - .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), - .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), - .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), - .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), - .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), - .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), - .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), - .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), - .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), - .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), - .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), - .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), - .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), - .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), - .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), - .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), - .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), - .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), - .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), - .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), - .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), - .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), - .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), - .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), - .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), - .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), - .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), - .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), - .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), - .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), - .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), - .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), - .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), - .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), - .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), - .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), - .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), - .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), - .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), - .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), - .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), - .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), - .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), - .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), - .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), - .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), - .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), - .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), - .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), - .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), - .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), - .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), - .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), - .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), - .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), - .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), - .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), - .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), - .l2_tbnk_way_l1 (l2_tbnk1_way_l1), - .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), - .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), - .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), - .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), - .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), - .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) - ); // ul2_tbnk1 - - maia_dt_pclk udt_pclk( // outputs - .CTICHINACK (CTICHINACK[3:0]), - .CTICHOUT (CTICHOUT[3:0]), - .CTIIRQ (CTIIRQ[`MAIA_CN:0]), - .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), - .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), - .PRDATADBG (PRDATADBG[31:0]), - .PREADYDBG (PREADYDBG), - .PSLVERRDBG (PSLVERRDBG), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), - .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), - .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), - .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), - .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), - .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), - .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), - .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), - .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), - .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), - .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), - .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), - .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), - .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), - .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), - .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), - .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), - .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), - .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), - .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), - .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), - .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), - .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), - .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), - .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), - .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), - .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), - .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), - .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), - .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), - .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), - .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), - .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), - .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), - .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), - .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), - .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), - .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), - .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), - .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), - .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), - .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), - .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), - .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), - .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), - .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), - .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), - .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), - .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), - .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), - .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), - .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), - .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), - .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), - .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), - .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), - .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), - .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), - .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), - .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), - .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), - .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), - .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), - .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), - .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - - // inputs - .CIHSBYPASS (CIHSBYPASS[3:0]), - .CISBYPASS (CISBYPASS), - .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), - .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), - .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), - .CTICHIN (CTICHIN[3:0]), - .CTICHOUTACK (CTICHOUTACK[3:0]), - .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), - .DBGEN (DBGEN[`MAIA_CN:0]), - .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .EDBGRQ (EDBGRQ[`MAIA_CN:0]), - .GICCDISABLE (GICCDISABLE), - .NIDEN (NIDEN[`MAIA_CN:0]), - .PADDRDBG (PADDRDBG[21:2]), - .PADDRDBG31 (PADDRDBG31), - .PCLKDBG (PCLKDBG), - .PCLKENDBG (PCLKENDBG), - .PENABLEDBG (PENABLEDBG), - .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), - .PSELDBG (PSELDBG), - .PWDATADBG (PWDATADBG[31:0]), - .PWRITEDBG (PWRITEDBG), - .SPIDEN (SPIDEN[`MAIA_CN:0]), - .SPNIDEN (SPNIDEN[`MAIA_CN:0]), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), - .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), - .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), - .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), - .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), - .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), - .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), - .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), - .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), - .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), - .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), - .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), - .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), - .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), - .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), - .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), - .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), - .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), - .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), - .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), - .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), - .nPRESETDBG (nPRESETDBG) - ); // udt_pclk - - maia_intctrl uic( // outputs - .ICCTDATA (ICCTDATA[15:0]), - .ICCTID (ICCTID[1:0]), - .ICCTLAST (ICCTLAST), - .ICCTVALID (ICCTVALID), - .ICDTREADY (ICDTREADY), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), - .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), - .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), - .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), - .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), - .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), - .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), - .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), - .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_p_rdata (ic_p_rdata[31:0]), - .ic_p_rdata_valid (ic_p_rdata_valid), - .ic_p_ready (ic_p_ready), - .ic_p_valid (ic_p_valid[`MAIA_CN:0]), - .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), - .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), - - // inputs - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .GICCDISABLE (GICCDISABLE), - .ICCTREADY (ICCTREADY), - .ICDTDATA (ICDTDATA[15:0]), - .ICDTDEST (ICDTDEST[1:0]), - .ICDTLAST (ICDTLAST), - .ICDTVALID (ICDTVALID), - .ck_areset_l2 (ck_areset_l2), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), - .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), - .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), - .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), - .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), - .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), - .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), - .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), - .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), - .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), - .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), - .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), - .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), - .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), - .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), - .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), - .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), - .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), - .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), - .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), - .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), - .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), - .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), - .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), - .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), - .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), - .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), - .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), - .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), - .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), - .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), - .l2_p_addr (l2_p_addr[13:0]), - .l2_p_cpu (l2_p_cpu[1:0]), - .l2_p_nsecure (l2_p_nsecure), - .l2_p_sel (l2_p_sel[2:0]), - .l2_p_wdata (l2_p_wdata[31:0]), - .l2_p_write (l2_p_write), - .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), - .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), - .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), - .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), - .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), - .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), - .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), - .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), - .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), - .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), - .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), - .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), - .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), - .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), - .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), - .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), - .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), - .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), - .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), - .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), - .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), - .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), - .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), - .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), - .nFIQ (nFIQ[`MAIA_CN:0]), - .nIRQ (nIRQ[`MAIA_CN:0]), - .nREI (nREI[`MAIA_CN:0]), - .nSEI (nSEI[`MAIA_CN:0]), - .nVFIQ (nVFIQ[`MAIA_CN:0]), - .nVIRQ (nVIRQ[`MAIA_CN:0]), - .nVSEI (nVSEI[`MAIA_CN:0]) - ); // uic - - maia_ck_l2 uck_l2( // outputs - .ck_gclkb0 (ck_gclkb0), - .ck_gclkb1 (ck_gclkb1), - .ck_gclkfr (ck_gclkfr), - .ck_gclkl2 (ck_gclkl2), - - // inputs - .DFTL2CLKDISABLE (DFTL2CLKDISABLE), - .DFTSE (DFTSE), - .ck_gclktl2 (ck_gclktl2), - .ck_l2_logic_clk_en (ck_l2_logic_clk_en), - .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), - .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), - .l2_reset3 (l2_reset3) - ); // uck_l2 - - maia_ck_top uck_top( // outputs - .ck_gclkt (ck_gclkt[`MAIA_CN:0]), - .ck_gclktl2 (ck_gclktl2), - - // inputs - .CLK (CLK), - .CLKEN (CLKEN), - .DFTSE (DFTSE), - .MBISTREQ (MBISTREQ) - ); // uck_top - - maia_ck_logic uck_logic( // outputs - .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), - .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), - .CPUQDENY (CPUQDENY[`MAIA_CN:0]), - .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), - .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), - .STANDBYWFIL2 (STANDBYWFIL2), - .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), - .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), - .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), - .ck_cpu0_event_reg (ck_cpu0_event_reg), - .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), - .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_poreset_status (ck_cpu0_poreset_status), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), - .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), - .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), - .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), - .ck_cpu1_event_reg (ck_cpu1_event_reg), - .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), - .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_poreset_status (ck_cpu1_poreset_status), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), - .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), - .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), - .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), - .ck_cpu2_event_reg (ck_cpu2_event_reg), - .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), - .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_poreset_status (ck_cpu2_poreset_status), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), - .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), - .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), - .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), - .ck_cpu3_event_reg (ck_cpu3_event_reg), - .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), - .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_poreset_status (ck_cpu3_poreset_status), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), - .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), - .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), - .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), - .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), - .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), - .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), - .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), - .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), - .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), - .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), - .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), - .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), - .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), - .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), - .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), - .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), - .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), - .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), - .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), - .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), - .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), - .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), - .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), - .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), - .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), - .ck_l2_ace_inactive (ck_l2_ace_inactive), - .ck_l2_acp_inactive (ck_l2_acp_inactive), - .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), - - // inputs - .ACINACTM (SINACT), - .AINACTS (AINACTS), - .CPUQREQn (CPUQREQn[`MAIA_CN:0]), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .ck_gclkfr (ck_gclkfr), - .clrexmon_c1 (clrexmon_c1), - .commrx_cpu0_i (commrx_cpu0_i), - .commrx_cpu1_i (commrx_cpu1_i), - .commrx_cpu2_i (commrx_cpu2_i), - .commrx_cpu3_i (commrx_cpu3_i), - .commtx_cpu0_i (commtx_cpu0_i), - .commtx_cpu1_i (commtx_cpu1_i), - .commtx_cpu2_i (commtx_cpu2_i), - .commtx_cpu3_i (commtx_cpu3_i), - .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), - .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), - .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), - .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), - .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), - .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), - .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), - .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), - .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), - .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), - .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), - .ds_cpu0_flush (ds_cpu0_flush), - .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), - .ds_cpu0_hcr_va (ds_cpu0_hcr_va), - .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), - .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), - .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), - .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), - .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), - .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), - .ds_cpu0_reset_req (ds_cpu0_reset_req), - .ds_cpu0_sevl_req (ds_cpu0_sevl_req), - .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), - .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), - .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), - .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), - .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), - .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), - .ds_cpu0_wfe_req (ds_cpu0_wfe_req), - .ds_cpu0_wfi_req (ds_cpu0_wfi_req), - .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), - .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), - .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), - .ds_cpu1_flush (ds_cpu1_flush), - .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), - .ds_cpu1_hcr_va (ds_cpu1_hcr_va), - .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), - .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), - .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), - .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), - .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), - .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), - .ds_cpu1_reset_req (ds_cpu1_reset_req), - .ds_cpu1_sevl_req (ds_cpu1_sevl_req), - .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), - .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), - .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), - .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), - .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), - .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), - .ds_cpu1_wfe_req (ds_cpu1_wfe_req), - .ds_cpu1_wfi_req (ds_cpu1_wfi_req), - .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), - .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), - .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), - .ds_cpu2_flush (ds_cpu2_flush), - .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), - .ds_cpu2_hcr_va (ds_cpu2_hcr_va), - .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), - .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), - .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), - .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), - .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), - .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), - .ds_cpu2_reset_req (ds_cpu2_reset_req), - .ds_cpu2_sevl_req (ds_cpu2_sevl_req), - .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), - .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), - .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), - .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), - .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), - .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), - .ds_cpu2_wfe_req (ds_cpu2_wfe_req), - .ds_cpu2_wfi_req (ds_cpu2_wfi_req), - .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), - .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), - .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), - .ds_cpu3_flush (ds_cpu3_flush), - .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), - .ds_cpu3_hcr_va (ds_cpu3_hcr_va), - .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), - .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), - .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), - .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), - .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), - .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), - .ds_cpu3_reset_req (ds_cpu3_reset_req), - .ds_cpu3_sevl_req (ds_cpu3_sevl_req), - .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), - .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), - .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), - .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), - .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), - .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), - .ds_cpu3_wfe_req (ds_cpu3_wfe_req), - .ds_cpu3_wfi_req (ds_cpu3_wfi_req), - .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), - .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), - .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), - .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), - .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), - .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), - .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), - .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), - .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), - .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), - .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), - .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), - .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), - .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), - .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), - .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), - .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), - .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), - .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), - .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), - .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), - .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), - .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), - .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), - .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), - .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), - .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), - .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), - .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), - .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), - .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), - .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), - .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), - .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), - .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), - .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), - .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), - .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), - .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), - .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), - .l2_cpu0_snp_active (l2_cpu0_snp_active), - .l2_cpu1_snp_active (l2_cpu1_snp_active), - .l2_cpu2_snp_active (l2_cpu2_snp_active), - .l2_cpu3_snp_active (l2_cpu3_snp_active), - .l2_idle (l2_idle), - .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), - .l2_reset3 (l2_reset3), - .l2_sky_link_stopped (l2_sky_link_stopped), - .ls_cpu0_clrexmon (ls_cpu0_clrexmon), - .ls_cpu1_clrexmon (ls_cpu1_clrexmon), - .ls_cpu2_clrexmon (ls_cpu2_clrexmon), - .ls_cpu3_clrexmon (ls_cpu3_clrexmon), - .nCORERESET (nCORERESET[`MAIA_CN:0]), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nL2RESET (nL2RESET), - .nMBISTRESET (nMBISTRESET), - .ncommirq_cpu0_i (ncommirq_cpu0_i), - .ncommirq_cpu1_i (ncommirq_cpu1_i), - .ncommirq_cpu2_i (ncommirq_cpu2_i), - .ncommirq_cpu3_i (ncommirq_cpu3_i), - .npmuirq_cpu0_i (npmuirq_cpu0_i), - .npmuirq_cpu1_i (npmuirq_cpu1_i), - .npmuirq_cpu2_i (npmuirq_cpu2_i), - .npmuirq_cpu3_i (npmuirq_cpu3_i), - .tm_cntpct_q (tm_cntpct_q[8:0]), - .tm_cpu0_event_sev (tm_cpu0_event_sev), - .tm_cpu1_event_sev (tm_cpu1_event_sev), - .tm_cpu2_event_sev (tm_cpu2_event_sev), - .tm_cpu3_event_sev (tm_cpu3_event_sev) - ); // uck_logic - - maia_cpu_io ucpu_io( // outputs - .aa64naa32_cpu0_o (aa64naa32_cpu0_o), - .aa64naa32_cpu1_o (aa64naa32_cpu1_o), - .aa64naa32_cpu2_o (aa64naa32_cpu2_o), - .aa64naa32_cpu3_o (aa64naa32_cpu3_o), - .cfgend_cpu0_o (cfgend_cpu0_o), - .cfgend_cpu1_o (cfgend_cpu1_o), - .cfgend_cpu2_o (cfgend_cpu2_o), - .cfgend_cpu3_o (cfgend_cpu3_o), - .cfgte_cpu0_o (cfgte_cpu0_o), - .cfgte_cpu1_o (cfgte_cpu1_o), - .cfgte_cpu2_o (cfgte_cpu2_o), - .cfgte_cpu3_o (cfgte_cpu3_o), - .clrexmon_c1 (clrexmon_c1), - .clrexmonack_o (CLREXMONACK), - .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), - .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), - .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), - .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), - .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), - .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), - .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), - .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), - .commrx_o (COMMRX[`MAIA_CN:0]), - .commtx_o (COMMTX[`MAIA_CN:0]), - .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), - .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), - .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), - .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), - .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), - .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), - .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), - .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), - .cryptodisable_cpu0_o (cryptodisable_cpu0_o), - .cryptodisable_cpu1_o (cryptodisable_cpu1_o), - .cryptodisable_cpu2_o (cryptodisable_cpu2_o), - .cryptodisable_cpu3_o (cryptodisable_cpu3_o), - .dbgack_o (DBGACK[`MAIA_CN:0]), - .dbgen_cpu0_o (dbgen_cpu0_o), - .dbgen_cpu1_o (dbgen_cpu1_o), - .dbgen_cpu2_o (dbgen_cpu2_o), - .dbgen_cpu3_o (dbgen_cpu3_o), - .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), - .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), - .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), - .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), - .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), - .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), - .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), - .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), - .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), - .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), - .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), - .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), - .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), - .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), - .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), - .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), - .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), - .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), - .dftramhold_cpu0_o (dftramhold_cpu0_o), - .dftramhold_cpu1_o (dftramhold_cpu1_o), - .dftramhold_cpu2_o (dftramhold_cpu2_o), - .dftramhold_cpu3_o (dftramhold_cpu3_o), - .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), - .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), - .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), - .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), - .dftse_cpu0_o (dftse_cpu0_o), - .dftse_cpu1_o (dftse_cpu1_o), - .dftse_cpu2_o (dftse_cpu2_o), - .dftse_cpu3_o (dftse_cpu3_o), - .eventi_sev (eventi_sev), - .evento_o (EVENTO), - .giccdisable_cpu0_o (giccdisable_cpu0_o), - .giccdisable_cpu1_o (giccdisable_cpu1_o), - .giccdisable_cpu2_o (giccdisable_cpu2_o), - .giccdisable_cpu3_o (giccdisable_cpu3_o), - .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), - .ncorereset_cpu0_o (ncorereset_cpu0_o), - .ncorereset_cpu1_o (ncorereset_cpu1_o), - .ncorereset_cpu2_o (ncorereset_cpu2_o), - .ncorereset_cpu3_o (ncorereset_cpu3_o), - .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), - .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), - .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), - .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), - .niden_cpu0_o (niden_cpu0_o), - .niden_cpu1_o (niden_cpu1_o), - .niden_cpu2_o (niden_cpu2_o), - .niden_cpu3_o (niden_cpu3_o), - .nmbistreset_cpu0_o (nmbistreset_cpu0_o), - .nmbistreset_cpu1_o (nmbistreset_cpu1_o), - .nmbistreset_cpu2_o (nmbistreset_cpu2_o), - .nmbistreset_cpu3_o (nmbistreset_cpu3_o), - .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), - .pmuevent0_o (PMUEVENT0[24:0]), - .pmuevent1_o (PMUEVENT1[24:0]), - .pmuevent2_o (PMUEVENT2[24:0]), - .pmuevent3_o (PMUEVENT3[24:0]), - .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), - .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), - .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), - .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), - .smpen_o (SMPEN[`MAIA_CN:0]), - .spiden_cpu0_o (spiden_cpu0_o), - .spiden_cpu1_o (spiden_cpu1_o), - .spiden_cpu2_o (spiden_cpu2_o), - .spiden_cpu3_o (spiden_cpu3_o), - .spniden_cpu0_o (spniden_cpu0_o), - .spniden_cpu1_o (spniden_cpu1_o), - .spniden_cpu2_o (spniden_cpu2_o), - .spniden_cpu3_o (spniden_cpu3_o), - .vinithi_cpu0_o (vinithi_cpu0_o), - .vinithi_cpu1_o (vinithi_cpu1_o), - .vinithi_cpu2_o (vinithi_cpu2_o), - .vinithi_cpu3_o (vinithi_cpu3_o), - - // inputs - .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), - .cfgend_i (CFGEND[`MAIA_CN:0]), - .cfgte_i (CFGTE[`MAIA_CN:0]), - .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), - .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), - .ck_cpu0_commrx (ck_cpu0_commrx), - .ck_cpu0_commtx (ck_cpu0_commtx), - .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), - .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), - .ck_cpu0_ncommirq (ck_cpu0_ncommirq), - .ck_cpu0_npmuirq (ck_cpu0_npmuirq), - .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), - .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), - .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), - .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), - .ck_cpu1_commrx (ck_cpu1_commrx), - .ck_cpu1_commtx (ck_cpu1_commtx), - .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), - .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), - .ck_cpu1_ncommirq (ck_cpu1_ncommirq), - .ck_cpu1_npmuirq (ck_cpu1_npmuirq), - .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), - .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), - .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), - .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), - .ck_cpu2_commrx (ck_cpu2_commrx), - .ck_cpu2_commtx (ck_cpu2_commtx), - .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), - .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), - .ck_cpu2_ncommirq (ck_cpu2_ncommirq), - .ck_cpu2_npmuirq (ck_cpu2_npmuirq), - .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), - .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), - .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), - .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), - .ck_cpu3_commrx (ck_cpu3_commrx), - .ck_cpu3_commtx (ck_cpu3_commtx), - .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), - .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), - .ck_cpu3_ncommirq (ck_cpu3_ncommirq), - .ck_cpu3_npmuirq (ck_cpu3_npmuirq), - .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), - .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), - .ck_gclkfr (ck_gclkfr), - .clrexmonreq_i (CLREXMONREQ), - .clusteridaff1_i (CLUSTERIDAFF1[7:0]), - .clusteridaff2_i (CLUSTERIDAFF2[7:0]), - .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), - .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), - .dbgack_cpu0_i (dbgack_cpu0_i), - .dbgack_cpu1_i (dbgack_cpu1_i), - .dbgack_cpu2_i (dbgack_cpu2_i), - .dbgack_cpu3_i (dbgack_cpu3_i), - .dbgen_i (DBGEN[`MAIA_CN:0]), - .dbgl1rstdisable_i (DBGL1RSTDISABLE), - .dbgromaddr_i (DBGROMADDR[43:12]), - .dbgromaddrv_i (DBGROMADDRV), - .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), - .dftramhold_i (DFTRAMHOLD), - .dftrstdisable_i (DFTRSTDISABLE), - .dftse_i (DFTSE), - .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), - .ds_cpu0_sev_req (ds_cpu0_sev_req), - .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), - .ds_cpu1_sev_req (ds_cpu1_sev_req), - .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), - .ds_cpu2_sev_req (ds_cpu2_sev_req), - .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), - .ds_cpu3_sev_req (ds_cpu3_sev_req), - .eventi_i (EVENTI), - .giccdisable_i (GICCDISABLE), - .l2_reset3 (l2_reset3), - .ncorereset_i (nCORERESET[`MAIA_CN:0]), - .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), - .niden_i (NIDEN[`MAIA_CN:0]), - .nmbistreset_i (nMBISTRESET), - .pm_export_cpu0_i (pm_export_cpu0_i), - .pm_export_cpu1_i (pm_export_cpu1_i), - .pm_export_cpu2_i (pm_export_cpu2_i), - .pm_export_cpu3_i (pm_export_cpu3_i), - .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), - .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), - .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), - .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), - .rvbaraddr0_i (RVBARADDR0[43:2]), - .rvbaraddr1_i (RVBARADDR1[43:2]), - .rvbaraddr2_i (RVBARADDR2[43:2]), - .rvbaraddr3_i (RVBARADDR3[43:2]), - .spiden_i (SPIDEN[`MAIA_CN:0]), - .spniden_i (SPNIDEN[`MAIA_CN:0]), - .vinithi_i (VINITHI[`MAIA_CN:0]) - ); // ucpu_io - - maia_dt_sb udt_sb( // outputs - .afreadym0_o (AFREADYM0), - .afreadym1_o (AFREADYM1), - .afreadym2_o (AFREADYM2), - .afreadym3_o (AFREADYM3), - .afvalidm_cpu0_o (afvalidm_cpu0_o), - .afvalidm_cpu1_o (afvalidm_cpu1_o), - .afvalidm_cpu2_o (afvalidm_cpu2_o), - .afvalidm_cpu3_o (afvalidm_cpu3_o), - .atbytesm0_o (ATBYTESM0[1:0]), - .atbytesm1_o (ATBYTESM1[1:0]), - .atbytesm2_o (ATBYTESM2[1:0]), - .atbytesm3_o (ATBYTESM3[1:0]), - .atclken_cpu0_o (atclken_cpu0_o), - .atclken_cpu1_o (atclken_cpu1_o), - .atclken_cpu2_o (atclken_cpu2_o), - .atclken_cpu3_o (atclken_cpu3_o), - .atdatam0_o (ATDATAM0[31:0]), - .atdatam1_o (ATDATAM1[31:0]), - .atdatam2_o (ATDATAM2[31:0]), - .atdatam3_o (ATDATAM3[31:0]), - .atidm0_o (ATIDM0[6:0]), - .atidm1_o (ATIDM1[6:0]), - .atidm2_o (ATIDM2[6:0]), - .atidm3_o (ATIDM3[6:0]), - .atreadym_cpu0_o (atreadym_cpu0_o), - .atreadym_cpu1_o (atreadym_cpu1_o), - .atreadym_cpu2_o (atreadym_cpu2_o), - .atreadym_cpu3_o (atreadym_cpu3_o), - .atvalidm0_o (ATVALIDM0), - .atvalidm1_o (ATVALIDM1), - .atvalidm2_o (ATVALIDM2), - .atvalidm3_o (ATVALIDM3), - .syncreqm_cpu0_o (syncreqm_cpu0_o), - .syncreqm_cpu1_o (syncreqm_cpu1_o), - .syncreqm_cpu2_o (syncreqm_cpu2_o), - .syncreqm_cpu3_o (syncreqm_cpu3_o), - .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), - .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), - .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), - .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), - - // inputs - .DFTMCPHOLD (DFTMCPHOLD), - .DFTRSTDISABLE (DFTRSTDISABLE), - .DFTSE (DFTSE), - .TSVALUEB (TSVALUEB[63:0]), - .afreadym_cpu0_i (afreadym_cpu0_i), - .afreadym_cpu1_i (afreadym_cpu1_i), - .afreadym_cpu2_i (afreadym_cpu2_i), - .afreadym_cpu3_i (afreadym_cpu3_i), - .afvalidm0_i (AFVALIDM0), - .afvalidm1_i (AFVALIDM1), - .afvalidm2_i (AFVALIDM2), - .afvalidm3_i (AFVALIDM3), - .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), - .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), - .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), - .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), - .atclken_i (ATCLKEN), - .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), - .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), - .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), - .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), - .atidm_cpu0_i (atidm_cpu0_i[6:0]), - .atidm_cpu1_i (atidm_cpu1_i[6:0]), - .atidm_cpu2_i (atidm_cpu2_i[6:0]), - .atidm_cpu3_i (atidm_cpu3_i[6:0]), - .atreadym0_i (ATREADYM0), - .atreadym1_i (ATREADYM1), - .atreadym2_i (ATREADYM2), - .atreadym3_i (ATREADYM3), - .atvalidm_cpu0_i (atvalidm_cpu0_i), - .atvalidm_cpu1_i (atvalidm_cpu1_i), - .atvalidm_cpu2_i (atvalidm_cpu2_i), - .atvalidm_cpu3_i (atvalidm_cpu3_i), - .ck_gclkfr (ck_gclkfr), - .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), - .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), - .etclken_cpu0_i (etclken_cpu0_i), - .etclken_cpu1_i (etclken_cpu1_i), - .etclken_cpu2_i (etclken_cpu2_i), - .etclken_cpu3_i (etclken_cpu3_i), - .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), - .nMBISTRESET (nMBISTRESET), - .syncreqm0_i (SYNCREQM0), - .syncreqm1_i (SYNCREQM1), - .syncreqm2_i (SYNCREQM2), - .syncreqm3_i (SYNCREQM3) - ); // udt_sb - - maia_ncpu_reg_rep uncpu_reg_rep( // outputs - .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), - .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), - .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), - .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), - .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), - .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), - .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), - .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), - .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), - .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), - .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), - .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), - .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), - .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), - .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), - .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), - .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), - .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), - .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), - .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), - .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), - .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), - .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), - .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), - .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), - .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), - .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), - .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), - .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), - .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), - .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), - .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), - .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), - .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), - .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), - .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), - .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), - .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), - .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), - - // inputs - .ck_gclkfr (ck_gclkfr), - .ck_reset1_n_l2 (ck_reset1_n_l2), - .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), - .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), - .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), - .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), - .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), - .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), - .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), - .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), - .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), - .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), - .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), - .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), - .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), - .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), - .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), - .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), - .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), - .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), - .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), - .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), - .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), - .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), - .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), - .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), - .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), - .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), - .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), - .ic_nirq (ic_nirq_o[`MAIA_CN:0]), - .ic_nsei (ic_nsei_o[`MAIA_CN:0]), - .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), - .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), - .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), - .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), - .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), - .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), - .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), - .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), - .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), - .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), - .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), - .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) - ); // uncpu_reg_rep - -//----------------------------------------------------------------------------- -// OVL Assertions -//----------------------------------------------------------------------------- -`ifdef ARM_ASSERT_ON - `include "maia_noncpu_s_val.v" -`endif - -endmodule // maia_noncpu_s - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v deleted file mode 100644 index 496b1e1872..0000000000 --- a/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v +++ /dev/null @@ -1,2816 +0,0 @@ - -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_complex.v $ -// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ -// Revision : $Revision: 70482 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- -//# -//# Overview -//# ======== -//# -//# This is top-level interconnect layer for the Complex Execute unit. -//# - -`include "maia_header.v" - -module maia_complex( // outputs - cx_active, - cx_credit_j, - cx_credit_k, - cx_dstp_tag_ke1, - cx_dstp_tag_vld_ke1, - cx_resp_data_w1, - cx_resp_qfbit_gid_w1, - cx_resp_qfbit_vld_w1, - cx_resp_qfbit_w2, - cx_resp_tag_vld_w0, - cx_resp_tag_w0, - cx_resx_data_w2, - cx_resx_dw_w1, - cx_resx_qfbit_gid_w1, - cx_resx_qfbit_vld_w1, - cx_resx_qfbit_w2, - cx_resx_tag_vld_w1, - cx_resx_tag_w1, - cx_resy_data_w2, - cx_resy_dw_w1, - cx_resy_qfbit_gid_w1, - cx_resy_qfbit_vld_w1, - cx_resy_qfbit_w2, - cx_resy_tag_vld_w1, - cx_resy_tag_w1, - cx_resz_data_w2, - cx_resz_dw_w1, - cx_resz_qfbit_gid_w1, - cx_resz_qfbit_vld_w1, - cx_resz_qfbit_w2, - cx_resz_tag_vld_w1, - cx_resz_tag_w1, - - // inputs - ck_areset, - ck_gclkcx, - ck_reset1_n_cx, - dftrstdisable_cpu, - dftse_cpu, - ds_cx_aarch32_state, - ds_cx_aarch64_state, - ds_cx_cpuactlr_frc_cpu_rcg_active, - ds_cx_dstp_tag_jp2, - ds_cx_dstp_tag_kp2, - ds_cx_dstp_tag_vld_jp2, - ds_cx_dstp_tag_vld_kp2, - ds_cx_dstx_dw_jp2, - ds_cx_dstx_dw_kp2, - ds_cx_dstx_tag_jp2, - ds_cx_dstx_tag_kp2, - ds_cx_dstx_tag_vld_jp2, - ds_cx_dstx_tag_vld_kp2, - ds_cx_dsty_dw_jp2, - ds_cx_dsty_dw_kp2, - ds_cx_dsty_tag_jp2, - ds_cx_dsty_tag_kp2, - ds_cx_dsty_tag_vld_jp2, - ds_cx_dsty_tag_vld_kp2, - ds_cx_flush_gid, - ds_cx_flush_seq, - ds_cx_flush_u1, - ds_cx_fpscr_ahp, - ds_cx_fpscr_dn, - ds_cx_fpscr_fz, - ds_cx_fpscr_rmode, - ds_cx_gid_jp2, - ds_cx_gid_kp2, - ds_cx_prt_sel_jp1, - ds_cx_prt_sel_kp1, - ds_cx_srca_data_jp2, - ds_cx_srca_data_kp2, - ds_cx_srca_data_vld_jp2, - ds_cx_srca_data_vld_kp2, - ds_cx_srcb_data_jp2, - ds_cx_srcb_data_kp2, - ds_cx_srcb_data_vld_jp2, - ds_cx_srcb_data_vld_kp2, - ds_cx_srcc_data_jp2, - ds_cx_srcc_data_kp2, - ds_cx_srcc_data_vld_jp2, - ds_cx_srcc_data_vld_kp2, - ds_cx_srcd_data_jp2, - ds_cx_srcd_data_kp2, - ds_cx_srcd_data_vld_jp2, - ds_cx_srcd_data_vld_kp2, - ds_cx_srcp_data_jp2, - ds_cx_srcp_data_kp2, - ds_cx_srcp_data_vld_jp2, - ds_cx_srcp_data_vld_kp2, - ds_cx_swdw_nuke_jp2, - ds_cx_swdw_nuke_kp2, - ds_cx_uop_ctl_jp2, - ds_cx_uop_ctl_kp2, - ds_cx_uop_vld_jp2, - ds_cx_uop_vld_kp2, - ds_srca_dw_0p1, - ds_srca_dw_1p1, - ds_srca_dw_2p1, - ds_srca_prdcr_dw_0p1, - ds_srca_prdcr_dw_1p1, - ds_srca_prdcr_dw_2p1, - ds_srca_tag_0p1, - ds_srca_tag_1p1, - ds_srca_tag_2p1, - ds_srca_tag_vld_0p1, - ds_srca_tag_vld_1p1, - ds_srca_tag_vld_2p1, - ds_srcb_dw_0p1, - ds_srcb_dw_1p1, - ds_srcb_dw_2p1, - ds_srcb_prdcr_dw_0p1, - ds_srcb_prdcr_dw_1p1, - ds_srcb_prdcr_dw_2p1, - ds_srcb_tag_0p1, - ds_srcb_tag_1p1, - ds_srcb_tag_2p1, - ds_srcb_tag_vld_0p1, - ds_srcb_tag_vld_1p1, - ds_srcb_tag_vld_2p1, - ds_srcc_dw_0p1, - ds_srcc_dw_1p1, - ds_srcc_dw_2p1, - ds_srcc_prdcr_dw_0p1, - ds_srcc_prdcr_dw_1p1, - ds_srcc_prdcr_dw_2p1, - ds_srcc_tag_0p1, - ds_srcc_tag_1p1, - ds_srcc_tag_2p1, - ds_srcc_tag_vld_0p1, - ds_srcc_tag_vld_1p1, - ds_srcc_tag_vld_2p1, - ds_srcd_dw_0p1, - ds_srcd_dw_1p1, - ds_srcd_dw_2p1, - ds_srcd_prdcr_dw_0p1, - ds_srcd_prdcr_dw_1p1, - ds_srcd_prdcr_dw_2p1, - ds_srcd_tag_0p1, - ds_srcd_tag_1p1, - ds_srcd_tag_2p1, - ds_srcd_tag_vld_0p1, - ds_srcd_tag_vld_1p1, - ds_srcd_tag_vld_2p1, - ds_srcp_tag_0p1, - ds_srcp_tag_1p1, - ds_srcp_tag_2p1, - ds_srcp_tag_vld_0p1, - ds_srcp_tag_vld_1p1, - ds_srcp_tag_vld_2p1, - ls_resx_data_cancel_w1, - ls_resx_data_cancel_w2, - ls_resx_data_w2, - ls_resx_dw_w0, - ls_resx_dw_w1, - ls_resx_tag_vld_w0, - ls_resx_tag_vld_w1, - ls_resx_tag_w0, - ls_resx_tag_w1, - ls_resy_data_cancel_w1, - ls_resy_data_cancel_w2, - ls_resy_data_w2, - ls_resy_dw_w0, - ls_resy_dw_w1, - ls_resy_tag_vld_w0, - ls_resy_tag_vld_w1, - ls_resy_tag_w0, - ls_resy_tag_w1, - mx_resp_data_w2, - mx_resp_tag_vld_w0, - mx_resp_tag_vld_w1, - mx_resp_tag_w0, - mx_resp_tag_w1, - sx_ldxcancel_sel_jw0, - sx_ldxcancel_sel_jw1, - sx_ldxcancel_sel_kw0, - sx_ldxcancel_sel_kw1, - sx_resp_data_jw2, - sx_resp_data_kw2, - sx_resp_tag_jw0, - sx_resp_tag_jw1, - sx_resp_tag_kw0, - sx_resp_tag_kw1, - sx_resp_tag_vld_jw0, - sx_resp_tag_vld_jw1, - sx_resp_tag_vld_kw0, - sx_resp_tag_vld_kw1, - sx_uop_vld_jw0, - sx_uop_vld_kw0 - ); - -wire [3:0] unused1; - - // outputs - output cx_active; - output [2:0] cx_credit_j; - output [2:0] cx_credit_k; - output [4:0] cx_dstp_tag_ke1; - output cx_dstp_tag_vld_ke1; - output [3:0] cx_resp_data_w1; - output [5:0] cx_resp_qfbit_gid_w1; - output cx_resp_qfbit_vld_w1; - output [6:0] cx_resp_qfbit_w2; - output cx_resp_tag_vld_w0; - output [4:0] cx_resp_tag_w0; - output [63:0] cx_resx_data_w2; - output cx_resx_dw_w1; - output [5:0] cx_resx_qfbit_gid_w1; - output cx_resx_qfbit_vld_w1; - output [6:0] cx_resx_qfbit_w2; - output cx_resx_tag_vld_w1; - output [6:0] cx_resx_tag_w1; - output [63:0] cx_resy_data_w2; - output cx_resy_dw_w1; - output [5:0] cx_resy_qfbit_gid_w1; - output cx_resy_qfbit_vld_w1; - output [6:0] cx_resy_qfbit_w2; - output cx_resy_tag_vld_w1; - output [6:0] cx_resy_tag_w1; - output [63:0] cx_resz_data_w2; - output cx_resz_dw_w1; - output [5:0] cx_resz_qfbit_gid_w1; - output cx_resz_qfbit_vld_w1; - output [6:0] cx_resz_qfbit_w2; - output cx_resz_tag_vld_w1; - output [6:0] cx_resz_tag_w1; - - // inputs - input ck_areset; - input ck_gclkcx; - input ck_reset1_n_cx; - input dftrstdisable_cpu; - input dftse_cpu; - input ds_cx_aarch32_state; - input ds_cx_aarch64_state; - input ds_cx_cpuactlr_frc_cpu_rcg_active; - input [4:0] ds_cx_dstp_tag_jp2; - input [4:0] ds_cx_dstp_tag_kp2; - input ds_cx_dstp_tag_vld_jp2; - input ds_cx_dstp_tag_vld_kp2; - input ds_cx_dstx_dw_jp2; - input ds_cx_dstx_dw_kp2; - input [6:0] ds_cx_dstx_tag_jp2; - input [6:0] ds_cx_dstx_tag_kp2; - input ds_cx_dstx_tag_vld_jp2; - input ds_cx_dstx_tag_vld_kp2; - input ds_cx_dsty_dw_jp2; - input ds_cx_dsty_dw_kp2; - input [6:0] ds_cx_dsty_tag_jp2; - input [6:0] ds_cx_dsty_tag_kp2; - input ds_cx_dsty_tag_vld_jp2; - input ds_cx_dsty_tag_vld_kp2; - input [6:0] ds_cx_flush_gid; - input ds_cx_flush_seq; - input ds_cx_flush_u1; - input ds_cx_fpscr_ahp; - input ds_cx_fpscr_dn; - input ds_cx_fpscr_fz; - input [1:0] ds_cx_fpscr_rmode; - input [6:0] ds_cx_gid_jp2; - input [6:0] ds_cx_gid_kp2; - input [2:0] ds_cx_prt_sel_jp1; - input [2:0] ds_cx_prt_sel_kp1; - input [63:0] ds_cx_srca_data_jp2; - input [63:0] ds_cx_srca_data_kp2; - input [1:0] ds_cx_srca_data_vld_jp2; - input [1:0] ds_cx_srca_data_vld_kp2; - input [63:0] ds_cx_srcb_data_jp2; - input [63:0] ds_cx_srcb_data_kp2; - input [1:0] ds_cx_srcb_data_vld_jp2; - input [1:0] ds_cx_srcb_data_vld_kp2; - input [63:0] ds_cx_srcc_data_jp2; - input [63:0] ds_cx_srcc_data_kp2; - input [1:0] ds_cx_srcc_data_vld_jp2; - input [1:0] ds_cx_srcc_data_vld_kp2; - input [63:0] ds_cx_srcd_data_jp2; - input [63:0] ds_cx_srcd_data_kp2; - input [1:0] ds_cx_srcd_data_vld_jp2; - input [1:0] ds_cx_srcd_data_vld_kp2; - input [3:0] ds_cx_srcp_data_jp2; - input [3:0] ds_cx_srcp_data_kp2; - input ds_cx_srcp_data_vld_jp2; - input ds_cx_srcp_data_vld_kp2; - input ds_cx_swdw_nuke_jp2; - input ds_cx_swdw_nuke_kp2; - input [58:0] ds_cx_uop_ctl_jp2; - input [58:0] ds_cx_uop_ctl_kp2; - input ds_cx_uop_vld_jp2; - input ds_cx_uop_vld_kp2; - input ds_srca_dw_0p1; - input ds_srca_dw_1p1; - input ds_srca_dw_2p1; - input ds_srca_prdcr_dw_0p1; - input ds_srca_prdcr_dw_1p1; - input ds_srca_prdcr_dw_2p1; - input [6:0] ds_srca_tag_0p1; - input [6:0] ds_srca_tag_1p1; - input [6:0] ds_srca_tag_2p1; - input ds_srca_tag_vld_0p1; - input ds_srca_tag_vld_1p1; - input ds_srca_tag_vld_2p1; - input ds_srcb_dw_0p1; - input ds_srcb_dw_1p1; - input ds_srcb_dw_2p1; - input ds_srcb_prdcr_dw_0p1; - input ds_srcb_prdcr_dw_1p1; - input ds_srcb_prdcr_dw_2p1; - input [6:0] ds_srcb_tag_0p1; - input [6:0] ds_srcb_tag_1p1; - input [6:0] ds_srcb_tag_2p1; - input ds_srcb_tag_vld_0p1; - input ds_srcb_tag_vld_1p1; - input ds_srcb_tag_vld_2p1; - input ds_srcc_dw_0p1; - input ds_srcc_dw_1p1; - input ds_srcc_dw_2p1; - input ds_srcc_prdcr_dw_0p1; - input ds_srcc_prdcr_dw_1p1; - input ds_srcc_prdcr_dw_2p1; - input [6:0] ds_srcc_tag_0p1; - input [6:0] ds_srcc_tag_1p1; - input [6:0] ds_srcc_tag_2p1; - input ds_srcc_tag_vld_0p1; - input ds_srcc_tag_vld_1p1; - input ds_srcc_tag_vld_2p1; - input ds_srcd_dw_0p1; - input ds_srcd_dw_1p1; - input ds_srcd_dw_2p1; - input ds_srcd_prdcr_dw_0p1; - input ds_srcd_prdcr_dw_1p1; - input ds_srcd_prdcr_dw_2p1; - input [6:0] ds_srcd_tag_0p1; - input [6:0] ds_srcd_tag_1p1; - input [6:0] ds_srcd_tag_2p1; - input ds_srcd_tag_vld_0p1; - input ds_srcd_tag_vld_1p1; - input ds_srcd_tag_vld_2p1; - input [4:0] ds_srcp_tag_0p1; - input [4:0] ds_srcp_tag_1p1; - input [4:0] ds_srcp_tag_2p1; - input ds_srcp_tag_vld_0p1; - input ds_srcp_tag_vld_1p1; - input ds_srcp_tag_vld_2p1; - input ls_resx_data_cancel_w1; - input ls_resx_data_cancel_w2; - input [63:0] ls_resx_data_w2; - input ls_resx_dw_w0; - input ls_resx_dw_w1; - input ls_resx_tag_vld_w0; - input ls_resx_tag_vld_w1; - input [6:0] ls_resx_tag_w0; - input [6:0] ls_resx_tag_w1; - input ls_resy_data_cancel_w1; - input ls_resy_data_cancel_w2; - input [63:0] ls_resy_data_w2; - input ls_resy_dw_w0; - input ls_resy_dw_w1; - input ls_resy_tag_vld_w0; - input ls_resy_tag_vld_w1; - input [6:0] ls_resy_tag_w0; - input [6:0] ls_resy_tag_w1; - input [3:0] mx_resp_data_w2; - input mx_resp_tag_vld_w0; - input mx_resp_tag_vld_w1; - input [4:0] mx_resp_tag_w0; - input [4:0] mx_resp_tag_w1; - input sx_ldxcancel_sel_jw0; - input sx_ldxcancel_sel_jw1; - input sx_ldxcancel_sel_kw0; - input sx_ldxcancel_sel_kw1; - input [3:0] sx_resp_data_jw2; - input [3:0] sx_resp_data_kw2; - input [4:0] sx_resp_tag_jw0; - input [4:0] sx_resp_tag_jw1; - input [4:0] sx_resp_tag_kw0; - input [4:0] sx_resp_tag_kw1; - input sx_resp_tag_vld_jw0; - input sx_resp_tag_vld_jw1; - input sx_resp_tag_vld_kw0; - input sx_resp_tag_vld_kw1; - input sx_uop_vld_jw0; - input sx_uop_vld_kw0; - - // wires - wire acc_size_eq64_e3_q; - wire acc_size_ge32_e3_q; - wire acc_size_ne08_e3_q; - wire addj_active; - wire addk_active; - wire aesd_e1; - wire aesdimc_e1; - wire aese_e1; - wire aesemc_e1; - wire aesimc_e1; - wire aesmc_e1; - wire ahp_mode_e1_q; - wire [3:0] c00_x_sel_e1; - wire c00_y_sel_e1; - wire [5:0] c01_x_sel_e1; - wire [2:0] c01_y_sel_e1; - wire [5:0] c02_x_sel_e1; - wire [2:0] c02_y_sel_e1; - wire [6:0] c03_x_sel_e1; - wire [4:0] c03_y_sel_e1; - wire [5:0] c04_x_sel_e1; - wire [2:0] c04_y_sel_e1; - wire [7:0] c05_x_sel_e1; - wire [4:0] c05_y_sel_e1; - wire [5:0] c06_x_sel_e1; - wire [4:0] c06_y_sel_e1; - wire [6:0] c07_x_sel_e1; - wire [4:0] c07_y_sel_e1; - wire [6:0] c08_x_sel_e1; - wire [2:0] c08_y_sel_e1; - wire [8:0] c09_x_sel_e1; - wire [5:0] c09_y_sel_e1; - wire [8:0] c10_x_sel_e1; - wire [5:0] c10_y_sel_e1; - wire [9:0] c11_x_sel_e1; - wire [7:0] c11_y_sel_e1; - wire [7:0] c12_x_sel_e1; - wire [5:0] c12_y_sel_e1; - wire [9:0] c13_x_sel_e1; - wire [6:0] c13_y_sel_e1; - wire [7:0] c14_x_sel_e1; - wire [6:0] c14_y_sel_e1; - wire [7:0] c15_x_sel_e1; - wire [6:0] c15_y_sel_e1; - wire ccpass_ke2; - wire ck_gclkcx_crypt; - wire ck_gclkcx_floatj; - wire ck_gclkcx_floatk; - wire ck_gclkcx_intj; - wire ck_gclkcx_intk; - wire crp3_vld_je1; - wire crypt2_active; - wire [127:0] crypt2_out_e3_q; - wire crypt2_vld_e1; - wire crypt3_active; - wire [127:0] crypt3_out_e6_q; - wire crypt3_vld0_e1; - wire crypt3_vld1_e1; - wire cvtj_active; - wire [3:0] cx_acc_type_je1; - wire [3:1] cx_acc_type_je2; - wire [3:0] cx_acc_type_ke1; - wire [3:1] cx_acc_type_ke2; - wire cx_ccpass_je1; - wire cx_ccpass_ke1; - wire cx_ctl_dp_fp_valid_ji1; - wire cx_ctl_dp_fp_valid_ki1; - wire cx_ctl_dp_int_valid_ji1; - wire cx_ctl_dp_int_valid_ki1; - wire [4:0] cx_dst_sel_je1; - wire [4:0] cx_dst_sel_ke1; - wire [4:0] cx_dstp_tag_je1; - wire [4:0] cx_dstp_tag_ke1; - wire cx_dstp_tag_vld_je1; - wire cx_dstp_tag_vld_ke1; - wire cx_dstx_dw_je1; - wire cx_dstx_dw_ke1; - wire [6:0] cx_dstx_tag_je1; - wire [6:0] cx_dstx_tag_je2; - wire [6:0] cx_dstx_tag_ke1; - wire [6:0] cx_dstx_tag_ke2; - wire cx_dstx_tag_vld_je1; - wire cx_dstx_tag_vld_ke1; - wire cx_dsty_dw_je1; - wire cx_dsty_dw_ke1; - wire [6:0] cx_dsty_tag_je1; - wire [6:0] cx_dsty_tag_ke1; - wire cx_dsty_tag_vld_je1; - wire cx_dsty_tag_vld_ke1; - wire [63:0] cx_fadd_srca_fp_data32_je1; - wire [63:0] cx_fadd_srca_fp_data32_ke1; - wire [63:0] cx_fadd_srca_fp_data64_je1; - wire [63:0] cx_fadd_srca_fp_data64_ke1; - wire [55:0] cx_fadd_srcb_fp_data32_h_je1; - wire [55:0] cx_fadd_srcb_fp_data32_h_ke1; - wire [55:0] cx_fadd_srcb_fp_data32_l_je1; - wire [55:0] cx_fadd_srcb_fp_data32_l_ke1; - wire [116:0] cx_fadd_srcb_fp_data64_je1; - wire [116:0] cx_fadd_srcb_fp_data64_ke1; - wire [63:0] cx_fadd_srcc_fp_data32_je1; - wire [63:0] cx_fadd_srcc_fp_data32_ke1; - wire [31:0] cx_fadd_srcc_fp_data64_je1; - wire [31:0] cx_fadd_srcc_fp_data64_ke1; - wire [31:0] cx_fadd_srcd_fp_data64_je1; - wire [31:0] cx_fadd_srcd_fp_data64_ke1; - wire [63:0] cx_fmul_srca_fp_data32_je1; - wire [63:0] cx_fmul_srca_fp_data32_ke1; - wire [63:0] cx_fmul_srcb_fp_data32_je1; - wire [63:0] cx_fmul_srcb_fp_data32_ke1; - wire [6:0] cx_gid_je1; - wire [6:0] cx_gid_ke1; - wire [12:0] cx_imac_cmd_e1; - wire cx_imac_vld_e1; - wire cx_ls_resx_data_cancel_w2; - wire cx_ls_resx_data_cancel_w3; - wire cx_ls_resx_dw_w1; - wire cx_ls_resx_dw_w2; - wire cx_ls_resx_tag_vld_w1; - wire cx_ls_resx_tag_vld_w2; - wire [6:0] cx_ls_resx_tag_w1; - wire [6:0] cx_ls_resx_tag_w2; - wire cx_ls_resy_data_cancel_w2; - wire cx_ls_resy_data_cancel_w3; - wire cx_ls_resy_dw_w1; - wire cx_ls_resy_dw_w2; - wire cx_ls_resy_tag_vld_w1; - wire cx_ls_resy_tag_vld_w2; - wire [6:0] cx_ls_resy_tag_w1; - wire [6:0] cx_ls_resy_tag_w2; - wire [4:0] cx_mla_fwd_sel_je1; - wire [4:0] cx_mla_fwd_sel_je2; - wire [4:0] cx_mla_fwd_sel_je3; - wire [4:0] cx_mla_fwd_sel_ke1; - wire [4:0] cx_mla_fwd_sel_ke2; - wire [4:0] cx_mla_fwd_sel_ke3; - wire cx_mx_resp_tag_vld_w1; - wire cx_mx_resp_tag_vld_w2; - wire [4:0] cx_mx_resp_tag_w1; - wire [4:0] cx_mx_resp_tag_w2; - wire [2:0] cx_region_je1; - wire [2:0] cx_region_ke1; - wire cx_res128_je1; - wire cx_res128_ke1; - wire cx_reset3; - wire [3:0] cx_resp_data_w1; - wire [3:0] cx_resp_data_w2; - wire cx_resp_tag_vld_w0; - wire cx_resp_tag_vld_w1; - wire cx_resp_tag_vld_w2; - wire [4:0] cx_resp_tag_w0; - wire [4:0] cx_resp_tag_w1; - wire [4:0] cx_resp_tag_w2; - wire [63:0] cx_resx_data_w2; - wire cx_resx_dw_w0; - wire cx_resx_dw_w0m1; - wire cx_resx_dw_w1; - wire cx_resx_dw_w2; - wire [2:0] cx_resx_region_w0m1; - wire [49:32] cx_resx_sel_dec_jw0; - wire [13:0] cx_resx_sel_dec_kw0; - wire cx_resx_selj_w0; - wire cx_resx_tag_vld_w0; - wire cx_resx_tag_vld_w0m1; - wire cx_resx_tag_vld_w1; - wire cx_resx_tag_vld_w2; - wire [6:0] cx_resx_tag_w0; - wire [6:0] cx_resx_tag_w0m1; - wire [6:0] cx_resx_tag_w1; - wire [6:0] cx_resx_tag_w2; - wire [63:0] cx_resy_data_w2; - wire cx_resy_dw_w0; - wire cx_resy_dw_w0m1; - wire cx_resy_dw_w1; - wire cx_resy_dw_w2; - wire [2:0] cx_resy_region_w0m1; - wire [49:32] cx_resy_sel_dec_jw0; - wire [13:0] cx_resy_sel_dec_kw0; - wire cx_resy_selj_w0; - wire cx_resy_tag_vld_w0; - wire cx_resy_tag_vld_w0m1; - wire cx_resy_tag_vld_w1; - wire cx_resy_tag_vld_w2; - wire [6:0] cx_resy_tag_w0; - wire [6:0] cx_resy_tag_w0m1; - wire [6:0] cx_resy_tag_w1; - wire [6:0] cx_resy_tag_w2; - wire [63:0] cx_resz_data_w2; - wire cx_resz_dw_w0; - wire cx_resz_dw_w0m1; - wire cx_resz_dw_w1; - wire cx_resz_dw_w2; - wire [2:0] cx_resz_region_w0m1; - wire [49:32] cx_resz_sel_dec_jw0; - wire [13:0] cx_resz_sel_dec_kw0; - wire cx_resz_selj_w0; - wire cx_resz_tag_vld_w0; - wire cx_resz_tag_vld_w0m1; - wire cx_resz_tag_vld_w1; - wire cx_resz_tag_vld_w2; - wire [6:0] cx_resz_tag_w0; - wire [6:0] cx_resz_tag_w0m1; - wire [6:0] cx_resz_tag_w1; - wire [6:0] cx_resz_tag_w2; - wire [63:0] cx_srca_crypt_data_je1; - wire [63:0] cx_srca_data_ji1; - wire [63:0] cx_srca_data_ki1; - wire cx_srca_en_je1; - wire cx_srca_en_ke1; - wire [63:0] cx_srca_fp_data32_je1; - wire [63:0] cx_srca_fp_data32_ke1; - wire [63:0] cx_srca_fp_data64_je1; - wire [63:0] cx_srca_fp_data64_ke1; - wire cx_srca_fp_h_en_ji1; - wire cx_srca_fp_h_en_ki1; - wire cx_srca_fp_l_en_ji1; - wire cx_srca_fp_l_en_ki1; - wire [63:0] cx_srca_int_data_je1; - wire [63:0] cx_srca_int_data_ke1; - wire cx_srca_int_h_en_ji1; - wire cx_srca_int_h_en_ki1; - wire cx_srca_int_l_en_ji1; - wire cx_srca_int_l_en_ki1; - wire [63:0] cx_srcb_crypt_data_je1; - wire [63:0] cx_srcb_data_ji1; - wire [63:0] cx_srcb_data_ki1; - wire cx_srcb_en_je1; - wire cx_srcb_en_ke1; - wire [63:0] cx_srcb_fp_data32_je1; - wire [63:0] cx_srcb_fp_data64_je1; - wire [63:0] cx_srcb_fp_data64_ke1; - wire cx_srcb_fp_h_en_ji1; - wire cx_srcb_fp_h_en_ki1; - wire cx_srcb_fp_l_en_ji1; - wire cx_srcb_fp_l_en_ki1; - wire [63:0] cx_srcb_int_data_je1; - wire [63:0] cx_srcb_int_data_ke1; - wire cx_srcb_int_h_en_ji1; - wire cx_srcb_int_h_en_ki1; - wire cx_srcb_int_l_en_ji1; - wire cx_srcb_int_l_en_ki1; - wire [63:0] cx_srcc_crypt_data_je1; - wire [63:0] cx_srcc_data_ji1; - wire [63:0] cx_srcc_data_ke3; - wire [63:0] cx_srcc_data_ki1; - wire cx_srcc_en_je1; - wire cx_srcc_en_ke1; - wire [63:0] cx_srcc_fp_data32_je1; - wire [63:0] cx_srcc_fp_data32_ke1; - wire cx_srcc_fp_h_en_ji1; - wire cx_srcc_fp_h_en_ki1; - wire cx_srcc_fp_l_en_ji1; - wire cx_srcc_fp_l_en_ki1; - wire [63:0] cx_srcc_int_data_je1; - wire [63:0] cx_srcc_int_data_ke1; - wire cx_srcc_int_h_en_ji1; - wire cx_srcc_int_h_en_ki1; - wire cx_srcc_int_l_en_ji1; - wire cx_srcc_int_l_en_ki1; - wire [63:0] cx_srcd_crypt_data_je1; - wire [63:0] cx_srcd_data_ji1; - wire [63:0] cx_srcd_data_ke3; - wire [63:0] cx_srcd_data_ki1; - wire cx_srcd_en_je1; - wire cx_srcd_en_ke1; - wire [31:0] cx_srcd_fp_data32_je1; - wire [31:0] cx_srcd_fp_data32_ke1; - wire cx_srcd_fp_h_en_ji1; - wire cx_srcd_fp_h_en_ki1; - wire cx_srcd_fp_l_en_ji1; - wire cx_srcd_fp_l_en_ki1; - wire [63:0] cx_srcd_int_data_je1; - wire [63:0] cx_srcd_int_data_ke1; - wire cx_srcd_int_h_en_ji1; - wire cx_srcd_int_h_en_ki1; - wire cx_srcd_int_l_en_ji1; - wire cx_srcd_int_l_en_ki1; - wire [3:0] cx_srcp_data_je1; - wire [3:0] cx_srcp_data_ke1; - wire cx_sx_ldxcancel_sel_jw1; - wire cx_sx_ldxcancel_sel_kw1; - wire [4:0] cx_sx_resp_tag_jw1; - wire [4:0] cx_sx_resp_tag_jw2; - wire [4:0] cx_sx_resp_tag_kw1; - wire [4:0] cx_sx_resp_tag_kw2; - wire cx_sx_resp_tag_vld_jw1; - wire cx_sx_resp_tag_vld_jw2; - wire cx_sx_resp_tag_vld_kw1; - wire cx_sx_resp_tag_vld_kw2; - wire [58:0] cx_uop_ctl_ji1; - wire [58:0] cx_uop_ctl_ki1; - wire [2:0] cx_uop_res_latency_je1; - wire [2:0] cx_uop_res_latency_ke1; - wire cx_uop_vld_je1; - wire cx_uop_vld_ji1; - wire cx_uop_vld_ke1; - wire cx_uop_vld_ki1; - wire dn_fadd_je1; - wire dn_fadd_ke1; - wire dn_je1; - wire dn_ke1; - wire dn_raw_e1_q; - wire [39:0] dstx_bytesel_je; - wire [39:0] dstx_bytesel_ke; - wire [39:0] dsty_bytesel_je; - wire [39:0] dsty_bytesel_ke; - wire [5:0] fadd32_ex_h_je4; - wire [5:0] fadd32_ex_h_ke4; - wire [5:0] fadd32_ex_l_je4; - wire [5:0] fadd32_ex_l_ke4; - wire [5:0] fadd64_ex_je4; - wire [5:0] fadd64_ex_ke4; - wire fadd_absin_je1; - wire fadd_absin_ke1; - wire fadd_absout_je1; - wire fadd_absout_ke1; - wire fadd_ccpass_je1; - wire fadd_ccpass_ke1; - wire fadd_hazard1_j; - wire fadd_hazard1_k; - wire [2:0] fadd_srca_sel_h_je1; - wire [2:0] fadd_srca_sel_h_ke1; - wire fadd_srca_sel_l_je1; - wire fadd_srca_sel_l_ke1; - wire [2:0] fadd_srcb_sel_h_je1; - wire [2:0] fadd_srcb_sel_h_ke1; - wire [2:0] fadd_srcb_sel_l_je1; - wire [2:0] fadd_srcb_sel_l_ke1; - wire fadd_sub_je1; - wire fadd_sub_ke1; - wire [2:0] fadd_vld_je1; - wire [2:0] fadd_vld_je4; - wire [2:0] fadd_vld_ke1; - wire [2:0] fadd_vld_ke4; - wire [31:0] faddout32_h_je4; - wire [31:0] faddout32_h_ke4; - wire [31:0] faddout32_l_je4; - wire [31:0] faddout32_l_ke4; - wire [63:0] faddout64_je4; - wire [63:0] faddout64_ke4; - wire fcvt_cvt_f_to_f_je1; - wire fcvt_cvt_f_to_i_je1; - wire fcvt_cvt_i_to_f_je1; - wire fcvt_cvts_je1; - wire [5:0] fcvt_ex_h_e3; - wire [5:0] fcvt_ex_l_e3; - wire fcvt_frint_je1; - wire fcvt_hp_sel_top_je1; - wire fcvt_imm_je1; - wire [5:0] fcvt_immv_je1; - wire [1:0] fcvt_isize_je1; - wire fcvt_noixc_je1; - wire [1:0] fcvt_osize_je1; - wire fcvt_recpe_je1; - wire fcvt_recpx_je1; - wire fcvt_restf_je1; - wire fcvt_rsqrte_je1; - wire fcvt_scalar_je1; - wire [1:0] fcvt_vld_je1; - wire [1:0] fcvt_vld_je3; - wire [127:0] fcvtout_e3; - wire fdiv_active; - wire [1:0] fdiv_busy_q; - wire [2:0] fdiv_cmd_e1; - wire [1:0] fdiv_done; - wire [1:0] fdiv_done_ack; - wire [1:0] fdiv_done_hold; - wire [1:0] fdiv_flush; - wire [1:0] fdiv_scalar; - wire fdiv_scalar_je1; - wire [1:0] fdiv_uop_vld_je1; - wire [5:0] fdivexc32_q; - wire [5:0] fdivexc64_q; - wire [31:0] fdivout32_q; - wire [63:0] fdivout64_q; - wire [63:0] fmla_acc_je4; - wire [63:0] fmla_acc_ke4; - wire fmla_fused_je1; - wire fmla_fused_je4; - wire fmla_fused_ke1; - wire fmla_fused_ke4; - wire [1:0] fmla_fwd_je3; - wire [1:0] fmla_fwd_je4; - wire [1:0] fmla_fwd_ke3; - wire [1:0] fmla_fwd_ke4; - wire fmla_je1; - wire fmla_je2; - wire fmla_je3; - wire fmla_je4; - wire fmla_ke1; - wire fmla_ke2; - wire fmla_ke3; - wire fmla_ke4; - wire fmla_negopa_je4; - wire fmla_negopa_ke4; - wire [4:0] fmul32_ex_h_je4; - wire [4:0] fmul32_ex_h_ke4; - wire [4:0] fmul32_ex_l_je4; - wire [4:0] fmul32_ex_l_ke4; - wire [4:0] fmul64_ex_je4; - wire [4:0] fmul64_ex_ke4; - wire fmul_c_on_d_je1; - wire fmul_c_on_d_ke1; - wire fmul_div_je4; - wire fmul_div_ke4; - wire fmul_ext_je1; - wire fmul_ext_ke1; - wire fmul_f_exp_ovfl_h_je4; - wire fmul_f_exp_ovfl_h_ke4; - wire fmul_f_exp_ovfl_je4; - wire fmul_f_exp_ovfl_ke4; - wire fmul_f_exp_ovfl_l_je4; - wire fmul_f_exp_ovfl_l_ke4; - wire fmul_f_infnanzero_h_je4; - wire fmul_f_infnanzero_h_ke4; - wire fmul_f_infnanzero_je4; - wire fmul_f_infnanzero_ke4; - wire fmul_f_infnanzero_l_je4; - wire fmul_f_infnanzero_l_ke4; - wire fmul_f_prod_inf_zero_h_je4; - wire fmul_f_prod_inf_zero_h_ke4; - wire fmul_f_prod_inf_zero_je4; - wire fmul_f_prod_inf_zero_ke4; - wire fmul_f_prod_inf_zero_l_je4; - wire fmul_f_prod_inf_zero_l_ke4; - wire fmul_negmul_je1; - wire fmul_negmul_ke1; - wire fmul_srca_sel_l_je1; - wire fmul_srca_sel_l_ke1; - wire fmul_srcb_sel_h_je1; - wire fmul_srcb_sel_h_ke1; - wire fmul_srcb_sel_l_je1; - wire fmul_srcb_sel_l_ke1; - wire fmul_step_je1; - wire fmul_step_ke1; - wire [2:0] fmul_vld_je1; - wire [2:0] fmul_vld_je2; - wire [2:0] fmul_vld_je3; - wire [2:0] fmul_vld_je4; - wire [2:0] fmul_vld_ke1; - wire [2:0] fmul_vld_ke2; - wire [2:0] fmul_vld_ke3; - wire [2:0] fmul_vld_ke4; - wire fmulj_active; - wire fmulk_active; - wire [55:0] fmulout32_h_je4; - wire [55:0] fmulout32_h_ke4; - wire [55:0] fmulout32_l_je4; - wire [55:0] fmulout32_l_ke4; - wire [116:0] fmulout64_je4; - wire [116:0] fmulout64_ke4; - wire fsqrt_active; - wire [1:0] fsqrt_busy_q; - wire [2:0] fsqrt_cmd_e1; - wire [1:0] fsqrt_done; - wire [1:0] fsqrt_done_ack; - wire [1:0] fsqrt_done_hold; - wire [1:0] fsqrt_flush; - wire [1:0] fsqrt_scalar; - wire fsqrt_scalar_ke1; - wire [1:0] fsqrt_uop_vld_ke1; - wire [5:0] fsqrtexc32_q; - wire [5:0] fsqrtexc64_q; - wire [31:0] fsqrtout32_q; - wire [63:0] fsqrtout64_q; - wire fz_fadd_je1; - wire fz_fadd_ke1; - wire fz_je1; - wire fz_ke1; - wire fz_raw_e1_q; - wire [7:1] iacc_cin_sel_e3_q; - wire iacc_en_e1; - wire iacc_en_e2; - wire iacc_en_e4; - wire iacc_shfsel_e2; - wire iacce4_fwd_e2; - wire ialu_acc_en_ke1; - wire [21:0] ialu_ctl_je1; - wire [21:0] ialu_ctl_ke1; - wire ialu_en_je1; - wire ialu_en_ke1; - wire ialu_en_ke3; - wire [1:0] ialu_esize_je1; - wire [1:0] ialu_esize_ke1; - wire ialu_fp_dn_je1; - wire ialu_fp_dn_ke1; - wire ialu_fp_fz_je1; - wire ialu_fp_fz_ke1; - wire [4:0] ialu_fpex_je3_q; - wire [4:0] ialu_fpex_ke3_q; - wire [3:0] ialu_nzcv_ke3_q; - wire ialu_qc_je3_q; - wire ialu_qc_ke3_q; - wire ialu_qc_vld_je2; - wire ialu_qc_vld_ke2; - wire ialu_res128_je1_q; - wire ialu_res128_ke1_q; - wire ialuj_active; - wire ialuk_active; - wire [127:0] ialuout_je3_q; - wire [127:0] ialuout_ke3_q; - wire imac_active; - wire imac_qc_e4_q; - wire imac_qc_vld_e3; - wire [6:0] iqj_flush_gid; - wire iqj_flush_u2; - wire [6:0] iqk_flush_gid; - wire iqk_flush_u2; - wire [1:0] ired_esize_ke1; - wire ired_long_ke1; - wire ired_opb_en_ke1; - wire ired_seladd_ke1; - wire ired_selmax_ke1; - wire ired_selmin_ke1; - wire ired_selusgn_ke1; - wire ired_vrop_ke1; - wire iredk_active; - wire [63:0] iredout_ke2; - wire ishf3_iss_e2; - wire ishf3_iss_e3; - wire ishf3_uiss_e2; - wire ishf_active; - wire ishf_imm_e1; - wire [7:0] ishf_immv_e1; - wire ishf_insert_e1; - wire ishf_iss_e1; - wire ishf_iss_e2; - wire ishf_left_e1; - wire ishf_narrow_e1; - wire ishf_qc_e4_q; - wire ishf_qc_vld_e3; - wire ishf_round_e1; - wire [2:0] ishf_s1_sel_e1; - wire [2:0] ishf_s2_sel_e1; - wire [3:0] ishf_s3_sel_e1; - wire [2:0] ishf_s4_sel_e1; - wire [3:0] ishf_s5_sel_e1; - wire [3:0] ishf_s6_sel_e1; - wire [4:0] ishf_s7_sel_e1; - wire ishf_saturate_e1; - wire ishf_scalar_e1; - wire ishf_sel16_e1; - wire ishf_sel32_e1; - wire ishf_sel64_e1; - wire ishf_sel8_e1; - wire ishf_selqsat_e3; - wire ishf_signed_e1; - wire ishf_stous_e1; - wire ishf_uiss_e2; - wire ishf_widen_e1; - wire [127:0] ishfaccout_e4_q; - wire [127:0] ishfout_e3_q; - wire issq_active; - wire issq_crypt_active; - wire issq_floatj_active; - wire issq_floatk_active; - wire issq_intj_active; - wire issq_intk_active; - wire [127:0] iwbout_e4_q; - wire [127:0] lspout_je3_q; - wire [127:0] lspout_ke3_q; - wire perm_en_je1; - wire perm_en_je2; - wire perm_en_ke1; - wire perm_en_ke2; - wire perm_opa_en_je1; - wire perm_opa_en_ke1; - wire perm_opb_en_je1; - wire perm_opb_en_ke1; - wire perm_opc_en_je1; - wire perm_opc_en_ke1; - wire perm_opd_en_je1; - wire perm_opd_en_ke1; - wire [2:0] perm_sign_sel0_je1; - wire [2:0] perm_sign_sel0_ke1; - wire [2:0] perm_sign_sel1_je1; - wire [2:0] perm_sign_sel1_ke1; - wire [2:0] perm_sign_sel2_je1; - wire [2:0] perm_sign_sel2_ke1; - wire [2:0] perm_sign_sel3_je1; - wire [2:0] perm_sign_sel3_ke1; - wire perm_uen_je1; - wire perm_uen_je2; - wire perm_uen_ke1; - wire perm_uen_ke2; - wire pmull_e1; - wire res128_e2; - wire [1:0] rmode_fadd_je1; - wire [1:0] rmode_fadd_ke1; - wire [2:0] rmode_fcvt_je1; - wire [1:0] rmode_fpscr_e1_q; - wire [1:0] rmode_je1; - wire [1:0] rmode_ke1; - wire selusgn_je1_q; - wire selusgn_ke1_q; - wire sha1c_e1; - wire sha1h_e1; - wire sha1m_e1; - wire sha1p_e1; - wire sha1su1_e1; - wire sha256h2_e1; - wire sha256h_e1; - wire sha256su0_e1; - wire sha256su1_e1; - wire shf_size_eq64_e3_q; - wire shf_size_ge32_e3_q; - wire shf_size_ne08_e3_q; - wire [11:1] srca_dec_hi_sel_ji1; - wire [11:1] srca_dec_hi_sel_ki1; - wire [11:1] srca_dec_sel_ji1; - wire [11:1] srca_dec_sel_ki1; - wire srca_hi_sel_ji1; - wire srca_hi_sel_ki1; - wire [11:1] srcb_dec_hi_sel_ji1; - wire [11:1] srcb_dec_hi_sel_ki1; - wire [11:1] srcb_dec_sel_ji1; - wire [11:1] srcb_dec_sel_ki1; - wire srcb_hi_sel_ji1; - wire srcb_hi_sel_ki1; - wire [11:1] srcc_dec_hi_sel_ji1; - wire [11:1] srcc_dec_hi_sel_ki1; - wire [11:1] srcc_dec_sel_ji1; - wire [11:1] srcc_dec_sel_ki1; - wire srcc_hi_sel_ji1; - wire srcc_hi_sel_ki1; - wire [11:1] srcd_dec_hi_sel_ji1; - wire [11:1] srcd_dec_hi_sel_ki1; - wire [11:1] srcd_dec_sel_ji1; - wire [11:1] srcd_dec_sel_ki1; - wire srcd_hi_sel_ji1; - wire srcd_hi_sel_ki1; - wire tbl_inst_je; - wire tbl_inst_ke; - wire tbltbx_qdest_je; - wire tbltbx_qdest_ke; - wire [3:0] tbltbx_reg_bitmask_je; - wire [3:0] tbltbx_reg_bitmask_ke; - wire tbx_inst_je; - wire tbx_inst_ke; - wire [2:0] uopnum_je; - wire [2:0] uopnum_ke; - wire vcmp_inst_je; - wire vcmp_inst_ke; - - maia_cx_rb urb( // outputs - .ahp_mode_e1_q (ahp_mode_e1_q), - .ck_gclkcx_crypt (ck_gclkcx_crypt), - .ck_gclkcx_floatj (ck_gclkcx_floatj), - .ck_gclkcx_floatk (ck_gclkcx_floatk), - .ck_gclkcx_intj (ck_gclkcx_intj), - .ck_gclkcx_intk (ck_gclkcx_intk), - .cx_acc_type_je2 (cx_acc_type_je2[3:1]), - .cx_acc_type_ke2 (cx_acc_type_ke2[3:1]), - .cx_active (cx_active), - .cx_dstx_tag_je2 (cx_dstx_tag_je2[6:0]), - .cx_dstx_tag_ke2 (cx_dstx_tag_ke2[6:0]), - .cx_ls_resx_data_cancel_w2 (cx_ls_resx_data_cancel_w2), - .cx_ls_resx_data_cancel_w3 (cx_ls_resx_data_cancel_w3), - .cx_ls_resx_dw_w1 (cx_ls_resx_dw_w1), - .cx_ls_resx_dw_w2 (cx_ls_resx_dw_w2), - .cx_ls_resx_tag_vld_w1 (cx_ls_resx_tag_vld_w1), - .cx_ls_resx_tag_vld_w2 (cx_ls_resx_tag_vld_w2), - .cx_ls_resx_tag_w1 (cx_ls_resx_tag_w1[6:0]), - .cx_ls_resx_tag_w2 (cx_ls_resx_tag_w2[6:0]), - .cx_ls_resy_data_cancel_w2 (cx_ls_resy_data_cancel_w2), - .cx_ls_resy_data_cancel_w3 (cx_ls_resy_data_cancel_w3), - .cx_ls_resy_dw_w1 (cx_ls_resy_dw_w1), - .cx_ls_resy_dw_w2 (cx_ls_resy_dw_w2), - .cx_ls_resy_tag_vld_w1 (cx_ls_resy_tag_vld_w1), - .cx_ls_resy_tag_vld_w2 (cx_ls_resy_tag_vld_w2), - .cx_ls_resy_tag_w1 (cx_ls_resy_tag_w1[6:0]), - .cx_ls_resy_tag_w2 (cx_ls_resy_tag_w2[6:0]), - .cx_mx_resp_tag_vld_w1 (cx_mx_resp_tag_vld_w1), - .cx_mx_resp_tag_vld_w2 (cx_mx_resp_tag_vld_w2), - .cx_mx_resp_tag_w1 (cx_mx_resp_tag_w1[4:0]), - .cx_mx_resp_tag_w2 (cx_mx_resp_tag_w2[4:0]), - .cx_reset3 (cx_reset3), - .cx_resp_data_w1 (cx_resp_data_w1[3:0]), - .cx_resp_data_w2 (cx_resp_data_w2[3:0]), - .cx_resp_qfbit_gid_w1 (cx_resp_qfbit_gid_w1[5:0]), - .cx_resp_qfbit_vld_w1 (cx_resp_qfbit_vld_w1), - .cx_resp_qfbit_w2 (cx_resp_qfbit_w2[6:0]), - .cx_resp_tag_vld_w0 (cx_resp_tag_vld_w0), - .cx_resp_tag_vld_w1 (cx_resp_tag_vld_w1), - .cx_resp_tag_vld_w2 (cx_resp_tag_vld_w2), - .cx_resp_tag_w0 (cx_resp_tag_w0[4:0]), - .cx_resp_tag_w1 (cx_resp_tag_w1[4:0]), - .cx_resp_tag_w2 (cx_resp_tag_w2[4:0]), - .cx_resx_dw_w0 (cx_resx_dw_w0), - .cx_resx_dw_w0m1 (cx_resx_dw_w0m1), - .cx_resx_dw_w1 (cx_resx_dw_w1), - .cx_resx_dw_w2 (cx_resx_dw_w2), - .cx_resx_qfbit_gid_w1 (cx_resx_qfbit_gid_w1[5:0]), - .cx_resx_qfbit_vld_w1 (cx_resx_qfbit_vld_w1), - .cx_resx_qfbit_w2 (cx_resx_qfbit_w2[6:0]), - .cx_resx_region_w0m1 (cx_resx_region_w0m1[2:0]), - .cx_resx_sel_dec_jw0 (cx_resx_sel_dec_jw0[49:32]), - .cx_resx_sel_dec_kw0 (cx_resx_sel_dec_kw0[13:0]), - .cx_resx_selj_w0 (cx_resx_selj_w0), - .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), - .cx_resx_tag_vld_w0m1 (cx_resx_tag_vld_w0m1), - .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), - .cx_resx_tag_vld_w2 (cx_resx_tag_vld_w2), - .cx_resx_tag_w0 (cx_resx_tag_w0[6:0]), - .cx_resx_tag_w0m1 (cx_resx_tag_w0m1[6:0]), - .cx_resx_tag_w1 (cx_resx_tag_w1[6:0]), - .cx_resx_tag_w2 (cx_resx_tag_w2[6:0]), - .cx_resy_dw_w0 (cx_resy_dw_w0), - .cx_resy_dw_w0m1 (cx_resy_dw_w0m1), - .cx_resy_dw_w1 (cx_resy_dw_w1), - .cx_resy_dw_w2 (cx_resy_dw_w2), - .cx_resy_qfbit_gid_w1 (cx_resy_qfbit_gid_w1[5:0]), - .cx_resy_qfbit_vld_w1 (cx_resy_qfbit_vld_w1), - .cx_resy_qfbit_w2 (cx_resy_qfbit_w2[6:0]), - .cx_resy_region_w0m1 (cx_resy_region_w0m1[2:0]), - .cx_resy_sel_dec_jw0 (cx_resy_sel_dec_jw0[49:32]), - .cx_resy_sel_dec_kw0 (cx_resy_sel_dec_kw0[13:0]), - .cx_resy_selj_w0 (cx_resy_selj_w0), - .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), - .cx_resy_tag_vld_w0m1 (cx_resy_tag_vld_w0m1), - .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), - .cx_resy_tag_vld_w2 (cx_resy_tag_vld_w2), - .cx_resy_tag_w0 (cx_resy_tag_w0[6:0]), - .cx_resy_tag_w0m1 (cx_resy_tag_w0m1[6:0]), - .cx_resy_tag_w1 (cx_resy_tag_w1[6:0]), - .cx_resy_tag_w2 (cx_resy_tag_w2[6:0]), - .cx_resz_dw_w0 (cx_resz_dw_w0), - .cx_resz_dw_w0m1 (cx_resz_dw_w0m1), - .cx_resz_dw_w1 (cx_resz_dw_w1), - .cx_resz_dw_w2 (cx_resz_dw_w2), - .cx_resz_qfbit_gid_w1 (cx_resz_qfbit_gid_w1[5:0]), - .cx_resz_qfbit_vld_w1 (cx_resz_qfbit_vld_w1), - .cx_resz_qfbit_w2 (cx_resz_qfbit_w2[6:0]), - .cx_resz_region_w0m1 (cx_resz_region_w0m1[2:0]), - .cx_resz_sel_dec_jw0 (cx_resz_sel_dec_jw0[49:32]), - .cx_resz_sel_dec_kw0 (cx_resz_sel_dec_kw0[13:0]), - .cx_resz_selj_w0 (cx_resz_selj_w0), - .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), - .cx_resz_tag_vld_w0m1 (cx_resz_tag_vld_w0m1), - .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), - .cx_resz_tag_vld_w2 (cx_resz_tag_vld_w2), - .cx_resz_tag_w0 (cx_resz_tag_w0[6:0]), - .cx_resz_tag_w0m1 (cx_resz_tag_w0m1[6:0]), - .cx_resz_tag_w1 (cx_resz_tag_w1[6:0]), - .cx_resz_tag_w2 (cx_resz_tag_w2[6:0]), - .cx_sx_ldxcancel_sel_jw1 (cx_sx_ldxcancel_sel_jw1), - .cx_sx_ldxcancel_sel_kw1 (cx_sx_ldxcancel_sel_kw1), - .cx_sx_resp_tag_jw1 (cx_sx_resp_tag_jw1[4:0]), - .cx_sx_resp_tag_jw2 (cx_sx_resp_tag_jw2[4:0]), - .cx_sx_resp_tag_kw1 (cx_sx_resp_tag_kw1[4:0]), - .cx_sx_resp_tag_kw2 (cx_sx_resp_tag_kw2[4:0]), - .cx_sx_resp_tag_vld_jw1 (cx_sx_resp_tag_vld_jw1), - .cx_sx_resp_tag_vld_jw2 (cx_sx_resp_tag_vld_jw2), - .cx_sx_resp_tag_vld_kw1 (cx_sx_resp_tag_vld_kw1), - .cx_sx_resp_tag_vld_kw2 (cx_sx_resp_tag_vld_kw2), - .dn_raw_e1_q (dn_raw_e1_q), - .fdiv_busy_q (fdiv_busy_q[1:0]), - .fdiv_done_hold (fdiv_done_hold[1:0]), - .fdiv_flush (fdiv_flush[1:0]), - .fdiv_scalar (fdiv_scalar[1:0]), - .fsqrt_busy_q (fsqrt_busy_q[1:0]), - .fsqrt_done_hold (fsqrt_done_hold[1:0]), - .fsqrt_flush (fsqrt_flush[1:0]), - .fsqrt_scalar (fsqrt_scalar[1:0]), - .fz_raw_e1_q (fz_raw_e1_q), - .iqj_flush_gid (iqj_flush_gid[6:0]), - .iqj_flush_u2 (iqj_flush_u2), - .iqk_flush_gid (iqk_flush_gid[6:0]), - .iqk_flush_u2 (iqk_flush_u2), - .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), - - // inputs - .ccpass_ke2 (ccpass_ke2), - .ck_areset (ck_areset), - .ck_gclkcx (ck_gclkcx), - .ck_reset1_n_cx (ck_reset1_n_cx), - .crypt2_active (crypt2_active), - .crypt3_active (crypt3_active), - .cx_acc_type_je1 (cx_acc_type_je1[3:0]), - .cx_acc_type_ke1 (cx_acc_type_ke1[3:0]), - .cx_ccpass_je1 (cx_ccpass_je1), - .cx_ccpass_ke1 (cx_ccpass_ke1), - .cx_dst_sel_je1 (cx_dst_sel_je1[4:0]), - .cx_dst_sel_ke1 (cx_dst_sel_ke1[4:0]), - .cx_dstp_tag_je1 (cx_dstp_tag_je1[4:0]), - .cx_dstp_tag_ke1 (cx_dstp_tag_ke1[4:0]), - .cx_dstp_tag_vld_je1 (cx_dstp_tag_vld_je1), - .cx_dstp_tag_vld_ke1 (cx_dstp_tag_vld_ke1), - .cx_dstx_dw_je1 (cx_dstx_dw_je1), - .cx_dstx_dw_ke1 (cx_dstx_dw_ke1), - .cx_dstx_tag_je1 (cx_dstx_tag_je1[6:0]), - .cx_dstx_tag_ke1 (cx_dstx_tag_ke1[6:0]), - .cx_dstx_tag_vld_je1 (cx_dstx_tag_vld_je1), - .cx_dstx_tag_vld_ke1 (cx_dstx_tag_vld_ke1), - .cx_dsty_dw_je1 (cx_dsty_dw_je1), - .cx_dsty_dw_ke1 (cx_dsty_dw_ke1), - .cx_dsty_tag_je1 (cx_dsty_tag_je1[6:0]), - .cx_dsty_tag_ke1 (cx_dsty_tag_ke1[6:0]), - .cx_dsty_tag_vld_je1 (cx_dsty_tag_vld_je1), - .cx_dsty_tag_vld_ke1 (cx_dsty_tag_vld_ke1), - .cx_gid_je1 (cx_gid_je1[6:0]), - .cx_gid_ke1 (cx_gid_ke1[6:0]), - .cx_region_je1 (cx_region_je1[2:0]), - .cx_region_ke1 (cx_region_ke1[2:0]), - .cx_uop_res_latency_je1 (cx_uop_res_latency_je1[2:0]), - .cx_uop_res_latency_ke1 (cx_uop_res_latency_ke1[2:0]), - .dftrstdisable_cpu (dftrstdisable_cpu), - .dftse_cpu (dftse_cpu), - .ds_cx_cpuactlr_frc_cpu_rcg_active (ds_cx_cpuactlr_frc_cpu_rcg_active), - .ds_cx_flush_gid (ds_cx_flush_gid[6:0]), - .ds_cx_flush_seq (ds_cx_flush_seq), - .ds_cx_flush_u1 (ds_cx_flush_u1), - .ds_cx_fpscr_ahp (ds_cx_fpscr_ahp), - .ds_cx_fpscr_dn (ds_cx_fpscr_dn), - .ds_cx_fpscr_fz (ds_cx_fpscr_fz), - .ds_cx_fpscr_rmode (ds_cx_fpscr_rmode[1:0]), - .fadd32_ex_h_je4 (fadd32_ex_h_je4[5:0]), - .fadd32_ex_h_ke4 (fadd32_ex_h_ke4[5:0]), - .fadd32_ex_l_je4 (fadd32_ex_l_je4[5:0]), - .fadd32_ex_l_ke4 (fadd32_ex_l_ke4[5:0]), - .fadd64_ex_je4 (fadd64_ex_je4[5:0]), - .fadd64_ex_ke4 (fadd64_ex_ke4[5:0]), - .fadd_vld_je4 (fadd_vld_je4[2:0]), - .fadd_vld_ke4 (fadd_vld_ke4[2:0]), - .faddj_active (addj_active), - .faddk_active (addk_active), - .fcvt_ex_h_je3 (fcvt_ex_h_e3[5:0]), - .fcvt_ex_l_je3 (fcvt_ex_l_e3[5:0]), - .fcvt_vld_je3 (fcvt_vld_je3[1:0]), - .fcvtj_active (cvtj_active), - .fdiv_done (fdiv_done[1:0]), - .fdiv_done_ack (fdiv_done_ack[1:0]), - .fdiv_scalar_je1 (fdiv_scalar_je1), - .fdiv_uop_vld_je1 (fdiv_uop_vld_je1[1:0]), - .fdivexc32_q (fdivexc32_q[5:0]), - .fdivexc64_q (fdivexc64_q[5:0]), - .fdivj_active (fdiv_active), - .fmul32_ex_h_je4 (fmul32_ex_h_je4[4:0]), - .fmul32_ex_h_ke4 (fmul32_ex_h_ke4[4:0]), - .fmul32_ex_l_je4 (fmul32_ex_l_je4[4:0]), - .fmul32_ex_l_ke4 (fmul32_ex_l_ke4[4:0]), - .fmul64_ex_je4 (fmul64_ex_je4[4:0]), - .fmul64_ex_ke4 (fmul64_ex_ke4[4:0]), - .fmul_vld_je4 (fmul_vld_je4[2:0]), - .fmul_vld_ke4 (fmul_vld_ke4[2:0]), - .fmulj_active (fmulj_active), - .fmulk_active (fmulk_active), - .fsqrt_done (fsqrt_done[1:0]), - .fsqrt_done_ack (fsqrt_done_ack[1:0]), - .fsqrt_scalar_ke1 (fsqrt_scalar_ke1), - .fsqrt_uop_vld_ke1 (fsqrt_uop_vld_ke1[1:0]), - .fsqrtexc32_q (fsqrtexc32_q[5:0]), - .fsqrtexc64_q (fsqrtexc64_q[5:0]), - .fsqrtk_active (fsqrt_active), - .ialu_fpex_je3_q (ialu_fpex_je3_q[4:0]), - .ialu_fpex_ke3_q (ialu_fpex_ke3_q[4:0]), - .ialu_nzcv_ke3_q (ialu_nzcv_ke3_q[3:0]), - .ialu_qc_je3_q (ialu_qc_je3_q), - .ialu_qc_ke3_q (ialu_qc_ke3_q), - .ialu_qc_vld_je2 (ialu_qc_vld_je2), - .ialu_qc_vld_ke2 (ialu_qc_vld_ke2), - .ialuj_active (ialuj_active), - .ialuk_active (ialuk_active), - .imac_qc_e4_q (imac_qc_e4_q), - .imac_qc_vld_e3 (imac_qc_vld_e3), - .imacj_active (imac_active), - .iredk_active (iredk_active), - .ishf_qc_e4_q (ishf_qc_e4_q), - .ishf_qc_vld_e3 (ishf_qc_vld_e3), - .ishfk_active (ishf_active), - .issq_active (issq_active), - .issq_crypt_active (issq_crypt_active), - .issq_floatj_active (issq_floatj_active), - .issq_floatk_active (issq_floatk_active), - .issq_intj_active (issq_intj_active), - .issq_intk_active (issq_intk_active), - .ls_resx_data_cancel_w1 (ls_resx_data_cancel_w1), - .ls_resx_data_cancel_w2 (ls_resx_data_cancel_w2), - .ls_resx_dw_w0 (ls_resx_dw_w0), - .ls_resx_dw_w1 (ls_resx_dw_w1), - .ls_resx_tag_vld_w0 (ls_resx_tag_vld_w0), - .ls_resx_tag_vld_w1 (ls_resx_tag_vld_w1), - .ls_resx_tag_w0 (ls_resx_tag_w0[6:0]), - .ls_resx_tag_w1 (ls_resx_tag_w1[6:0]), - .ls_resy_data_cancel_w1 (ls_resy_data_cancel_w1), - .ls_resy_data_cancel_w2 (ls_resy_data_cancel_w2), - .ls_resy_dw_w0 (ls_resy_dw_w0), - .ls_resy_dw_w1 (ls_resy_dw_w1), - .ls_resy_tag_vld_w0 (ls_resy_tag_vld_w0), - .ls_resy_tag_vld_w1 (ls_resy_tag_vld_w1), - .ls_resy_tag_w0 (ls_resy_tag_w0[6:0]), - .ls_resy_tag_w1 (ls_resy_tag_w1[6:0]), - .mx_resp_tag_vld_w0 (mx_resp_tag_vld_w0), - .mx_resp_tag_vld_w1 (mx_resp_tag_vld_w1), - .mx_resp_tag_w0 (mx_resp_tag_w0[4:0]), - .mx_resp_tag_w1 (mx_resp_tag_w1[4:0]), - .sx_ldxcancel_sel_jw0 (sx_ldxcancel_sel_jw0), - .sx_ldxcancel_sel_jw1 (sx_ldxcancel_sel_jw1), - .sx_ldxcancel_sel_kw0 (sx_ldxcancel_sel_kw0), - .sx_ldxcancel_sel_kw1 (sx_ldxcancel_sel_kw1), - .sx_resp_tag_jw0 (sx_resp_tag_jw0[4:0]), - .sx_resp_tag_jw1 (sx_resp_tag_jw1[4:0]), - .sx_resp_tag_kw0 (sx_resp_tag_kw0[4:0]), - .sx_resp_tag_kw1 (sx_resp_tag_kw1[4:0]), - .sx_resp_tag_vld_jw0 (sx_resp_tag_vld_jw0), - .sx_resp_tag_vld_jw1 (sx_resp_tag_vld_jw1), - .sx_resp_tag_vld_kw0 (sx_resp_tag_vld_kw0), - .sx_resp_tag_vld_kw1 (sx_resp_tag_vld_kw1), - .sx_uop_vld_jw0 (sx_uop_vld_jw0), - .sx_uop_vld_kw0 (sx_uop_vld_kw0) - ); // urb - - maia_cx_rb_dp urb_dp( // outputs - .cx_fadd_srca_fp_data32_je1 (cx_fadd_srca_fp_data32_je1[63:0]), - .cx_fadd_srca_fp_data32_ke1 (cx_fadd_srca_fp_data32_ke1[63:0]), - .cx_fadd_srca_fp_data64_je1 (cx_fadd_srca_fp_data64_je1[63:0]), - .cx_fadd_srca_fp_data64_ke1 (cx_fadd_srca_fp_data64_ke1[63:0]), - .cx_fadd_srcb_fp_data32_h_je1 (cx_fadd_srcb_fp_data32_h_je1[55:0]), - .cx_fadd_srcb_fp_data32_h_ke1 (cx_fadd_srcb_fp_data32_h_ke1[55:0]), - .cx_fadd_srcb_fp_data32_l_je1 (cx_fadd_srcb_fp_data32_l_je1[55:0]), - .cx_fadd_srcb_fp_data32_l_ke1 (cx_fadd_srcb_fp_data32_l_ke1[55:0]), - .cx_fadd_srcb_fp_data64_je1 (cx_fadd_srcb_fp_data64_je1[116:0]), - .cx_fadd_srcb_fp_data64_ke1 (cx_fadd_srcb_fp_data64_ke1[116:0]), - .cx_fadd_srcc_fp_data32_je1 (cx_fadd_srcc_fp_data32_je1[63:0]), - .cx_fadd_srcc_fp_data32_ke1 (cx_fadd_srcc_fp_data32_ke1[63:0]), - .cx_fadd_srcc_fp_data64_je1 (cx_fadd_srcc_fp_data64_je1[31:0]), - .cx_fadd_srcc_fp_data64_ke1 (cx_fadd_srcc_fp_data64_ke1[31:0]), - .cx_fadd_srcd_fp_data64_je1 (cx_fadd_srcd_fp_data64_je1[31:0]), - .cx_fadd_srcd_fp_data64_ke1 (cx_fadd_srcd_fp_data64_ke1[31:0]), - .cx_fmul_srca_fp_data32_je1 (cx_fmul_srca_fp_data32_je1[63:0]), - .cx_fmul_srca_fp_data32_ke1 (cx_fmul_srca_fp_data32_ke1[63:0]), - .cx_fmul_srcb_fp_data32_je1 (cx_fmul_srcb_fp_data32_je1[63:0]), - .cx_fmul_srcb_fp_data32_ke1 (cx_fmul_srcb_fp_data32_ke1[63:0]), - .cx_resx_data_w2 (cx_resx_data_w2[63:0]), - .cx_resy_data_w2 (cx_resy_data_w2[63:0]), - .cx_resz_data_w2 (cx_resz_data_w2[63:0]), - .cx_srca_crypt_data_je1 (cx_srca_crypt_data_je1[63:0]), - .cx_srca_fp_data32_je1 (cx_srca_fp_data32_je1[63:0]), - .cx_srca_fp_data32_ke1 (cx_srca_fp_data32_ke1[63:0]), - .cx_srca_fp_data64_je1 (cx_srca_fp_data64_je1[63:0]), - .cx_srca_fp_data64_ke1 (cx_srca_fp_data64_ke1[63:0]), - .cx_srca_int_data_je1 (cx_srca_int_data_je1[63:0]), - .cx_srca_int_data_ke1 (cx_srca_int_data_ke1[63:0]), - .cx_srcb_crypt_data_je1 (cx_srcb_crypt_data_je1[63:0]), - .cx_srcb_fp_data32_je1 (cx_srcb_fp_data32_je1[63:0]), - .cx_srcb_fp_data64_je1 (cx_srcb_fp_data64_je1[63:0]), - .cx_srcb_fp_data64_ke1 (cx_srcb_fp_data64_ke1[63:0]), - .cx_srcb_int_data_je1 (cx_srcb_int_data_je1[63:0]), - .cx_srcb_int_data_ke1 (cx_srcb_int_data_ke1[63:0]), - .cx_srcc_crypt_data_je1 (cx_srcc_crypt_data_je1[63:0]), - .cx_srcc_fp_data32_je1 (cx_srcc_fp_data32_je1[63:0]), - .cx_srcc_fp_data32_ke1 (cx_srcc_fp_data32_ke1[63:0]), - .cx_srcc_int_data_je1 (cx_srcc_int_data_je1[63:0]), - .cx_srcc_int_data_ke1 (cx_srcc_int_data_ke1[63:0]), - .cx_srcd_crypt_data_je1 (cx_srcd_crypt_data_je1[63:0]), - .cx_srcd_fp_data32_je1 (cx_srcd_fp_data32_je1[31:0]), - .cx_srcd_fp_data32_ke1 (cx_srcd_fp_data32_ke1[31:0]), - .cx_srcd_int_data_je1 (cx_srcd_int_data_je1[63:0]), - .cx_srcd_int_data_ke1 (cx_srcd_int_data_ke1[63:0]), - - // inputs - .ck_gclkcx (ck_gclkcx), - .crypt2_out_e3_q (crypt2_out_e3_q[127:0]), - .crypt3_out_e6_q (crypt3_out_e6_q[127:0]), - .cx_ctl_dp_fp_valid_ji1 (cx_ctl_dp_fp_valid_ji1), - .cx_ctl_dp_fp_valid_ki1 (cx_ctl_dp_fp_valid_ki1), - .cx_ctl_dp_int_valid_ji1 (cx_ctl_dp_int_valid_ji1), - .cx_ctl_dp_int_valid_ki1 (cx_ctl_dp_int_valid_ki1), - .cx_reset3 (cx_reset3), - .cx_resx_dw_w1 (cx_resx_dw_w1), - .cx_resx_sel_dec_jw0 (cx_resx_sel_dec_jw0[49:32]), - .cx_resx_sel_dec_kw0 (cx_resx_sel_dec_kw0[13:0]), - .cx_resx_selj_w0 (cx_resx_selj_w0), - .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), - .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), - .cx_resy_dw_w1 (cx_resy_dw_w1), - .cx_resy_sel_dec_jw0 (cx_resy_sel_dec_jw0[49:32]), - .cx_resy_sel_dec_kw0 (cx_resy_sel_dec_kw0[13:0]), - .cx_resy_selj_w0 (cx_resy_selj_w0), - .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), - .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), - .cx_resz_dw_w1 (cx_resz_dw_w1), - .cx_resz_sel_dec_jw0 (cx_resz_sel_dec_jw0[49:32]), - .cx_resz_sel_dec_kw0 (cx_resz_sel_dec_kw0[13:0]), - .cx_resz_selj_w0 (cx_resz_selj_w0), - .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), - .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), - .cx_srca_data_ji1 (cx_srca_data_ji1[63:0]), - .cx_srca_data_ki1 (cx_srca_data_ki1[63:0]), - .cx_srca_fp_h_en_ji1 (cx_srca_fp_h_en_ji1), - .cx_srca_fp_h_en_ki1 (cx_srca_fp_h_en_ki1), - .cx_srca_fp_l_en_ji1 (cx_srca_fp_l_en_ji1), - .cx_srca_fp_l_en_ki1 (cx_srca_fp_l_en_ki1), - .cx_srca_int_h_en_ji1 (cx_srca_int_h_en_ji1), - .cx_srca_int_h_en_ki1 (cx_srca_int_h_en_ki1), - .cx_srca_int_l_en_ji1 (cx_srca_int_l_en_ji1), - .cx_srca_int_l_en_ki1 (cx_srca_int_l_en_ki1), - .cx_srcb_data_ji1 (cx_srcb_data_ji1[63:0]), - .cx_srcb_data_ki1 (cx_srcb_data_ki1[63:0]), - .cx_srcb_fp_h_en_ji1 (cx_srcb_fp_h_en_ji1), - .cx_srcb_fp_h_en_ki1 (cx_srcb_fp_h_en_ki1), - .cx_srcb_fp_l_en_ji1 (cx_srcb_fp_l_en_ji1), - .cx_srcb_fp_l_en_ki1 (cx_srcb_fp_l_en_ki1), - .cx_srcb_int_h_en_ji1 (cx_srcb_int_h_en_ji1), - .cx_srcb_int_h_en_ki1 (cx_srcb_int_h_en_ki1), - .cx_srcb_int_l_en_ji1 (cx_srcb_int_l_en_ji1), - .cx_srcb_int_l_en_ki1 (cx_srcb_int_l_en_ki1), - .cx_srcc_data_ji1 (cx_srcc_data_ji1[63:0]), - .cx_srcc_data_ki1 (cx_srcc_data_ki1[63:0]), - .cx_srcc_fp_h_en_ji1 (cx_srcc_fp_h_en_ji1), - .cx_srcc_fp_h_en_ki1 (cx_srcc_fp_h_en_ki1), - .cx_srcc_fp_l_en_ji1 (cx_srcc_fp_l_en_ji1), - .cx_srcc_fp_l_en_ki1 (cx_srcc_fp_l_en_ki1), - .cx_srcc_int_h_en_ji1 (cx_srcc_int_h_en_ji1), - .cx_srcc_int_h_en_ki1 (cx_srcc_int_h_en_ki1), - .cx_srcc_int_l_en_ji1 (cx_srcc_int_l_en_ji1), - .cx_srcc_int_l_en_ki1 (cx_srcc_int_l_en_ki1), - .cx_srcd_data_ji1 (cx_srcd_data_ji1[63:0]), - .cx_srcd_data_ki1 (cx_srcd_data_ki1[63:0]), - .cx_srcd_fp_h_en_ji1 (cx_srcd_fp_h_en_ji1), - .cx_srcd_fp_h_en_ki1 (cx_srcd_fp_h_en_ki1), - .cx_srcd_fp_l_en_ji1 (cx_srcd_fp_l_en_ji1), - .cx_srcd_fp_l_en_ki1 (cx_srcd_fp_l_en_ki1), - .cx_srcd_int_h_en_ji1 (cx_srcd_int_h_en_ji1), - .cx_srcd_int_h_en_ki1 (cx_srcd_int_h_en_ki1), - .cx_srcd_int_l_en_ji1 (cx_srcd_int_l_en_ji1), - .cx_srcd_int_l_en_ki1 (cx_srcd_int_l_en_ki1), - .cx_uop_vld_ji1 (cx_uop_vld_ji1), - .cx_uop_vld_ki1 (cx_uop_vld_ki1), - .fadd_srca_sel_h_je1 (fadd_srca_sel_h_je1[2:0]), - .fadd_srca_sel_h_ke1 (fadd_srca_sel_h_ke1[2:0]), - .fadd_srca_sel_l_je1 (fadd_srca_sel_l_je1), - .fadd_srca_sel_l_ke1 (fadd_srca_sel_l_ke1), - .fadd_srcb_sel_h_je1 (fadd_srcb_sel_h_je1[2:0]), - .fadd_srcb_sel_h_ke1 (fadd_srcb_sel_h_ke1[2:0]), - .fadd_srcb_sel_l_je1 (fadd_srcb_sel_l_je1[2:0]), - .fadd_srcb_sel_l_ke1 (fadd_srcb_sel_l_ke1[2:0]), - .fadd_vld_je4 (fadd_vld_je4[0]), - .fadd_vld_ke4 (fadd_vld_ke4[0]), - .faddout32_h_je4 (faddout32_h_je4[31:0]), - .faddout32_h_ke4 (faddout32_h_ke4[31:0]), - .faddout32_l_je4 (faddout32_l_je4[31:0]), - .faddout32_l_ke4 (faddout32_l_ke4[31:0]), - .faddout64_je4 (faddout64_je4[63:0]), - .faddout64_ke4 (faddout64_ke4[63:0]), - .fcvtout_je3 (fcvtout_e3[127:0]), - .fdivout32_q (fdivout32_q[31:0]), - .fdivout64_q (fdivout64_q[63:0]), - .fmla_acc_je4 (fmla_acc_je4[63:0]), - .fmla_acc_ke4 (fmla_acc_ke4[63:0]), - .fmla_fwd_je3 (fmla_fwd_je3[1:0]), - .fmla_fwd_je4 (fmla_fwd_je4[1:0]), - .fmla_fwd_ke3 (fmla_fwd_ke3[1:0]), - .fmla_fwd_ke4 (fmla_fwd_ke4[1:0]), - .fmla_je3 (fmla_je3), - .fmla_je4 (fmla_je4), - .fmla_ke3 (fmla_ke3), - .fmla_ke4 (fmla_ke4), - .fmul_srca_sel_l_je1 (fmul_srca_sel_l_je1), - .fmul_srca_sel_l_ke1 (fmul_srca_sel_l_ke1), - .fmul_srcb_sel_h_je1 (fmul_srcb_sel_h_je1), - .fmul_srcb_sel_h_ke1 (fmul_srcb_sel_h_ke1), - .fmul_srcb_sel_l_je1 (fmul_srcb_sel_l_je1), - .fmul_srcb_sel_l_ke1 (fmul_srcb_sel_l_ke1), - .fmul_vld_je4 (fmul_vld_je4[0]), - .fmul_vld_ke4 (fmul_vld_ke4[0]), - .fmulout32_h_je4 (fmulout32_h_je4[55:0]), - .fmulout32_h_ke4 (fmulout32_h_ke4[55:0]), - .fmulout32_l_je4 (fmulout32_l_je4[55:0]), - .fmulout32_l_ke4 (fmulout32_l_ke4[55:0]), - .fmulout64_je4 (fmulout64_je4[116:0]), - .fmulout64_ke4 (fmulout64_ke4[116:0]), - .fsqrtout32_q (fsqrtout32_q[31:0]), - .fsqrtout64_q (fsqrtout64_q[63:0]), - .ialuout_je3_q (ialuout_je3_q[127:0]), - .ialuout_ke3_q (ialuout_ke3_q[127:0]), - .iredout_ke3_q (iredout_ke2[63:0]), - .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), - .ishfout_e3_q (ishfout_e3_q[127:0]), - .iwbout_e4_q (iwbout_e4_q[127:0]), - .ls_resx_data_w2 (ls_resx_data_w2[63:0]), - .ls_resy_data_w2 (ls_resy_data_w2[63:0]), - .lspout_je3_q (lspout_je3_q[127:0]), - .lspout_ke3_q (lspout_ke3_q[127:0]), - .srca_dec_hi_sel_ji1 (srca_dec_hi_sel_ji1[11:1]), - .srca_dec_hi_sel_ki1 (srca_dec_hi_sel_ki1[11:1]), - .srca_dec_sel_ji1 (srca_dec_sel_ji1[11:1]), - .srca_dec_sel_ki1 (srca_dec_sel_ki1[11:1]), - .srca_hi_sel_ji1 (srca_hi_sel_ji1), - .srca_hi_sel_ki1 (srca_hi_sel_ki1), - .srcb_dec_hi_sel_ji1 (srcb_dec_hi_sel_ji1[11:1]), - .srcb_dec_hi_sel_ki1 (srcb_dec_hi_sel_ki1[11:1]), - .srcb_dec_sel_ji1 (srcb_dec_sel_ji1[11:1]), - .srcb_dec_sel_ki1 (srcb_dec_sel_ki1[11:1]), - .srcb_hi_sel_ji1 (srcb_hi_sel_ji1), - .srcb_hi_sel_ki1 (srcb_hi_sel_ki1), - .srcc_dec_hi_sel_ji1 (srcc_dec_hi_sel_ji1[11:1]), - .srcc_dec_hi_sel_ki1 (srcc_dec_hi_sel_ki1[11:1]), - .srcc_dec_sel_ji1 (srcc_dec_sel_ji1[11:1]), - .srcc_dec_sel_ki1 (srcc_dec_sel_ki1[11:1]), - .srcc_hi_sel_ji1 (srcc_hi_sel_ji1), - .srcc_hi_sel_ki1 (srcc_hi_sel_ki1), - .srcd_dec_hi_sel_ji1 (srcd_dec_hi_sel_ji1[11:1]), - .srcd_dec_hi_sel_ki1 (srcd_dec_hi_sel_ki1[11:1]), - .srcd_dec_sel_ji1 (srcd_dec_sel_ji1[11:1]), - .srcd_dec_sel_ki1 (srcd_dec_sel_ki1[11:1]), - .srcd_hi_sel_ji1 (srcd_hi_sel_ji1), - .srcd_hi_sel_ki1 (srcd_hi_sel_ki1) - ); // urb_dp - - maia_cx_issq_top uissq_top( // outputs - .cx_acc_type_je1 (cx_acc_type_je1[3:0]), - .cx_acc_type_ke1 (cx_acc_type_ke1[3:0]), - .cx_credit_j (cx_credit_j[2:0]), - .cx_credit_k (cx_credit_k[2:0]), - .cx_ctl_dp_fp_valid_ji1 (cx_ctl_dp_fp_valid_ji1), - .cx_ctl_dp_fp_valid_ki1 (cx_ctl_dp_fp_valid_ki1), - .cx_ctl_dp_int_valid_ji1 (cx_ctl_dp_int_valid_ji1), - .cx_ctl_dp_int_valid_ki1 (cx_ctl_dp_int_valid_ki1), - .cx_dstp_tag_je1 (cx_dstp_tag_je1[4:0]), - .cx_dstp_tag_ke1 (cx_dstp_tag_ke1[4:0]), - .cx_dstp_tag_vld_je1 (cx_dstp_tag_vld_je1), - .cx_dstp_tag_vld_ke1 (cx_dstp_tag_vld_ke1), - .cx_dstx_dw_je1 (cx_dstx_dw_je1), - .cx_dstx_dw_ke1 (cx_dstx_dw_ke1), - .cx_dstx_tag_je1 (cx_dstx_tag_je1[6:0]), - .cx_dstx_tag_ke1 (cx_dstx_tag_ke1[6:0]), - .cx_dstx_tag_vld_je1 (cx_dstx_tag_vld_je1), - .cx_dstx_tag_vld_ke1 (cx_dstx_tag_vld_ke1), - .cx_dsty_dw_je1 (cx_dsty_dw_je1), - .cx_dsty_dw_ke1 (cx_dsty_dw_ke1), - .cx_dsty_tag_je1 (cx_dsty_tag_je1[6:0]), - .cx_dsty_tag_ke1 (cx_dsty_tag_ke1[6:0]), - .cx_dsty_tag_vld_je1 (cx_dsty_tag_vld_je1), - .cx_dsty_tag_vld_ke1 (cx_dsty_tag_vld_ke1), - .cx_gid_je1 (cx_gid_je1[6:0]), - .cx_gid_ke1 (cx_gid_ke1[6:0]), - .cx_mla_fwd_sel_je1 (cx_mla_fwd_sel_je1[4:0]), - .cx_mla_fwd_sel_ke1 (cx_mla_fwd_sel_ke1[4:0]), - .cx_region_je1 (cx_region_je1[2:0]), - .cx_region_ke1 (cx_region_ke1[2:0]), - .cx_res128_je1 (cx_res128_je1), - .cx_res128_ke1 (cx_res128_ke1), - .cx_srca_data_ji1 (cx_srca_data_ji1[63:0]), - .cx_srca_data_ki1 (cx_srca_data_ki1[63:0]), - .cx_srca_en_je1 (cx_srca_en_je1), - .cx_srca_en_ke1 (cx_srca_en_ke1), - .cx_srca_fp_h_en_ji1 (cx_srca_fp_h_en_ji1), - .cx_srca_fp_h_en_ki1 (cx_srca_fp_h_en_ki1), - .cx_srca_fp_l_en_ji1 (cx_srca_fp_l_en_ji1), - .cx_srca_fp_l_en_ki1 (cx_srca_fp_l_en_ki1), - .cx_srca_int_h_en_ji1 (cx_srca_int_h_en_ji1), - .cx_srca_int_h_en_ki1 (cx_srca_int_h_en_ki1), - .cx_srca_int_l_en_ji1 (cx_srca_int_l_en_ji1), - .cx_srca_int_l_en_ki1 (cx_srca_int_l_en_ki1), - .cx_srcb_data_ji1 (cx_srcb_data_ji1[63:0]), - .cx_srcb_data_ki1 (cx_srcb_data_ki1[63:0]), - .cx_srcb_en_je1 (cx_srcb_en_je1), - .cx_srcb_en_ke1 (cx_srcb_en_ke1), - .cx_srcb_fp_h_en_ji1 (cx_srcb_fp_h_en_ji1), - .cx_srcb_fp_h_en_ki1 (cx_srcb_fp_h_en_ki1), - .cx_srcb_fp_l_en_ji1 (cx_srcb_fp_l_en_ji1), - .cx_srcb_fp_l_en_ki1 (cx_srcb_fp_l_en_ki1), - .cx_srcb_int_h_en_ji1 (cx_srcb_int_h_en_ji1), - .cx_srcb_int_h_en_ki1 (cx_srcb_int_h_en_ki1), - .cx_srcb_int_l_en_ji1 (cx_srcb_int_l_en_ji1), - .cx_srcb_int_l_en_ki1 (cx_srcb_int_l_en_ki1), - .cx_srcc_data_ji1 (cx_srcc_data_ji1[63:0]), - .cx_srcc_data_ki1 (cx_srcc_data_ki1[63:0]), - .cx_srcc_en_je1 (cx_srcc_en_je1), - .cx_srcc_en_ke1 (cx_srcc_en_ke1), - .cx_srcc_fp_h_en_ji1 (cx_srcc_fp_h_en_ji1), - .cx_srcc_fp_h_en_ki1 (cx_srcc_fp_h_en_ki1), - .cx_srcc_fp_l_en_ji1 (cx_srcc_fp_l_en_ji1), - .cx_srcc_fp_l_en_ki1 (cx_srcc_fp_l_en_ki1), - .cx_srcc_int_h_en_ji1 (cx_srcc_int_h_en_ji1), - .cx_srcc_int_h_en_ki1 (cx_srcc_int_h_en_ki1), - .cx_srcc_int_l_en_ji1 (cx_srcc_int_l_en_ji1), - .cx_srcc_int_l_en_ki1 (cx_srcc_int_l_en_ki1), - .cx_srcd_data_ji1 (cx_srcd_data_ji1[63:0]), - .cx_srcd_data_ki1 (cx_srcd_data_ki1[63:0]), - .cx_srcd_en_je1 (cx_srcd_en_je1), - .cx_srcd_en_ke1 (cx_srcd_en_ke1), - .cx_srcd_fp_h_en_ji1 (cx_srcd_fp_h_en_ji1), - .cx_srcd_fp_h_en_ki1 (cx_srcd_fp_h_en_ki1), - .cx_srcd_fp_l_en_ji1 (cx_srcd_fp_l_en_ji1), - .cx_srcd_fp_l_en_ki1 (cx_srcd_fp_l_en_ki1), - .cx_srcd_int_h_en_ji1 (cx_srcd_int_h_en_ji1), - .cx_srcd_int_h_en_ki1 (cx_srcd_int_h_en_ki1), - .cx_srcd_int_l_en_ji1 (cx_srcd_int_l_en_ji1), - .cx_srcd_int_l_en_ki1 (cx_srcd_int_l_en_ki1), - .cx_srcp_data_je1 (cx_srcp_data_je1[3:0]), - .cx_srcp_data_ke1 (cx_srcp_data_ke1[3:0]), - .cx_uop_ctl_ji1 (cx_uop_ctl_ji1[58:0]), - .cx_uop_ctl_ki1 (cx_uop_ctl_ki1[58:0]), - .cx_uop_vld_je1 (cx_uop_vld_je1), - .cx_uop_vld_ji1 (cx_uop_vld_ji1), - .cx_uop_vld_ke1 (cx_uop_vld_ke1), - .cx_uop_vld_ki1 (cx_uop_vld_ki1), - .fdiv_done_ack (fdiv_done_ack[1:0]), - .fdiv_uop_vld_je1 (fdiv_uop_vld_je1[1:0]), - .fsqrt_done_ack (fsqrt_done_ack[1:0]), - .fsqrt_uop_vld_ke1 (fsqrt_uop_vld_ke1[1:0]), - .issq_active (issq_active), - .issq_crypt_active (issq_crypt_active), - .issq_floatj_active (issq_floatj_active), - .issq_floatk_active (issq_floatk_active), - .issq_intj_active (issq_intj_active), - .issq_intk_active (issq_intk_active), - .srca_dec_hi_sel_ji1 (srca_dec_hi_sel_ji1[11:1]), - .srca_dec_hi_sel_ki1 (srca_dec_hi_sel_ki1[11:1]), - .srca_dec_sel_ji1 (srca_dec_sel_ji1[11:1]), - .srca_dec_sel_ki1 (srca_dec_sel_ki1[11:1]), - .srca_hi_sel_ji1 (srca_hi_sel_ji1), - .srca_hi_sel_ki1 (srca_hi_sel_ki1), - .srcb_dec_hi_sel_ji1 (srcb_dec_hi_sel_ji1[11:1]), - .srcb_dec_hi_sel_ki1 (srcb_dec_hi_sel_ki1[11:1]), - .srcb_dec_sel_ji1 (srcb_dec_sel_ji1[11:1]), - .srcb_dec_sel_ki1 (srcb_dec_sel_ki1[11:1]), - .srcb_hi_sel_ji1 (srcb_hi_sel_ji1), - .srcb_hi_sel_ki1 (srcb_hi_sel_ki1), - .srcc_dec_hi_sel_ji1 (srcc_dec_hi_sel_ji1[11:1]), - .srcc_dec_hi_sel_ki1 (srcc_dec_hi_sel_ki1[11:1]), - .srcc_dec_sel_ji1 (srcc_dec_sel_ji1[11:1]), - .srcc_dec_sel_ki1 (srcc_dec_sel_ki1[11:1]), - .srcc_hi_sel_ji1 (srcc_hi_sel_ji1), - .srcc_hi_sel_ki1 (srcc_hi_sel_ki1), - .srcd_dec_hi_sel_ji1 (srcd_dec_hi_sel_ji1[11:1]), - .srcd_dec_hi_sel_ki1 (srcd_dec_hi_sel_ki1[11:1]), - .srcd_dec_sel_ji1 (srcd_dec_sel_ji1[11:1]), - .srcd_dec_sel_ki1 (srcd_dec_sel_ki1[11:1]), - .srcd_hi_sel_ji1 (srcd_hi_sel_ji1), - .srcd_hi_sel_ki1 (srcd_hi_sel_ki1), - - // inputs - .ck_gclkcx (ck_gclkcx), - .crp3_vld_je1 (crp3_vld_je1), - .cx_acc_type_je2 (cx_acc_type_je2[3:1]), - .cx_acc_type_ke2 (cx_acc_type_ke2[3:1]), - .cx_dstx_tag_je2 (cx_dstx_tag_je2[6:0]), - .cx_dstx_tag_ke2 (cx_dstx_tag_ke2[6:0]), - .cx_ls_resx_data_cancel_w2 (cx_ls_resx_data_cancel_w2), - .cx_ls_resx_data_cancel_w3 (cx_ls_resx_data_cancel_w3), - .cx_ls_resx_dw_w1 (cx_ls_resx_dw_w1), - .cx_ls_resx_dw_w2 (cx_ls_resx_dw_w2), - .cx_ls_resx_tag_vld_w1 (cx_ls_resx_tag_vld_w1), - .cx_ls_resx_tag_vld_w2 (cx_ls_resx_tag_vld_w2), - .cx_ls_resx_tag_w1 (cx_ls_resx_tag_w1[6:0]), - .cx_ls_resx_tag_w2 (cx_ls_resx_tag_w2[6:0]), - .cx_ls_resy_data_cancel_w2 (cx_ls_resy_data_cancel_w2), - .cx_ls_resy_data_cancel_w3 (cx_ls_resy_data_cancel_w3), - .cx_ls_resy_dw_w1 (cx_ls_resy_dw_w1), - .cx_ls_resy_dw_w2 (cx_ls_resy_dw_w2), - .cx_ls_resy_tag_vld_w1 (cx_ls_resy_tag_vld_w1), - .cx_ls_resy_tag_vld_w2 (cx_ls_resy_tag_vld_w2), - .cx_ls_resy_tag_w1 (cx_ls_resy_tag_w1[6:0]), - .cx_ls_resy_tag_w2 (cx_ls_resy_tag_w2[6:0]), - .cx_mx_resp_tag_vld_w1 (cx_mx_resp_tag_vld_w1), - .cx_mx_resp_tag_vld_w2 (cx_mx_resp_tag_vld_w2), - .cx_mx_resp_tag_w1 (cx_mx_resp_tag_w1[4:0]), - .cx_mx_resp_tag_w2 (cx_mx_resp_tag_w2[4:0]), - .cx_reset3 (cx_reset3), - .cx_resp_data_w1 (cx_resp_data_w1[3:0]), - .cx_resp_data_w2 (cx_resp_data_w2[3:0]), - .cx_resp_tag_vld_w0 (cx_resp_tag_vld_w0), - .cx_resp_tag_vld_w1 (cx_resp_tag_vld_w1), - .cx_resp_tag_vld_w2 (cx_resp_tag_vld_w2), - .cx_resp_tag_w0 (cx_resp_tag_w0[4:0]), - .cx_resp_tag_w1 (cx_resp_tag_w1[4:0]), - .cx_resp_tag_w2 (cx_resp_tag_w2[4:0]), - .cx_resx_data_w2 (cx_resx_data_w2[63:0]), - .cx_resx_dw_w0 (cx_resx_dw_w0), - .cx_resx_dw_w0m1 (cx_resx_dw_w0m1), - .cx_resx_dw_w1 (cx_resx_dw_w1), - .cx_resx_dw_w2 (cx_resx_dw_w2), - .cx_resx_region_w0m1 (cx_resx_region_w0m1[2:0]), - .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), - .cx_resx_tag_vld_w0m1 (cx_resx_tag_vld_w0m1), - .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), - .cx_resx_tag_vld_w2 (cx_resx_tag_vld_w2), - .cx_resx_tag_w0 (cx_resx_tag_w0[6:0]), - .cx_resx_tag_w0m1 (cx_resx_tag_w0m1[6:0]), - .cx_resx_tag_w1 (cx_resx_tag_w1[6:0]), - .cx_resx_tag_w2 (cx_resx_tag_w2[6:0]), - .cx_resy_data_w2 (cx_resy_data_w2[63:0]), - .cx_resy_dw_w0 (cx_resy_dw_w0), - .cx_resy_dw_w0m1 (cx_resy_dw_w0m1), - .cx_resy_dw_w1 (cx_resy_dw_w1), - .cx_resy_dw_w2 (cx_resy_dw_w2), - .cx_resy_region_w0m1 (cx_resy_region_w0m1[2:0]), - .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), - .cx_resy_tag_vld_w0m1 (cx_resy_tag_vld_w0m1), - .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), - .cx_resy_tag_vld_w2 (cx_resy_tag_vld_w2), - .cx_resy_tag_w0 (cx_resy_tag_w0[6:0]), - .cx_resy_tag_w0m1 (cx_resy_tag_w0m1[6:0]), - .cx_resy_tag_w1 (cx_resy_tag_w1[6:0]), - .cx_resy_tag_w2 (cx_resy_tag_w2[6:0]), - .cx_resz_data_w2 (cx_resz_data_w2[63:0]), - .cx_resz_dw_w0 (cx_resz_dw_w0), - .cx_resz_dw_w0m1 (cx_resz_dw_w0m1), - .cx_resz_dw_w1 (cx_resz_dw_w1), - .cx_resz_dw_w2 (cx_resz_dw_w2), - .cx_resz_region_w0m1 (cx_resz_region_w0m1[2:0]), - .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), - .cx_resz_tag_vld_w0m1 (cx_resz_tag_vld_w0m1), - .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), - .cx_resz_tag_vld_w2 (cx_resz_tag_vld_w2), - .cx_resz_tag_w0 (cx_resz_tag_w0[6:0]), - .cx_resz_tag_w0m1 (cx_resz_tag_w0m1[6:0]), - .cx_resz_tag_w1 (cx_resz_tag_w1[6:0]), - .cx_resz_tag_w2 (cx_resz_tag_w2[6:0]), - .cx_sx_ldxcancel_sel_jw1 (cx_sx_ldxcancel_sel_jw1), - .cx_sx_ldxcancel_sel_kw1 (cx_sx_ldxcancel_sel_kw1), - .cx_sx_resp_tag_jw1 (cx_sx_resp_tag_jw1[4:0]), - .cx_sx_resp_tag_jw2 (cx_sx_resp_tag_jw2[4:0]), - .cx_sx_resp_tag_kw1 (cx_sx_resp_tag_kw1[4:0]), - .cx_sx_resp_tag_kw2 (cx_sx_resp_tag_kw2[4:0]), - .cx_sx_resp_tag_vld_jw1 (cx_sx_resp_tag_vld_jw1), - .cx_sx_resp_tag_vld_jw2 (cx_sx_resp_tag_vld_jw2), - .cx_sx_resp_tag_vld_kw1 (cx_sx_resp_tag_vld_kw1), - .cx_sx_resp_tag_vld_kw2 (cx_sx_resp_tag_vld_kw2), - .ds_cx_dstp_tag_jp2 (ds_cx_dstp_tag_jp2[4:0]), - .ds_cx_dstp_tag_kp2 (ds_cx_dstp_tag_kp2[4:0]), - .ds_cx_dstp_tag_vld_jp2 (ds_cx_dstp_tag_vld_jp2), - .ds_cx_dstp_tag_vld_kp2 (ds_cx_dstp_tag_vld_kp2), - .ds_cx_dstx_dw_jp2 (ds_cx_dstx_dw_jp2), - .ds_cx_dstx_dw_kp2 (ds_cx_dstx_dw_kp2), - .ds_cx_dstx_tag_jp2 (ds_cx_dstx_tag_jp2[6:0]), - .ds_cx_dstx_tag_kp2 (ds_cx_dstx_tag_kp2[6:0]), - .ds_cx_dstx_tag_vld_jp2 (ds_cx_dstx_tag_vld_jp2), - .ds_cx_dstx_tag_vld_kp2 (ds_cx_dstx_tag_vld_kp2), - .ds_cx_dsty_dw_jp2 (ds_cx_dsty_dw_jp2), - .ds_cx_dsty_dw_kp2 (ds_cx_dsty_dw_kp2), - .ds_cx_dsty_tag_jp2 (ds_cx_dsty_tag_jp2[6:0]), - .ds_cx_dsty_tag_kp2 (ds_cx_dsty_tag_kp2[6:0]), - .ds_cx_dsty_tag_vld_jp2 (ds_cx_dsty_tag_vld_jp2), - .ds_cx_dsty_tag_vld_kp2 (ds_cx_dsty_tag_vld_kp2), - .ds_cx_gid_jp2 (ds_cx_gid_jp2[6:0]), - .ds_cx_gid_kp2 (ds_cx_gid_kp2[6:0]), - .ds_cx_prt_sel_jp1 (ds_cx_prt_sel_jp1[2:0]), - .ds_cx_prt_sel_kp1 (ds_cx_prt_sel_kp1[2:0]), - .ds_cx_srca_data_jp2 (ds_cx_srca_data_jp2[63:0]), - .ds_cx_srca_data_kp2 (ds_cx_srca_data_kp2[63:0]), - .ds_cx_srca_data_vld_jp2 (ds_cx_srca_data_vld_jp2[1:0]), - .ds_cx_srca_data_vld_kp2 (ds_cx_srca_data_vld_kp2[1:0]), - .ds_cx_srcb_data_jp2 (ds_cx_srcb_data_jp2[63:0]), - .ds_cx_srcb_data_kp2 (ds_cx_srcb_data_kp2[63:0]), - .ds_cx_srcb_data_vld_jp2 (ds_cx_srcb_data_vld_jp2[1:0]), - .ds_cx_srcb_data_vld_kp2 (ds_cx_srcb_data_vld_kp2[1:0]), - .ds_cx_srcc_data_jp2 (ds_cx_srcc_data_jp2[63:0]), - .ds_cx_srcc_data_kp2 (ds_cx_srcc_data_kp2[63:0]), - .ds_cx_srcc_data_vld_jp2 (ds_cx_srcc_data_vld_jp2[1:0]), - .ds_cx_srcc_data_vld_kp2 (ds_cx_srcc_data_vld_kp2[1:0]), - .ds_cx_srcd_data_jp2 (ds_cx_srcd_data_jp2[63:0]), - .ds_cx_srcd_data_kp2 (ds_cx_srcd_data_kp2[63:0]), - .ds_cx_srcd_data_vld_jp2 (ds_cx_srcd_data_vld_jp2[1:0]), - .ds_cx_srcd_data_vld_kp2 (ds_cx_srcd_data_vld_kp2[1:0]), - .ds_cx_srcp_data_jp2 (ds_cx_srcp_data_jp2[3:0]), - .ds_cx_srcp_data_kp2 (ds_cx_srcp_data_kp2[3:0]), - .ds_cx_srcp_data_vld_jp2 (ds_cx_srcp_data_vld_jp2), - .ds_cx_srcp_data_vld_kp2 (ds_cx_srcp_data_vld_kp2), - .ds_cx_swdw_nuke_jp2 (ds_cx_swdw_nuke_jp2), - .ds_cx_swdw_nuke_kp2 (ds_cx_swdw_nuke_kp2), - .ds_cx_uop_ctl_jp2 (ds_cx_uop_ctl_jp2[58:0]), - .ds_cx_uop_ctl_kp2 (ds_cx_uop_ctl_kp2[58:0]), - .ds_cx_uop_vld_jp2 (ds_cx_uop_vld_jp2), - .ds_cx_uop_vld_kp2 (ds_cx_uop_vld_kp2), - .ds_srca_dw_0p1 (ds_srca_dw_0p1), - .ds_srca_dw_1p1 (ds_srca_dw_1p1), - .ds_srca_dw_2p1 (ds_srca_dw_2p1), - .ds_srca_prdcr_dw_0p1 (ds_srca_prdcr_dw_0p1), - .ds_srca_prdcr_dw_1p1 (ds_srca_prdcr_dw_1p1), - .ds_srca_prdcr_dw_2p1 (ds_srca_prdcr_dw_2p1), - .ds_srca_tag_0p1 (ds_srca_tag_0p1[6:0]), - .ds_srca_tag_1p1 (ds_srca_tag_1p1[6:0]), - .ds_srca_tag_2p1 (ds_srca_tag_2p1[6:0]), - .ds_srca_tag_vld_0p1 (ds_srca_tag_vld_0p1), - .ds_srca_tag_vld_1p1 (ds_srca_tag_vld_1p1), - .ds_srca_tag_vld_2p1 (ds_srca_tag_vld_2p1), - .ds_srcb_dw_0p1 (ds_srcb_dw_0p1), - .ds_srcb_dw_1p1 (ds_srcb_dw_1p1), - .ds_srcb_dw_2p1 (ds_srcb_dw_2p1), - .ds_srcb_prdcr_dw_0p1 (ds_srcb_prdcr_dw_0p1), - .ds_srcb_prdcr_dw_1p1 (ds_srcb_prdcr_dw_1p1), - .ds_srcb_prdcr_dw_2p1 (ds_srcb_prdcr_dw_2p1), - .ds_srcb_tag_0p1 (ds_srcb_tag_0p1[6:0]), - .ds_srcb_tag_1p1 (ds_srcb_tag_1p1[6:0]), - .ds_srcb_tag_2p1 (ds_srcb_tag_2p1[6:0]), - .ds_srcb_tag_vld_0p1 (ds_srcb_tag_vld_0p1), - .ds_srcb_tag_vld_1p1 (ds_srcb_tag_vld_1p1), - .ds_srcb_tag_vld_2p1 (ds_srcb_tag_vld_2p1), - .ds_srcc_dw_0p1 (ds_srcc_dw_0p1), - .ds_srcc_dw_1p1 (ds_srcc_dw_1p1), - .ds_srcc_dw_2p1 (ds_srcc_dw_2p1), - .ds_srcc_prdcr_dw_0p1 (ds_srcc_prdcr_dw_0p1), - .ds_srcc_prdcr_dw_1p1 (ds_srcc_prdcr_dw_1p1), - .ds_srcc_prdcr_dw_2p1 (ds_srcc_prdcr_dw_2p1), - .ds_srcc_tag_0p1 (ds_srcc_tag_0p1[6:0]), - .ds_srcc_tag_1p1 (ds_srcc_tag_1p1[6:0]), - .ds_srcc_tag_2p1 (ds_srcc_tag_2p1[6:0]), - .ds_srcc_tag_vld_0p1 (ds_srcc_tag_vld_0p1), - .ds_srcc_tag_vld_1p1 (ds_srcc_tag_vld_1p1), - .ds_srcc_tag_vld_2p1 (ds_srcc_tag_vld_2p1), - .ds_srcd_dw_0p1 (ds_srcd_dw_0p1), - .ds_srcd_dw_1p1 (ds_srcd_dw_1p1), - .ds_srcd_dw_2p1 (ds_srcd_dw_2p1), - .ds_srcd_prdcr_dw_0p1 (ds_srcd_prdcr_dw_0p1), - .ds_srcd_prdcr_dw_1p1 (ds_srcd_prdcr_dw_1p1), - .ds_srcd_prdcr_dw_2p1 (ds_srcd_prdcr_dw_2p1), - .ds_srcd_tag_0p1 (ds_srcd_tag_0p1[6:0]), - .ds_srcd_tag_1p1 (ds_srcd_tag_1p1[6:0]), - .ds_srcd_tag_2p1 (ds_srcd_tag_2p1[6:0]), - .ds_srcd_tag_vld_0p1 (ds_srcd_tag_vld_0p1), - .ds_srcd_tag_vld_1p1 (ds_srcd_tag_vld_1p1), - .ds_srcd_tag_vld_2p1 (ds_srcd_tag_vld_2p1), - .ds_srcp_tag_0p1 (ds_srcp_tag_0p1[4:0]), - .ds_srcp_tag_1p1 (ds_srcp_tag_1p1[4:0]), - .ds_srcp_tag_2p1 (ds_srcp_tag_2p1[4:0]), - .ds_srcp_tag_vld_0p1 (ds_srcp_tag_vld_0p1), - .ds_srcp_tag_vld_1p1 (ds_srcp_tag_vld_1p1), - .ds_srcp_tag_vld_2p1 (ds_srcp_tag_vld_2p1), - .fadd_hazard1_j (fadd_hazard1_j), - .fadd_hazard1_k (fadd_hazard1_k), - .fdiv_busy_q (fdiv_busy_q[1:0]), - .fdiv_done (fdiv_done[1:0]), - .fdiv_done_hold (fdiv_done_hold[1:0]), - .fdiv_flush (fdiv_flush[1:0]), - .fdiv_scalar (fdiv_scalar[1:0]), - .fmla_je2 (fmla_je2), - .fmla_ke2 (fmla_ke2), - .fsqrt_busy_q (fsqrt_busy_q[1:0]), - .fsqrt_done (fsqrt_done[1:0]), - .fsqrt_done_hold (fsqrt_done_hold[1:0]), - .fsqrt_flush (fsqrt_flush[1:0]), - .fsqrt_scalar (fsqrt_scalar[1:0]), - .iqj_flush_gid (iqj_flush_gid[6:0]), - .iqj_flush_u2 (iqj_flush_u2), - .iqk_flush_gid (iqk_flush_gid[6:0]), - .iqk_flush_u2 (iqk_flush_u2), - .ls_resx_data_w2 (ls_resx_data_w2[63:0]), - .ls_resy_data_w2 (ls_resy_data_w2[63:0]), - .mx_resp_data_w2 (mx_resp_data_w2[3:0]), - .sx_resp_data_jw2 (sx_resp_data_jw2[3:0]), - .sx_resp_data_kw2 (sx_resp_data_kw2[3:0]) - ); // uissq_top - - maia_cx_dpj_ctl udpj_ctl( // outputs - .aesd_e1 (aesd_e1), - .aesdimc_e1 (aesdimc_e1), - .aese_e1 (aese_e1), - .aesemc_e1 (aesemc_e1), - .aesimc_e1 (aesimc_e1), - .aesmc_e1 (aesmc_e1), - .crp3_vld_je1 (crp3_vld_je1), - .crypt2_vld_e1 (crypt2_vld_e1), - .crypt3_vld0_e1 (crypt3_vld0_e1), - .crypt3_vld1_e1 (crypt3_vld1_e1), - .cx_ccpass_je1 (cx_ccpass_je1), - .cx_dst_sel_je1 (cx_dst_sel_je1[4:0]), - .cx_imac_cmd_e1 (cx_imac_cmd_e1[12:0]), - .cx_imac_vld_e1 (cx_imac_vld_e1), - .cx_mla_fwd_sel_je2 (cx_mla_fwd_sel_je2[4:0]), - .cx_mla_fwd_sel_je3 (cx_mla_fwd_sel_je3[4:0]), - .cx_uop_res_latency_je1 (cx_uop_res_latency_je1[2:0]), - .dn_fadd_je1 (dn_fadd_je1), - .dn_je1 (dn_je1), - .dstx_bytesel_je1 (dstx_bytesel_je[39:0]), - .dsty_bytesel_je1 (dsty_bytesel_je[39:0]), - .fadd_absin_je1 (fadd_absin_je1), - .fadd_absout_je1 (fadd_absout_je1), - .fadd_ccpass_je1 (fadd_ccpass_je1), - .fadd_hazard1_j (fadd_hazard1_j), - .fadd_srca_sel_h_je1 (fadd_srca_sel_h_je1[2:0]), - .fadd_srca_sel_l_je1 (fadd_srca_sel_l_je1), - .fadd_srcb_sel_h_je1 (fadd_srcb_sel_h_je1[2:0]), - .fadd_srcb_sel_l_je1 (fadd_srcb_sel_l_je1[2:0]), - .fadd_sub_je1 (fadd_sub_je1), - .fadd_vld_je1 (fadd_vld_je1[2:0]), - .fadd_vld_je4 (fadd_vld_je4[2:0]), - .fcvt_cvt_f_to_f_je1 (fcvt_cvt_f_to_f_je1), - .fcvt_cvt_f_to_i_je1 (fcvt_cvt_f_to_i_je1), - .fcvt_cvt_i_to_f_je1 (fcvt_cvt_i_to_f_je1), - .fcvt_cvts_je1 (fcvt_cvts_je1), - .fcvt_frint_je1 (fcvt_frint_je1), - .fcvt_hp_sel_top_je1 (fcvt_hp_sel_top_je1), - .fcvt_imm_je1 (fcvt_imm_je1), - .fcvt_immv_je1 (fcvt_immv_je1[5:0]), - .fcvt_isize_je1 (fcvt_isize_je1[1:0]), - .fcvt_noixc_je1 (fcvt_noixc_je1), - .fcvt_osize_je1 (fcvt_osize_je1[1:0]), - .fcvt_recpe_je1 (fcvt_recpe_je1), - .fcvt_recpx_je1 (fcvt_recpx_je1), - .fcvt_restf_je1 (fcvt_restf_je1), - .fcvt_rsqrte_je1 (fcvt_rsqrte_je1), - .fcvt_scalar_je1 (fcvt_scalar_je1), - .fcvt_vld_je1 (fcvt_vld_je1[1:0]), - .fcvt_vld_je3 (fcvt_vld_je3[1:0]), - .fdiv_cmd_e1 (fdiv_cmd_e1[2:0]), - .fdiv_scalar_je1 (fdiv_scalar_je1), - .fmla_fused_je1 (fmla_fused_je1), - .fmla_fused_je4 (fmla_fused_je4), - .fmla_fwd_je3 (fmla_fwd_je3[1:0]), - .fmla_fwd_je4 (fmla_fwd_je4[1:0]), - .fmla_je1 (fmla_je1), - .fmla_je2 (fmla_je2), - .fmla_je3 (fmla_je3), - .fmla_je4 (fmla_je4), - .fmla_negopa_je4 (fmla_negopa_je4), - .fmul_c_on_d_je1 (fmul_c_on_d_je1), - .fmul_div_je4 (fmul_div_je4), - .fmul_ext_je1 (fmul_ext_je1), - .fmul_negmul_je1 (fmul_negmul_je1), - .fmul_srca_sel_l_je1 (fmul_srca_sel_l_je1), - .fmul_srcb_sel_h_je1 (fmul_srcb_sel_h_je1), - .fmul_srcb_sel_l_je1 (fmul_srcb_sel_l_je1), - .fmul_step_je1 (fmul_step_je1), - .fmul_vld_je1 (fmul_vld_je1[2:0]), - .fmul_vld_je2 (fmul_vld_je2[2:0]), - .fmul_vld_je3 (fmul_vld_je3[2:0]), - .fmul_vld_je4 (fmul_vld_je4[2:0]), - .fz_fadd_je1 (fz_fadd_je1), - .fz_je1 (fz_je1), - .ialu_ctl_je1 (ialu_ctl_je1[21:0]), - .ialu_en_je1 (ialu_en_je1), - .ialu_esize_je1 (ialu_esize_je1[1:0]), - .ialu_fp_dn_je1 (ialu_fp_dn_je1), - .ialu_fp_fz_je1 (ialu_fp_fz_je1), - .ialu_res128_je1 (ialu_res128_je1_q), - .ialu_selusgn_je1 (selusgn_je1_q), - .perm_en_je1 (perm_en_je1), - .perm_en_je2 (perm_en_je2), - .perm_opa_en_je1 (perm_opa_en_je1), - .perm_opb_en_je1 (perm_opb_en_je1), - .perm_opc_en_je1 (perm_opc_en_je1), - .perm_opd_en_je1 (perm_opd_en_je1), - .perm_sign_sel0_je1 (perm_sign_sel0_je1[2:0]), - .perm_sign_sel1_je1 (perm_sign_sel1_je1[2:0]), - .perm_sign_sel2_je1 (perm_sign_sel2_je1[2:0]), - .perm_sign_sel3_je1 (perm_sign_sel3_je1[2:0]), - .perm_uen_je1 (perm_uen_je1), - .perm_uen_je2 (perm_uen_je2), - .pmull_e1 (pmull_e1), - .rmode_fadd_je1 (rmode_fadd_je1[1:0]), - .rmode_fcvt_je1 (rmode_fcvt_je1[2:0]), - .rmode_je1 (rmode_je1[1:0]), - .sha1c_e1 (sha1c_e1), - .sha1h_e1 (sha1h_e1), - .sha1m_e1 (sha1m_e1), - .sha1p_e1 (sha1p_e1), - .sha1su1_e1 (sha1su1_e1), - .sha256h2_e1 (sha256h2_e1), - .sha256h_e1 (sha256h_e1), - .sha256su0_e1 (sha256su0_e1), - .sha256su1_e1 (sha256su1_e1), - .tbl_inst_je1 (tbl_inst_je), - .tbltbx_qdest_je1 (tbltbx_qdest_je), - .tbltbx_reg_bitmask_je1 (tbltbx_reg_bitmask_je[3:0]), - .tbx_inst_je1 (tbx_inst_je), - .uopnum_je1 (uopnum_je[2:0]), - .vcmp_inst_je1 (vcmp_inst_je), - - // inputs - .ck_gclkcx (ck_gclkcx), - .cx_mla_fwd_sel_je1 (cx_mla_fwd_sel_je1[4:0]), - .cx_res128_je1 (cx_res128_je1), - .cx_reset3 (cx_reset3), - .cx_srca_en_je1 (cx_srca_en_je1), - .cx_srcb_en_je1 (cx_srcb_en_je1), - .cx_srcc_en_je1 (cx_srcc_en_je1), - .cx_srcd_en_je1 (cx_srcd_en_je1), - .cx_srcp_data_je1 (cx_srcp_data_je1[3:0]), - .cx_uop_ctl_ji1 (cx_uop_ctl_ji1[58:0]), - .cx_uop_vld_je1 (cx_uop_vld_je1), - .cx_uop_vld_ji1 (cx_uop_vld_ji1), - .dn_raw_e1_q (dn_raw_e1_q), - .ds_cx_aarch32_state (ds_cx_aarch32_state), - .ds_cx_aarch64_state (ds_cx_aarch64_state), - .fz_raw_e1_q (fz_raw_e1_q), - .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), - .srca_hi_sel_ji1 (srca_hi_sel_ji1), - .srcb_hi_sel_ji1 (srcb_hi_sel_ji1) - ); // udpj_ctl - - maia_cx_dpk_ctl udpk_ctl( // outputs - .acc_size_eq64_e3_q (acc_size_eq64_e3_q), - .acc_size_ge32_e3_q (acc_size_ge32_e3_q), - .acc_size_ne08_e3_q (acc_size_ne08_e3_q), - .c00_x_sel_e1 (c00_x_sel_e1[3:0]), - .c00_y_sel_e1 (c00_y_sel_e1), - .c01_x_sel_e1 (c01_x_sel_e1[5:0]), - .c01_y_sel_e1 (c01_y_sel_e1[2:0]), - .c02_x_sel_e1 (c02_x_sel_e1[5:0]), - .c02_y_sel_e1 (c02_y_sel_e1[2:0]), - .c03_x_sel_e1 (c03_x_sel_e1[6:0]), - .c03_y_sel_e1 (c03_y_sel_e1[4:0]), - .c04_x_sel_e1 (c04_x_sel_e1[5:0]), - .c04_y_sel_e1 (c04_y_sel_e1[2:0]), - .c05_x_sel_e1 (c05_x_sel_e1[7:0]), - .c05_y_sel_e1 (c05_y_sel_e1[4:0]), - .c06_x_sel_e1 (c06_x_sel_e1[5:0]), - .c06_y_sel_e1 (c06_y_sel_e1[4:0]), - .c07_x_sel_e1 (c07_x_sel_e1[6:0]), - .c07_y_sel_e1 (c07_y_sel_e1[4:0]), - .c08_x_sel_e1 (c08_x_sel_e1[6:0]), - .c08_y_sel_e1 (c08_y_sel_e1[2:0]), - .c09_x_sel_e1 (c09_x_sel_e1[8:0]), - .c09_y_sel_e1 (c09_y_sel_e1[5:0]), - .c10_x_sel_e1 (c10_x_sel_e1[8:0]), - .c10_y_sel_e1 (c10_y_sel_e1[5:0]), - .c11_x_sel_e1 (c11_x_sel_e1[9:0]), - .c11_y_sel_e1 (c11_y_sel_e1[7:0]), - .c12_x_sel_e1 (c12_x_sel_e1[7:0]), - .c12_y_sel_e1 (c12_y_sel_e1[5:0]), - .c13_x_sel_e1 (c13_x_sel_e1[9:0]), - .c13_y_sel_e1 (c13_y_sel_e1[6:0]), - .c14_x_sel_e1 (c14_x_sel_e1[7:0]), - .c14_y_sel_e1 (c14_y_sel_e1[6:0]), - .c15_x_sel_e1 (c15_x_sel_e1[7:0]), - .c15_y_sel_e1 (c15_y_sel_e1[6:0]), - .ccpass_ke2 (ccpass_ke2), - .cx_ccpass_ke1 (cx_ccpass_ke1), - .cx_dst_sel_ke1 (cx_dst_sel_ke1[4:0]), - .cx_mla_fwd_sel_ke2 (cx_mla_fwd_sel_ke2[4:0]), - .cx_mla_fwd_sel_ke3 (cx_mla_fwd_sel_ke3[4:0]), - .cx_uop_res_latency_ke1 (cx_uop_res_latency_ke1[2:0]), - .dn_fadd_ke1 (dn_fadd_ke1), - .dn_ke1 (dn_ke1), - .dstx_bytesel_ke1 (dstx_bytesel_ke[39:0]), - .dsty_bytesel_ke1 (dsty_bytesel_ke[39:0]), - .fadd_absin_ke1 (fadd_absin_ke1), - .fadd_absout_ke1 (fadd_absout_ke1), - .fadd_ccpass_ke1 (fadd_ccpass_ke1), - .fadd_hazard1_k (fadd_hazard1_k), - .fadd_srca_sel_h_ke1 (fadd_srca_sel_h_ke1[2:0]), - .fadd_srca_sel_l_ke1 (fadd_srca_sel_l_ke1), - .fadd_srcb_sel_h_ke1 (fadd_srcb_sel_h_ke1[2:0]), - .fadd_srcb_sel_l_ke1 (fadd_srcb_sel_l_ke1[2:0]), - .fadd_sub_ke1 (fadd_sub_ke1), - .fadd_vld_ke1 (fadd_vld_ke1[2:0]), - .fadd_vld_ke4 (fadd_vld_ke4[2:0]), - .fmla_fused_ke1 (fmla_fused_ke1), - .fmla_fused_ke4 (fmla_fused_ke4), - .fmla_fwd_ke3 (fmla_fwd_ke3[1:0]), - .fmla_fwd_ke4 (fmla_fwd_ke4[1:0]), - .fmla_ke1 (fmla_ke1), - .fmla_ke2 (fmla_ke2), - .fmla_ke3 (fmla_ke3), - .fmla_ke4 (fmla_ke4), - .fmla_negopa_ke4 (fmla_negopa_ke4), - .fmul_c_on_d_ke1 (fmul_c_on_d_ke1), - .fmul_div_ke4 (fmul_div_ke4), - .fmul_ext_ke1 (fmul_ext_ke1), - .fmul_negmul_ke1 (fmul_negmul_ke1), - .fmul_srca_sel_l_ke1 (fmul_srca_sel_l_ke1), - .fmul_srcb_sel_h_ke1 (fmul_srcb_sel_h_ke1), - .fmul_srcb_sel_l_ke1 (fmul_srcb_sel_l_ke1), - .fmul_step_ke1 (fmul_step_ke1), - .fmul_vld_ke1 (fmul_vld_ke1[2:0]), - .fmul_vld_ke2 (fmul_vld_ke2[2:0]), - .fmul_vld_ke3 (fmul_vld_ke3[2:0]), - .fmul_vld_ke4 (fmul_vld_ke4[2:0]), - .fsqrt_cmd_e1 (fsqrt_cmd_e1[2:0]), - .fsqrt_scalar_ke1 (fsqrt_scalar_ke1), - .fz_fadd_ke1 (fz_fadd_ke1), - .fz_ke1 (fz_ke1), - .iacc_cin_sel_e3_q (iacc_cin_sel_e3_q[7:1]), - .iacc_en_e1 (iacc_en_e1), - .iacc_en_e2 (iacc_en_e2), - .iacc_en_e4 (iacc_en_e4), - .iacc_shfsel_e2 (iacc_shfsel_e2), - .iacce4_fwd_e2 (iacce4_fwd_e2), - .ialu_acc_en_ke1 (ialu_acc_en_ke1), - .ialu_ctl_ke1 (ialu_ctl_ke1[21:0]), - .ialu_en_ke1 (ialu_en_ke1), - .ialu_en_ke3 (ialu_en_ke3), - .ialu_esize_ke1 (ialu_esize_ke1[1:0]), - .ialu_fp_dn_ke1 (ialu_fp_dn_ke1), - .ialu_fp_fz_ke1 (ialu_fp_fz_ke1), - .ialu_res128_ke1 (ialu_res128_ke1_q), - .ialu_selusgn_ke1 (selusgn_ke1_q), - .ired_esize_ke1 (ired_esize_ke1[1:0]), - .ired_long_ke1 (ired_long_ke1), - .ired_opb_en_ke1 (ired_opb_en_ke1), - .ired_seladd_ke1 (ired_seladd_ke1), - .ired_selmax_ke1 (ired_selmax_ke1), - .ired_selmin_ke1 (ired_selmin_ke1), - .ired_selusgn_ke1 (ired_selusgn_ke1), - .ired_vrop_ke1 (ired_vrop_ke1), - .ishf3_iss_e2 (ishf3_iss_e2), - .ishf3_iss_e3 (ishf3_iss_e3), - .ishf3_uiss_e2 (ishf3_uiss_e2), - .ishf_imm_e1 (ishf_imm_e1), - .ishf_immv_e1 (ishf_immv_e1[7:0]), - .ishf_insert_e1 (ishf_insert_e1), - .ishf_iss_e1 (ishf_iss_e1), - .ishf_iss_e2 (ishf_iss_e2), - .ishf_left_e1 (ishf_left_e1), - .ishf_narrow_e1 (ishf_narrow_e1), - .ishf_qc_vld_e3 (ishf_qc_vld_e3), - .ishf_round_e1 (ishf_round_e1), - .ishf_s1_sel_e1 (ishf_s1_sel_e1[2:0]), - .ishf_s2_sel_e1 (ishf_s2_sel_e1[2:0]), - .ishf_s3_sel_e1 (ishf_s3_sel_e1[3:0]), - .ishf_s4_sel_e1 (ishf_s4_sel_e1[2:0]), - .ishf_s5_sel_e1 (ishf_s5_sel_e1[3:0]), - .ishf_s6_sel_e1 (ishf_s6_sel_e1[3:0]), - .ishf_s7_sel_e1 (ishf_s7_sel_e1[4:0]), - .ishf_saturate_e1 (ishf_saturate_e1), - .ishf_scalar_e1 (ishf_scalar_e1), - .ishf_sel16_e1 (ishf_sel16_e1), - .ishf_sel32_e1 (ishf_sel32_e1), - .ishf_sel64_e1 (ishf_sel64_e1), - .ishf_sel8_e1 (ishf_sel8_e1), - .ishf_selqsat_e3 (ishf_selqsat_e3), - .ishf_signed_e1 (ishf_signed_e1), - .ishf_stous_e1 (ishf_stous_e1), - .ishf_uiss_e2 (ishf_uiss_e2), - .ishf_widen_e1 (ishf_widen_e1), - .perm_en_ke1 (perm_en_ke1), - .perm_en_ke2 (perm_en_ke2), - .perm_opa_en_ke1 (perm_opa_en_ke1), - .perm_opb_en_ke1 (perm_opb_en_ke1), - .perm_opc_en_ke1 (perm_opc_en_ke1), - .perm_opd_en_ke1 (perm_opd_en_ke1), - .perm_sign_sel0_ke1 (perm_sign_sel0_ke1[2:0]), - .perm_sign_sel1_ke1 (perm_sign_sel1_ke1[2:0]), - .perm_sign_sel2_ke1 (perm_sign_sel2_ke1[2:0]), - .perm_sign_sel3_ke1 (perm_sign_sel3_ke1[2:0]), - .perm_uen_ke1 (perm_uen_ke1), - .perm_uen_ke2 (perm_uen_ke2), - .res128_e2 (res128_e2), - .rmode_fadd_ke1 (rmode_fadd_ke1[1:0]), - .rmode_ke1 (rmode_ke1[1:0]), - .shf_size_eq64_e3_q (shf_size_eq64_e3_q), - .shf_size_ge32_e3_q (shf_size_ge32_e3_q), - .shf_size_ne08_e3_q (shf_size_ne08_e3_q), - .tbl_inst_ke1 (tbl_inst_ke), - .tbltbx_qdest_ke1 (tbltbx_qdest_ke), - .tbltbx_reg_bitmask_ke1 (tbltbx_reg_bitmask_ke[3:0]), - .tbx_inst_ke1 (tbx_inst_ke), - .uopnum_ke1 (uopnum_ke[2:0]), - .vcmp_inst_ke1 (vcmp_inst_ke), - - // inputs - .ck_gclkcx (ck_gclkcx), - .cx_mla_fwd_sel_ke1 (cx_mla_fwd_sel_ke1[4:0]), - .cx_res128_ke1 (cx_res128_ke1), - .cx_reset3 (cx_reset3), - .cx_srca_en_ke1 (cx_srca_en_ke1), - .cx_srcb_en_ke1 (cx_srcb_en_ke1), - .cx_srcc_en_ke1 (cx_srcc_en_ke1), - .cx_srcd_en_ke1 (cx_srcd_en_ke1), - .cx_srcp_data_ke1 (cx_srcp_data_ke1[3:0]), - .cx_uop_ctl_ki1 (cx_uop_ctl_ki1[58:0]), - .cx_uop_vld_ke1 (cx_uop_vld_ke1), - .cx_uop_vld_ki1 (cx_uop_vld_ki1), - .dn_raw_e1_q (dn_raw_e1_q), - .ds_cx_aarch32_state (ds_cx_aarch32_state), - .ds_cx_aarch64_state (ds_cx_aarch64_state), - .fz_raw_e1_q (fz_raw_e1_q), - .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), - .srca_hi_sel_ki1 (srca_hi_sel_ki1), - .srcb_hi_sel_ki1 (srcb_hi_sel_ki1) - ); // udpk_ctl - - maia_cx_iacc_ff uiacck_ff( // outputs - .cx_srcc_data_e3_q (cx_srcc_data_ke3[63:0]), - .cx_srcd_data_e3_q (cx_srcd_data_ke3[63:0]), - - // inputs - .ck_gclkcx_int (ck_gclkcx_intk), - .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_ke1[1:0]), - .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_ke2[1:0]), - .cx_reset3 (cx_reset3), - .cx_srcc_data_e1 (cx_srcc_int_data_ke1[63:0]), - .cx_srcc_en_e1 (cx_srcc_en_ke1), - .cx_srcd_data_e1 (cx_srcd_int_data_ke1[63:0]), - .iacc_en_e1 (iacc_en_e1), - .iacc_en_e4 (iacc_en_e4), - .ialu_en_ke3 (ialu_en_ke3), - .ialuout_e3_q (ialuout_ke3_q[127:0]), - .ishf3_iss_e3 (ishf3_iss_e3), - .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), - .ishfout_e3_q (ishfout_e3_q[127:0]), - .res128_e1 (cx_res128_ke1), - .res128_e2 (res128_e2) - ); // uiacck_ff - - maia_cx_fmla_ff ufmlaj_ff( // outputs - .fmla_acc_e4 (fmla_acc_je4[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatj), - .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_je1[4:0]), - .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_je2[4:0]), - .cx_mla_fwd_sel_e3 (cx_mla_fwd_sel_je3[4:0]), - .cx_reset3 (cx_reset3), - .cx_srcc_en_e1 (cx_srcc_en_je1), - .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_je1[63:0]), - .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_je1[31:0]), - .faddout32_h_e4 (faddout32_h_je4[31:0]), - .faddout32_h_oe4 (faddout32_h_ke4[31:0]), - .faddout32_l_e4 (faddout32_l_je4[31:0]), - .faddout32_l_oe4 (faddout32_l_ke4[31:0]), - .faddout64_e4 (faddout64_je4[63:0]), - .faddout64_oe4 (faddout64_ke4[63:0]), - .fmla_e1 (fmla_je1), - .fmla_e2 (fmla_je2), - .fmla_e3 (fmla_je3), - .fmul_c_on_d_e1 (fmul_c_on_d_je1), - .fmul_vld_e1 (fmul_vld_je1[2:0]), - .fmul_vld_e2 (fmul_vld_je2[2:0]), - .fmul_vld_e3 (fmul_vld_je3[2:0]), - .fmulout32_h_e4 (fmulout32_h_je4[55:24]), - .fmulout32_h_oe4 (fmulout32_h_ke4[55:24]), - .fmulout32_l_e4 (fmulout32_l_je4[55:24]), - .fmulout32_l_oe4 (fmulout32_l_ke4[55:24]), - .fmulout64_e4 (fmulout64_je4[116:53]), - .fmulout64_oe4 (fmulout64_ke4[116:53]) - ); // ufmlaj_ff - - maia_cx_fmla_ff ufmlak_ff( // outputs - .fmla_acc_e4 (fmla_acc_ke4[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatk), - .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_ke1[4:0]), - .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_ke2[4:0]), - .cx_mla_fwd_sel_e3 (cx_mla_fwd_sel_ke3[4:0]), - .cx_reset3 (cx_reset3), - .cx_srcc_en_e1 (cx_srcc_en_ke1), - .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_ke1[63:0]), - .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_ke1[31:0]), - .faddout32_h_e4 (faddout32_h_ke4[31:0]), - .faddout32_h_oe4 (faddout32_h_je4[31:0]), - .faddout32_l_e4 (faddout32_l_ke4[31:0]), - .faddout32_l_oe4 (faddout32_l_je4[31:0]), - .faddout64_e4 (faddout64_ke4[63:0]), - .faddout64_oe4 (faddout64_je4[63:0]), - .fmla_e1 (fmla_ke1), - .fmla_e2 (fmla_ke2), - .fmla_e3 (fmla_ke3), - .fmul_c_on_d_e1 (fmul_c_on_d_ke1), - .fmul_vld_e1 (fmul_vld_ke1[2:0]), - .fmul_vld_e2 (fmul_vld_ke2[2:0]), - .fmul_vld_e3 (fmul_vld_ke3[2:0]), - .fmulout32_h_e4 (fmulout32_h_ke4[55:24]), - .fmulout32_h_oe4 (fmulout32_h_je4[55:24]), - .fmulout32_l_e4 (fmulout32_l_ke4[55:24]), - .fmulout32_l_oe4 (fmulout32_l_je4[55:24]), - .fmulout64_e4 (fmulout64_ke4[116:53]), - .fmulout64_oe4 (fmulout64_je4[116:53]) - ); // ufmlak_ff - - maia_cx_fmul ufmulj( // outputs - .fmul32_ex_h_e4 (fmul32_ex_h_je4[4:0]), - .fmul32_ex_l_e4 (fmul32_ex_l_je4[4:0]), - .fmul64_ex_e4 (fmul64_ex_je4[4:0]), - .fmul_active (fmulj_active), - .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_je4), - .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_je4), - .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_je4), - .fmul_f_infnanzero_e4 (fmul_f_infnanzero_je4), - .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_je4), - .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_je4), - .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_je4), - .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_je4), - .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_je4), - .fmulout32_h_e4 (fmulout32_h_je4[55:0]), - .fmulout32_l_e4 (fmulout32_l_je4[55:0]), - .fmulout64_e4 (fmulout64_je4[116:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatj), - .cx_ccpass_e1 (cx_ccpass_je1), - .cx_reset3 (cx_reset3), - .cx_srca_fp_data32_e1 (cx_fmul_srca_fp_data32_je1[63:0]), - .cx_srca_fp_data64_e1 (cx_srca_fp_data64_je1[63:0]), - .cx_srcb_fp_data32_e1 (cx_fmul_srcb_fp_data32_je1[63:0]), - .cx_srcb_fp_data64_e1 (cx_srcb_fp_data64_je1[63:0]), - .cx_srcc_fp_data32_e1 (cx_srcc_fp_data32_je1[63:0]), - .cx_srcc_fp_data64_e1 (cx_srcc_fp_data32_je1[31:0]), - .cx_srcd_fp_data64_e1 (cx_srcd_fp_data32_je1[31:0]), - .dn_e1 (dn_je1), - .fmla_fused_e1_q (fmla_fused_je1), - .fmul_ext_e1 (fmul_ext_je1), - .fmul_negmul_e1_q (fmul_negmul_je1), - .fmul_step_e1_q (fmul_step_je1), - .fmul_vld_e1 (fmul_vld_je1[2:0]), - .fz_e1 (fz_je1), - .rmode_e1_q (rmode_je1[1:0]) - ); // ufmulj - - maia_cx_fadd ufaddj( // outputs - .fadd32_ex_h_e4 (fadd32_ex_h_je4[5:0]), - .fadd32_ex_l_e4 (fadd32_ex_l_je4[5:0]), - .fadd64_ex_e4 (fadd64_ex_je4[5:0]), - .fadd_active (addj_active), - .faddout32_h_e4 (faddout32_h_je4[31:0]), - .faddout32_l_e4 (faddout32_l_je4[31:0]), - .faddout64_e4 (faddout64_je4[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatj), - .cx_reset3 (cx_reset3), - .cx_srca_fp_data32_e1 (cx_fadd_srca_fp_data32_je1[63:0]), - .cx_srca_fp_data64_e1 (cx_fadd_srca_fp_data64_je1[63:0]), - .cx_srcb_fp_data32_h_e1 (cx_fadd_srcb_fp_data32_h_je1[55:0]), - .cx_srcb_fp_data32_l_e1 (cx_fadd_srcb_fp_data32_l_je1[55:0]), - .cx_srcb_fp_data64_e1 (cx_fadd_srcb_fp_data64_je1[116:0]), - .cx_srcc_fp_data32_e1 (cx_fadd_srcc_fp_data32_je1[63:0]), - .cx_srcc_fp_data64_e1 (cx_fadd_srcc_fp_data64_je1[31:0]), - .cx_srcd_fp_data64_e1 (cx_fadd_srcd_fp_data64_je1[31:0]), - .dn_e1 (dn_fadd_je1), - .fadd_absin_e1_q (fadd_absin_je1), - .fadd_absout_e1_q (fadd_absout_je1), - .fadd_ccpass_e1 (fadd_ccpass_je1), - .fadd_sub_e1_q (fadd_sub_je1), - .fadd_vld_e1 (fadd_vld_je1[2:0]), - .fmla_e4_q (fmla_je4), - .fmla_fused_e4_q (fmla_fused_je4), - .fmla_negopa_e4_q (fmla_negopa_je4), - .fmul32_ex_h_e4 (fmul32_ex_h_je4[4:0]), - .fmul32_ex_l_e4 (fmul32_ex_l_je4[4:0]), - .fmul64_ex_e4 (fmul64_ex_je4[4:0]), - .fmul_div_e4_q (fmul_div_je4), - .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_je4), - .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_je4), - .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_je4), - .fmul_f_infnanzero_e4 (fmul_f_infnanzero_je4), - .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_je4), - .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_je4), - .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_je4), - .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_je4), - .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_je4), - .fz_e1 (fz_fadd_je1), - .rmode_e1_q (rmode_fadd_je1[1:0]) - ); // ufaddj - - maia_cx_ialu uialuj( // outputs - .ialu_active (ialuj_active), - .ialu_fpex_e3_q (ialu_fpex_je3_q[4:0]), - .ialu_nzcv_e3_q (unused1[3:0]), - .ialu_qc_e3_q (ialu_qc_je3_q), - .ialu_qc_vld_e2 (ialu_qc_vld_je2), - .ialuout_e3_q (ialuout_je3_q[127:0]), - - // inputs - .ck_gclkcx_int (ck_gclkcx_intj), - .cx_reset3 (cx_reset3), - .esize_e1 (ialu_esize_je1[1:0]), - .ialu_acc_en_e1 (1'b0), - .ialu_ccpass_e1 (1'b1), - .ialu_ctl_e1 (ialu_ctl_je1[21:0]), - .ialu_en_e1 (ialu_en_je1), - .ialu_fp_dn_e1 (ialu_fp_dn_je1), - .ialu_fp_fz_e1 (ialu_fp_fz_je1), - .ialu_nzcv_e1 (4'b0000), - .opa_e1_q (cx_srca_int_data_je1[63:0]), - .opb_e1_q (cx_srcb_int_data_je1[63:0]), - .opc_e1_q (cx_srcc_int_data_je1[63:0]), - .opd_e1_q (cx_srcd_int_data_je1[63:0]), - .res128_e1 (ialu_res128_je1_q), - .unsigned_e1 (selusgn_je1_q) - ); // uialuj - - maia_cx_perm upermj( // outputs - .lspout_e3_q (lspout_je3_q[127:0]), - - // inputs - .ck_gclkcx (ck_gclkcx), - .ds_cx_aarch64_state (ds_cx_aarch64_state), - .dstx_bytesel_e1 (dstx_bytesel_je[39:0]), - .dsty_bytesel_e1 (dsty_bytesel_je[39:0]), - .fpscr_e1_q (cx_srcp_data_je1[3:0]), - .opa_e1_q (cx_srca_int_data_je1[63:0]), - .opb_e1_q (cx_srcb_int_data_je1[63:0]), - .opc_e1_q (cx_srcc_int_data_je1[63:0]), - .opd_e1_q (cx_srcd_int_data_je1[63:0]), - .perm_en_e1 (perm_en_je1), - .perm_en_e2 (perm_en_je2), - .perm_opa_en_e1 (perm_opa_en_je1), - .perm_opb_en_e1 (perm_opb_en_je1), - .perm_opc_en_e1 (perm_opc_en_je1), - .perm_opd_en_e1 (perm_opd_en_je1), - .perm_sign_sel0_e1 (perm_sign_sel0_je1[2:0]), - .perm_sign_sel1_e1 (perm_sign_sel1_je1[2:0]), - .perm_sign_sel2_e1 (perm_sign_sel2_je1[2:0]), - .perm_sign_sel3_e1 (perm_sign_sel3_je1[2:0]), - .perm_uen_e1 (perm_uen_je1), - .perm_uen_e2 (perm_uen_je2), - .tbl_inst_e1 (tbl_inst_je), - .tbltbx_qdest_e1 (tbltbx_qdest_je), - .tbltbx_reg_bitmask_e1 (tbltbx_reg_bitmask_je[3:0]), - .tbx_inst_e1 (tbx_inst_je), - .uopnum_e1 (uopnum_je[2:0]), - .vcmp_inst_e1 (vcmp_inst_je) - ); // upermj - - maia_cx_imac uimacj( // outputs - .imac_active (imac_active), - .imac_qc_e4_q (imac_qc_e4_q), - .imac_qc_vld_e3 (imac_qc_vld_e3), - .iwbout_e4_q (iwbout_e4_q[127:0]), - - // inputs - .ck_gclkcx_int (ck_gclkcx_intj), - .cx_imac_cmd_e1_q (cx_imac_cmd_e1[12:0]), - .cx_imac_fwd_sel_e1_q (cx_mla_fwd_sel_je1[2:0]), - .cx_imac_vld_e1_q (cx_imac_vld_e1), - .cx_reset3 (cx_reset3), - .opa_e1_q (cx_srca_int_data_je1[63:0]), - .opb_e1_q (cx_srcb_int_data_je1[63:0]), - .opc_e1_q (cx_srcc_int_data_je1[63:0]), - .opd_e1_q (cx_srcd_int_data_je1[63:0]) - ); // uimacj - - maia_cx_fdiv ufdivj( // outputs - .fdiv_active (fdiv_active), - .fdiv_done (fdiv_done[1:0]), - .fdivexc32_q (fdivexc32_q[5:0]), - .fdivexc64_q (fdivexc64_q[5:0]), - .fdivout32_q (fdivout32_q[31:0]), - .fdivout64_q (fdivout64_q[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatj), - .cx_reset3 (cx_reset3), - .dn_e1_q (dn_je1), - .fdiv_ccpass_e1 (cx_ccpass_je1), - .fdiv_cmd_e1_q (fdiv_cmd_e1[2:0]), - .fdiv_flush (fdiv_flush[1:0]), - .fdiv_vld_e1 (fdiv_uop_vld_je1[1:0]), - .fz_e1_q (fz_je1), - .opa_e1_q (cx_srca_fp_data32_je1[63:0]), - .opb_e1_q (cx_srcb_fp_data32_je1[63:0]), - .opc_e1_q (cx_srcc_fp_data32_je1[31:0]), - .opd_e1_q (cx_srcd_fp_data32_je1[31:0]), - .rmode_e1_q (rmode_je1[1:0]) - ); // ufdivj - - maia_cx_fcvt ufcvtj( // outputs - .fcvt_active (cvtj_active), - .fcvt_ex_h_e3 (fcvt_ex_h_e3[5:0]), - .fcvt_ex_l_e3 (fcvt_ex_l_e3[5:0]), - .fcvtout_e3 (fcvtout_e3[127:0]), - - // inputs - .ahp_mode_e1_q (ahp_mode_e1_q), - .ccpass_e1 (cx_ccpass_je1), - .ck_gclkcx_float (ck_gclkcx_floatj), - .cx_reset3 (cx_reset3), - .cx_srca_fp_data_e1 (cx_srca_fp_data32_je1[63:0]), - .cx_srcb_fp_data_e1 (cx_srcb_fp_data32_je1[63:0]), - .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_je1[31:0]), - .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_je1[31:0]), - .dn_e1_q (dn_je1), - .fcvt_cvt_f_to_f_e1 (fcvt_cvt_f_to_f_je1), - .fcvt_cvt_f_to_i_e1 (fcvt_cvt_f_to_i_je1), - .fcvt_cvt_i_to_f_e1 (fcvt_cvt_i_to_f_je1), - .fcvt_cvts_e1 (fcvt_cvts_je1), - .fcvt_frint_e1 (fcvt_frint_je1), - .fcvt_hp_sel_top_e1 (fcvt_hp_sel_top_je1), - .fcvt_imm_e1 (fcvt_imm_je1), - .fcvt_immv_e1 (fcvt_immv_je1[5:0]), - .fcvt_isize_e1 (fcvt_isize_je1[1:0]), - .fcvt_noixc_e1 (fcvt_noixc_je1), - .fcvt_osize_e1 (fcvt_osize_je1[1:0]), - .fcvt_recpe_e1 (fcvt_recpe_je1), - .fcvt_recpx_e1 (fcvt_recpx_je1), - .fcvt_restf_e1 (fcvt_restf_je1), - .fcvt_rsqrte_e1 (fcvt_rsqrte_je1), - .fcvt_scalar_e1 (fcvt_scalar_je1), - .fcvt_vld_e1 (fcvt_vld_je1[1:0]), - .fz_e1_q (fz_je1), - .rmode_e1_q (rmode_fcvt_je1[2:0]) - ); // ufcvtj - - maia_cx_fmul ufmulk( // outputs - .fmul32_ex_h_e4 (fmul32_ex_h_ke4[4:0]), - .fmul32_ex_l_e4 (fmul32_ex_l_ke4[4:0]), - .fmul64_ex_e4 (fmul64_ex_ke4[4:0]), - .fmul_active (fmulk_active), - .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_ke4), - .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_ke4), - .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_ke4), - .fmul_f_infnanzero_e4 (fmul_f_infnanzero_ke4), - .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_ke4), - .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_ke4), - .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_ke4), - .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_ke4), - .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_ke4), - .fmulout32_h_e4 (fmulout32_h_ke4[55:0]), - .fmulout32_l_e4 (fmulout32_l_ke4[55:0]), - .fmulout64_e4 (fmulout64_ke4[116:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatk), - .cx_ccpass_e1 (cx_ccpass_ke1), - .cx_reset3 (cx_reset3), - .cx_srca_fp_data32_e1 (cx_fmul_srca_fp_data32_ke1[63:0]), - .cx_srca_fp_data64_e1 (cx_srca_fp_data64_ke1[63:0]), - .cx_srcb_fp_data32_e1 (cx_fmul_srcb_fp_data32_ke1[63:0]), - .cx_srcb_fp_data64_e1 (cx_srcb_fp_data64_ke1[63:0]), - .cx_srcc_fp_data32_e1 (cx_srcc_fp_data32_ke1[63:0]), - .cx_srcc_fp_data64_e1 (cx_srcc_fp_data32_ke1[31:0]), - .cx_srcd_fp_data64_e1 (cx_srcd_fp_data32_ke1[31:0]), - .dn_e1 (dn_ke1), - .fmla_fused_e1_q (fmla_fused_ke1), - .fmul_ext_e1 (fmul_ext_ke1), - .fmul_negmul_e1_q (fmul_negmul_ke1), - .fmul_step_e1_q (fmul_step_ke1), - .fmul_vld_e1 (fmul_vld_ke1[2:0]), - .fz_e1 (fz_ke1), - .rmode_e1_q (rmode_ke1[1:0]) - ); // ufmulk - - maia_cx_fadd ufaddk( // outputs - .fadd32_ex_h_e4 (fadd32_ex_h_ke4[5:0]), - .fadd32_ex_l_e4 (fadd32_ex_l_ke4[5:0]), - .fadd64_ex_e4 (fadd64_ex_ke4[5:0]), - .fadd_active (addk_active), - .faddout32_h_e4 (faddout32_h_ke4[31:0]), - .faddout32_l_e4 (faddout32_l_ke4[31:0]), - .faddout64_e4 (faddout64_ke4[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatk), - .cx_reset3 (cx_reset3), - .cx_srca_fp_data32_e1 (cx_fadd_srca_fp_data32_ke1[63:0]), - .cx_srca_fp_data64_e1 (cx_fadd_srca_fp_data64_ke1[63:0]), - .cx_srcb_fp_data32_h_e1 (cx_fadd_srcb_fp_data32_h_ke1[55:0]), - .cx_srcb_fp_data32_l_e1 (cx_fadd_srcb_fp_data32_l_ke1[55:0]), - .cx_srcb_fp_data64_e1 (cx_fadd_srcb_fp_data64_ke1[116:0]), - .cx_srcc_fp_data32_e1 (cx_fadd_srcc_fp_data32_ke1[63:0]), - .cx_srcc_fp_data64_e1 (cx_fadd_srcc_fp_data64_ke1[31:0]), - .cx_srcd_fp_data64_e1 (cx_fadd_srcd_fp_data64_ke1[31:0]), - .dn_e1 (dn_fadd_ke1), - .fadd_absin_e1_q (fadd_absin_ke1), - .fadd_absout_e1_q (fadd_absout_ke1), - .fadd_ccpass_e1 (fadd_ccpass_ke1), - .fadd_sub_e1_q (fadd_sub_ke1), - .fadd_vld_e1 (fadd_vld_ke1[2:0]), - .fmla_e4_q (fmla_ke4), - .fmla_fused_e4_q (fmla_fused_ke4), - .fmla_negopa_e4_q (fmla_negopa_ke4), - .fmul32_ex_h_e4 (fmul32_ex_h_ke4[4:0]), - .fmul32_ex_l_e4 (fmul32_ex_l_ke4[4:0]), - .fmul64_ex_e4 (fmul64_ex_ke4[4:0]), - .fmul_div_e4_q (fmul_div_ke4), - .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_ke4), - .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_ke4), - .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_ke4), - .fmul_f_infnanzero_e4 (fmul_f_infnanzero_ke4), - .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_ke4), - .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_ke4), - .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_ke4), - .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_ke4), - .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_ke4), - .fz_e1 (fz_fadd_ke1), - .rmode_e1_q (rmode_fadd_ke1[1:0]) - ); // ufaddk - - maia_cx_ialu uialuk( // outputs - .ialu_active (ialuk_active), - .ialu_fpex_e3_q (ialu_fpex_ke3_q[4:0]), - .ialu_nzcv_e3_q (ialu_nzcv_ke3_q[3:0]), - .ialu_qc_e3_q (ialu_qc_ke3_q), - .ialu_qc_vld_e2 (ialu_qc_vld_ke2), - .ialuout_e3_q (ialuout_ke3_q[127:0]), - - // inputs - .ck_gclkcx_int (ck_gclkcx_intk), - .cx_reset3 (cx_reset3), - .esize_e1 (ialu_esize_ke1[1:0]), - .ialu_acc_en_e1 (ialu_acc_en_ke1), - .ialu_ccpass_e1 (cx_ccpass_ke1), - .ialu_ctl_e1 (ialu_ctl_ke1[21:0]), - .ialu_en_e1 (ialu_en_ke1), - .ialu_fp_dn_e1 (ialu_fp_dn_ke1), - .ialu_fp_fz_e1 (ialu_fp_fz_ke1), - .ialu_nzcv_e1 (cx_srcp_data_ke1[3:0]), - .opa_e1_q (cx_srca_int_data_ke1[63:0]), - .opb_e1_q (cx_srcb_int_data_ke1[63:0]), - .opc_e1_q (cx_srcc_int_data_ke1[63:0]), - .opd_e1_q (cx_srcd_int_data_ke1[63:0]), - .res128_e1 (ialu_res128_ke1_q), - .unsigned_e1 (selusgn_ke1_q) - ); // uialuk - - maia_cx_ired uiredk( // outputs - .ired_active (iredk_active), - .iredout_e3_q (iredout_ke2[63:0]), - - // inputs - .ck_gclkcx_int (ck_gclkcx_intk), - .cx_reset3 (cx_reset3), - .esize_e1 (ired_esize_ke1[1:0]), - .long_e1 (ired_long_ke1), - .opa_e1_q (cx_srca_int_data_ke1[63:0]), - .opb_e1_q (cx_srcb_int_data_ke1[63:0]), - .opb_en_e1 (ired_opb_en_ke1), - .seladd_e1 (ired_seladd_ke1), - .selmax_e1 (ired_selmax_ke1), - .selmin_e1 (ired_selmin_ke1), - .unsigned_e1 (ired_selusgn_ke1), - .vrop_e1 (ired_vrop_ke1) - ); // uiredk - - maia_cx_perm upermk( // outputs - .lspout_e3_q (lspout_ke3_q[127:0]), - - // inputs - .ck_gclkcx (ck_gclkcx), - .ds_cx_aarch64_state (ds_cx_aarch64_state), - .dstx_bytesel_e1 (dstx_bytesel_ke[39:0]), - .dsty_bytesel_e1 (dsty_bytesel_ke[39:0]), - .fpscr_e1_q (cx_srcp_data_ke1[3:0]), - .opa_e1_q (cx_srca_int_data_ke1[63:0]), - .opb_e1_q (cx_srcb_int_data_ke1[63:0]), - .opc_e1_q (cx_srcc_int_data_ke1[63:0]), - .opd_e1_q (cx_srcd_int_data_ke1[63:0]), - .perm_en_e1 (perm_en_ke1), - .perm_en_e2 (perm_en_ke2), - .perm_opa_en_e1 (perm_opa_en_ke1), - .perm_opb_en_e1 (perm_opb_en_ke1), - .perm_opc_en_e1 (perm_opc_en_ke1), - .perm_opd_en_e1 (perm_opd_en_ke1), - .perm_sign_sel0_e1 (perm_sign_sel0_ke1[2:0]), - .perm_sign_sel1_e1 (perm_sign_sel1_ke1[2:0]), - .perm_sign_sel2_e1 (perm_sign_sel2_ke1[2:0]), - .perm_sign_sel3_e1 (perm_sign_sel3_ke1[2:0]), - .perm_uen_e1 (perm_uen_ke1), - .perm_uen_e2 (perm_uen_ke2), - .tbl_inst_e1 (tbl_inst_ke), - .tbltbx_qdest_e1 (tbltbx_qdest_ke), - .tbltbx_reg_bitmask_e1 (tbltbx_reg_bitmask_ke[3:0]), - .tbx_inst_e1 (tbx_inst_ke), - .uopnum_e1 (uopnum_ke[2:0]), - .vcmp_inst_e1 (vcmp_inst_ke) - ); // upermk - - maia_cx_ishf uishfk( // outputs - .ishf_active (ishf_active), - .ishf_qc_e4_q (ishf_qc_e4_q), - .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), - .ishfout_e3_q (ishfout_e3_q[127:0]), - - // inputs - .acc_size_eq64_e3_q (acc_size_eq64_e3_q), - .acc_size_ge32_e3_q (acc_size_ge32_e3_q), - .acc_size_ne08_e3_q (acc_size_ne08_e3_q), - .c00_x_sel_e1_q (c00_x_sel_e1[3:0]), - .c00_y_sel_e1_q (c00_y_sel_e1), - .c01_x_sel_e1_q (c01_x_sel_e1[5:0]), - .c01_y_sel_e1_q (c01_y_sel_e1[2:0]), - .c02_x_sel_e1_q (c02_x_sel_e1[5:0]), - .c02_y_sel_e1_q (c02_y_sel_e1[2:0]), - .c03_x_sel_e1_q (c03_x_sel_e1[6:0]), - .c03_y_sel_e1_q (c03_y_sel_e1[4:0]), - .c04_x_sel_e1_q (c04_x_sel_e1[5:0]), - .c04_y_sel_e1_q (c04_y_sel_e1[2:0]), - .c05_x_sel_e1_q (c05_x_sel_e1[7:0]), - .c05_y_sel_e1_q (c05_y_sel_e1[4:0]), - .c06_x_sel_e1_q (c06_x_sel_e1[5:0]), - .c06_y_sel_e1_q (c06_y_sel_e1[4:0]), - .c07_x_sel_e1_q (c07_x_sel_e1[6:0]), - .c07_y_sel_e1_q (c07_y_sel_e1[4:0]), - .c08_x_sel_e1_q (c08_x_sel_e1[6:0]), - .c08_y_sel_e1_q (c08_y_sel_e1[2:0]), - .c09_x_sel_e1_q (c09_x_sel_e1[8:0]), - .c09_y_sel_e1_q (c09_y_sel_e1[5:0]), - .c10_x_sel_e1_q (c10_x_sel_e1[8:0]), - .c10_y_sel_e1_q (c10_y_sel_e1[5:0]), - .c11_x_sel_e1_q (c11_x_sel_e1[9:0]), - .c11_y_sel_e1_q (c11_y_sel_e1[7:0]), - .c12_x_sel_e1_q (c12_x_sel_e1[7:0]), - .c12_y_sel_e1_q (c12_y_sel_e1[5:0]), - .c13_x_sel_e1_q (c13_x_sel_e1[9:0]), - .c13_y_sel_e1_q (c13_y_sel_e1[6:0]), - .c14_x_sel_e1_q (c14_x_sel_e1[7:0]), - .c14_y_sel_e1_q (c14_y_sel_e1[6:0]), - .c15_x_sel_e1_q (c15_x_sel_e1[7:0]), - .c15_y_sel_e1_q (c15_y_sel_e1[6:0]), - .ck_gclkcx_int (ck_gclkcx_intk), - .cx_reset3 (cx_reset3), - .iacc_cin_sel_e3_q (iacc_cin_sel_e3_q[7:1]), - .iacc_en_e2 (iacc_en_e2), - .iacc_shfsel_e2 (iacc_shfsel_e2), - .iacce4_fwd_e2 (iacce4_fwd_e2), - .ialuout_e3_q (ialuout_ke3_q[127:0]), - .ishf3_iss_e2_q (ishf3_iss_e2), - .ishf3_iss_e3_q (ishf3_iss_e3), - .ishf3_uiss_e2_q (ishf3_uiss_e2), - .ishf_imm_e1_q (ishf_imm_e1), - .ishf_immv_e1_q (ishf_immv_e1[7:0]), - .ishf_insert_e1_q (ishf_insert_e1), - .ishf_iss_e1_q (ishf_iss_e1), - .ishf_iss_e2_q (ishf_iss_e2), - .ishf_left_e1_q (ishf_left_e1), - .ishf_narrow_e1_q (ishf_narrow_e1), - .ishf_round_e1_q (ishf_round_e1), - .ishf_s1_sel_e1_q (ishf_s1_sel_e1[2:0]), - .ishf_s2_sel_e1_q (ishf_s2_sel_e1[2:0]), - .ishf_s3_sel_e1_q (ishf_s3_sel_e1[3:0]), - .ishf_s4_sel_e1_q (ishf_s4_sel_e1[2:0]), - .ishf_s5_sel_e1_q (ishf_s5_sel_e1[3:0]), - .ishf_s6_sel_e1_q (ishf_s6_sel_e1[3:0]), - .ishf_s7_sel_e1_q (ishf_s7_sel_e1[4:0]), - .ishf_saturate_e1_q (ishf_saturate_e1), - .ishf_scalar_e1 (ishf_scalar_e1), - .ishf_sel16_e1_q (ishf_sel16_e1), - .ishf_sel32_e1_q (ishf_sel32_e1), - .ishf_sel64_e1_q (ishf_sel64_e1), - .ishf_sel8_e1_q (ishf_sel8_e1), - .ishf_selqsat_e3_q (ishf_selqsat_e3), - .ishf_signed_e1_q (ishf_signed_e1), - .ishf_stous_e1_q (ishf_stous_e1), - .ishf_uiss_e2_q (ishf_uiss_e2), - .ishf_widen_e1_q (ishf_widen_e1), - .opa_e1_q (cx_srca_int_data_ke1[63:0]), - .opb_e1_q (cx_srcb_int_data_ke1[63:0]), - .opc_e3_q (cx_srcc_data_ke3[63:0]), - .opd_e3_q (cx_srcd_data_ke3[63:0]), - .shf_size_eq64_e3_q (shf_size_eq64_e3_q), - .shf_size_ge32_e3_q (shf_size_ge32_e3_q), - .shf_size_ne08_e3_q (shf_size_ne08_e3_q) - ); // uishfk - - maia_cx_crypt2 ucrypt2( // outputs - .crypt2_active (crypt2_active), - .crypt2_out_e3_q (crypt2_out_e3_q[127:0]), - - // inputs - .aesd_e1_q (aesd_e1), - .aesdimc_e1_q (aesdimc_e1), - .aese_e1_q (aese_e1), - .aesemc_e1_q (aesemc_e1), - .aesimc_e1_q (aesimc_e1), - .aesmc_e1_q (aesmc_e1), - .ck_gclkcx_crypt (ck_gclkcx_crypt), - .cx_reset3 (cx_reset3), - .ival_e1_q (crypt2_vld_e1), - .pmull_e1_q (pmull_e1), - .qd ({cx_srcd_crypt_data_je1[63:0], cx_srcc_crypt_data_je1[63:0]}), - .qn ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), - .sha1h_e1_q (sha1h_e1), - .sha1su1_e1_q (sha1su1_e1), - .sha256su0_e1_q (sha256su0_e1) - ); // ucrypt2 - - maia_cx_crypt3 ucrypt3( // outputs - .crypt3_active (crypt3_active), - .crypt3_out_e6_q (crypt3_out_e6_q[127:0]), - - // inputs - .ck_gclkcx_crypt (ck_gclkcx_crypt), - .cx_reset3 (cx_reset3), - .ival_e1_q (crypt3_vld0_e1), - .ival_e2_q (crypt3_vld1_e1), - .qd_e2_q ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), - .qm_e1_q ({cx_srcd_crypt_data_je1[63:0], cx_srcc_crypt_data_je1[63:0]}), - .qn_e1_q ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), - .sha1c_e1_q (sha1c_e1), - .sha1m_e1_q (sha1m_e1), - .sha1p_e1_q (sha1p_e1), - .sha256h2_e1_q (sha256h2_e1), - .sha256h_e1_q (sha256h_e1), - .sha256su1_e1_q (sha256su1_e1) - ); // ucrypt3 - - maia_cx_fsqrt ufsqrtk( // outputs - .fsqrt_active (fsqrt_active), - .fsqrt_done (fsqrt_done[1:0]), - .fsqrtexc32_q (fsqrtexc32_q[5:0]), - .fsqrtexc64_q (fsqrtexc64_q[5:0]), - .fsqrtout32_q (fsqrtout32_q[31:0]), - .fsqrtout64_q (fsqrtout64_q[63:0]), - - // inputs - .ck_gclkcx_float (ck_gclkcx_floatk), - .cx_reset3 (cx_reset3), - .dn_e1_q (dn_ke1), - .fsqrt_ccpass_e1 (cx_ccpass_ke1), - .fsqrt_cmd_e1_q (fsqrt_cmd_e1[2:0]), - .fsqrt_flush (fsqrt_flush[1:0]), - .fsqrt_vld_e1 (fsqrt_uop_vld_ke1[1:0]), - .fz_e1_q (fz_ke1), - .opa_e1_q (cx_srca_fp_data32_ke1[63:0]), - .opc_e1_q (cx_srcc_fp_data32_ke1[31:0]), - .opd_e1_q (cx_srcd_fp_data32_ke1[31:0]), - .rmode_e1_q (rmode_ke1[1:0]) - ); // ufsqrtk -endmodule // maia_complex - - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v deleted file mode 100644 index 6c292397b2..0000000000 --- a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v +++ /dev/null @@ -1,351 +0,0 @@ - -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_cx_crypt2.v $ -// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ -// Revision : $Revision: 70482 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// This block does the following operations: -// - AES encrypt and decrypt operations: aesd, aese, aesmc, aesimc -// - SHA single-cycle operations: sha1h, sha1su1, sha256su0 - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -module maia_cx_crypt2 ( - -//# -//# Interface Signals -//# ================= -//# - -// Global inputs - ck_gclkcx_crypt, - cx_reset3, - -// Control inputs - ival_e1_q, - aesd_e1_q, - aese_e1_q, - aesmc_e1_q, - aesimc_e1_q, - aesdimc_e1_q, - aesemc_e1_q, - pmull_e1_q, - sha1h_e1_q, - sha1su1_e1_q, - sha256su0_e1_q, - - -// Data inputs - qd, - qn, - - -// Outputs - crypt2_out_e3_q, - crypt2_active -); - - -//# -//# Interface Signals -//# ================= -//# - -// Global inputs - input ck_gclkcx_crypt; - input cx_reset3; - -// Control inputs - input ival_e1_q; - input aesd_e1_q; // aes encode - input aese_e1_q; // aes decode - input aesmc_e1_q; // ae smix columns - input aesimc_e1_q; // aes inverse mix columns - input aesdimc_e1_q; // aes decode superop - input aesemc_e1_q; // aes encode superop - input pmull_e1_q; // polynomial multiplication - input sha1h_e1_q; // sha1 fixed rotate - input sha1su1_e1_q; // sha1 schedule update 1 - input sha256su0_e1_q; // sha256 schedule update 0 - - -// Data inputs - input [127:0] qd; - input [127:0] qn; - - -// Outputs - output [127:0] crypt2_out_e3_q; - output crypt2_active; - -//# -//# Internal Signals - Automatic Declarations -//# ========================================= -//# - wire [ 15: 0] aes_shf_e1; - reg [ 15: 0] aes_shf_e2_q; - wire [127: 0] aesd_e1; - reg aesd_e2_q; - wire aesd_or_e_e1; - wire [127: 0] aesd_out; - wire [ 15: 0] aesd_shf_e1; - reg aesdimc_e2_q; - wire [127: 0] aesdimc_out; - wire [127: 0] aese_e1; - reg aese_e2_q; - wire [127: 0] aese_out; - wire [ 15: 0] aese_shf_e1; - reg aesemc_e2_q; - wire [127: 0] aesemc_out; - reg aesimc_e2_q; - wire [127: 0] aesimc_in; - wire [127: 0] aesimc_out; - reg aesmc_e2_q; - wire [127: 0] aesmc_in; - wire [127: 0] aesmc_out; - wire [127: 0] crypt2_d_e1; - reg [127: 0] crypt2_d_e2_q; - wire [127: 0] crypt2_out_e2; - reg [127: 0] crypt2_out_e3_q; - reg ival_e2_q; - reg pmull_e2_q; - wire [127: 0] pmull_out; - wire [127: 0] qx_e1; - wire [ 31: 0] sha1h_in_e1; - wire [ 31: 0] sha1h_out_e1; - wire [127: 0] sha1su1_out_e1; - wire [127: 0] sha1su1_qdin_e1; - wire [127: 0] sha1su1_qnin_e1; - wire [127: 0] sha256su0_out_e1; - wire sha_inst_e1; - reg sha_inst_e2_q; - -//# -//# Main Code -//# ========= -//# -// - -// aes functions are all in the same block because of limited result bus bandwidth. -// Mais CX has 3x64-bit result buses, and each of these instructions produces -// a 128-bit result. Two instructions could be issued in a cycle, but there is -// no value in doing this because they could not both write results. -// -// The single-cycle 2-input SHA instructions are in the same block because they have the same inputs -// and latency as the aes instructions. -// -// Originally, all functions in this block had single-cycle latency, but CX is unable to make use -// of single-cycle latency. To reduce area, functionality is spread across E1 and E2 -// In particular, the AES SBOX and ISBOX functions are split into LUT(mult inverse) -> affine transform -// & affine inverse transform -> LUT(mult inverse), so that they can share the same LUT. - -// E1 -// 38% of this cycle is used up to drive qd and qn from the issq block. Therefore, the relatively -// shallow SHA operations are performed in this cycle, along with some preliminary processing for AESE and AESD - -assign qx_e1[127:0] = {128{aesd_or_e_e1}} & (qd[127:0] ^ qn[127:0]); - - maia_cx_aese1 uaese1( - .q (qx_e1[127:0]), - .aese_out (aese_e1[127:0]), - .aese_shf (aese_shf_e1[15:0]) -); - - maia_cx_aesd1 uaesd1( - .q (qx_e1[127:0]), - .aesd_out (aesd_e1[127:0]), - .aesd_shf (aesd_shf_e1[15:0]) -); - -assign aesd_or_e_e1 = aesd_e1_q | aese_e1_q; - -// Perform sha functions in E1 to save pipeline flops -// and reduce complexity of multiplexer in E2 - -assign sha1h_in_e1[31:0] = {32{sha1h_e1_q}} & qn[31:0]; - - maia_cx_sha1h usha1h( - .qn (sha1h_in_e1[31:0]), - .d (sha1h_out_e1[31:0]) -); - -assign sha1su1_qdin_e1[127:0] = {128{sha1su1_e1_q}} & qd[127:0]; -assign sha1su1_qnin_e1[127:0] = {128{sha1su1_e1_q}} & qn[127:0]; - - maia_cx_sha1su1 usha1su1( - .qd (sha1su1_qdin_e1[127:0]), - .qn (sha1su1_qnin_e1[127:0]), - .d (sha1su1_out_e1[127:0]) -); - - - maia_cx_sha256su0 usha256su0( - .qd (qd[127:0]), - .qn (qn[127:0]), - .d (sha256su0_out_e1[127:0]) -); - -assign sha_inst_e1 = sha1h_e1_q | sha1su1_e1_q | sha256su0_e1_q; - -assign crypt2_d_e1[127:0] = ({128{sha1h_e1_q}} & {{96{1'b0}}, sha1h_out_e1[31:0]}) - | ({128{sha1su1_e1_q}} & sha1su1_out_e1[127:0]) - | ({128{sha256su0_e1_q}} & sha256su0_out_e1[127:0]) - | ({128{aese_e1_q}} & aese_e1[127:0]) - | ({128{aesd_e1_q}} & aesd_e1[127:0]) - | ({128{~(aesd_or_e_e1 | sha_inst_e1)}} & qn[127:0]); - -assign aes_shf_e1[15:0] = {16{aese_e1_q}} & aese_shf_e1[15:0] | - {16{aesd_e1_q}} & aesd_shf_e1[15:0]; - -// reset flop(s) since feeds into active signal used for RCG - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt or posedge cx_reset3) - begin: uival_e2_q - if (cx_reset3 == 1'b1) - ival_e2_q <= `MAIA_DFF_DELAY {1{1'b0}}; -`ifdef MAIA_XPROP_FLOP - else if (cx_reset3==1'b0) - ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q; - else - ival_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; -`else - else - ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q; -`endif - end - // verilint flop_checks on - // end of Macro DFF - - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: ucrypt2_e2 - if (ival_e1_q==1'b1) begin - crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY crypt2_d_e1[127:0]; - aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY aes_shf_e1[15:0]; - aesd_e2_q <= `MAIA_DFF_DELAY aesd_e1_q; - aese_e2_q <= `MAIA_DFF_DELAY aese_e1_q; - aesmc_e2_q <= `MAIA_DFF_DELAY aesmc_e1_q; - aesimc_e2_q <= `MAIA_DFF_DELAY aesimc_e1_q; - aesemc_e2_q <= `MAIA_DFF_DELAY aesemc_e1_q; - aesdimc_e2_q <= `MAIA_DFF_DELAY aesdimc_e1_q; - pmull_e2_q <= `MAIA_DFF_DELAY pmull_e1_q; - sha_inst_e2_q <= `MAIA_DFF_DELAY sha_inst_e1; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e1_q==1'b0)); - else begin - crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY {16{1'bx}}; - aesd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - aese_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - aesmc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - aesimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - aesemc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - aesdimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - pmull_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha_inst_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// Enable data inputs for selected operation (glitch suppression in unused datapaths) - assign aesmc_in[127:0] = {128{aesmc_e2_q }} & crypt2_d_e2_q[127:0]; - assign aesimc_in[127:0] = {128{aesimc_e2_q}} & crypt2_d_e2_q[127:0]; - - maia_cx_aesed2 uaesed2( - .aes_din (crypt2_d_e2_q[127:0]), - .aes_shf (aes_shf_e2_q[15:0]), - .aesd_out (aesd_out[127:0]), - .aese_out (aese_out[127:0]), - .aesemc_out (aesemc_out[127:0]), - .aesdimc_out (aesdimc_out[127:0]) -); - - maia_cx_aesmc uaesmc( - .d_in (aesmc_in[127:0]), - .mc (aesmc_out[127:0]) -); - - maia_cx_aesimc uaesimc( - .d_in (aesimc_in[127:0]), - .imc (aesimc_out[127:0]) -); - - maia_cx_pmull upmull( - .a_in (crypt2_d_e2_q[63:0]), - .b_in (crypt2_d_e2_q[127:64]), - .p_out (pmull_out[127:0]) -); - -assign crypt2_out_e2[127:0] = ({128{aesd_e2_q & ~aesdimc_e2_q}} & aesd_out[127:0]) - | ({128{aese_e2_q & ~aesemc_e2_q}} & aese_out[127:0]) - | ({128{aesmc_e2_q}} & aesmc_out[127:0]) - | ({128{aesemc_e2_q}} & aesemc_out[127:0]) - | ({128{aesimc_e2_q}} & aesimc_out[127:0]) - | ({128{aesdimc_e2_q}} & aesdimc_out[127:0]) - | ({128{sha_inst_e2_q}} & crypt2_d_e2_q[127:0]) - | ({128{pmull_e2_q}} & pmull_out[127:0]); - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: ucrypt2_e3 - if (ival_e2_q==1'b1) begin - crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY crypt2_out_e2[127:0]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e2_q==1'b0)); - else begin - crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -//----------------------------------------------------------------------------- -// regional clock gating (RCG) terms -//----------------------------------------------------------------------------- - -assign crypt2_active = (ival_e1_q | ival_e2_q); - - -endmodule - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v deleted file mode 100644 index 3654c6017b..0000000000 --- a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v +++ /dev/null @@ -1,713 +0,0 @@ - -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2013-2014 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// Filename : $RCSfile: maia_cx_crypt3.v $ -// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ -// Revision : $Revision: 70482 $ -// Release Information : Cortex-A72-r1p0-00rel0 -// -//----------------------------------------------------------------------------- -// Verilog-2001 (IEEE Std 1364-2001) -//----------------------------------------------------------------------------- - -//# -//# Overview -//# ======== -//# - -// This block does the following operations: -// - SHA 3-input operations: sha1cpm, sha1su0, sha256h, sha256h2, sha256su1 - -//# -//# Module Declaration -//# ================== -//# - -`include "maia_header.v" - -module maia_cx_crypt3 ( - -//# -//# Interface Signals -//# ================= -//# - -// Global inputs - ck_gclkcx_crypt, - cx_reset3, - -// Control inputs -// -// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to -// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q, -// which allows the operands to be stored in flops. We also get inputs indicating which -// instruction is to be computed. -// -// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that -// we should begin the computation. -// -// There are 4 execution stages, E2-E5. - ival_e1_q, - sha1c_e1_q, - sha1p_e1_q, - sha1m_e1_q, - sha256h_e1_q, - sha256h2_e1_q, - sha256su1_e1_q, - ival_e2_q, -// Data inputs - qn_e1_q, - qm_e1_q, - qd_e2_q, -// Outputs - crypt3_out_e6_q, - crypt3_active -); - - -//# -//# Interface Signals -//# ================= -//# - -// Global inputs - input ck_gclkcx_crypt; - input cx_reset3; - -// Control inputs -// -// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to -// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q, -// which allows the operands to be stored in flops. We also get inputs indicating which -// instruction is to be computed. -// -// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that -// we should begin the computation. -// -// There are 4 execution stages, E2-E5. - input ival_e1_q; - input sha1c_e1_q; // sha hash update (choose) - input sha1p_e1_q; // sha hash update (parity) - input sha1m_e1_q; // sha hash update (majority) - input sha256h_e1_q; // sha256 hash update - input sha256h2_e1_q; // sha256 hash update 2 - input sha256su1_e1_q; // sha256 schedule update 1 - input ival_e2_q; -// Data inputs - input [127:0] qn_e1_q; // qn arrives with first uop on {srcb,srca} - input [127:0] qm_e1_q; // qm arrives with first uop on {srcd,srcc} - input [127:0] qd_e2_q; // qd arrives with second uop on {srcb,srca} -// Outputs - output [127:0] crypt3_out_e6_q; - output crypt3_active; - -//# -//# Internal Signals - Automatic Declarations -//# ========================================= -//# - wire [127: 0] crypt3_out_e5; - reg [127: 0] crypt3_out_e6_q; - wire firstop_recvd_e1; - reg firstop_recvd_e2_q; - reg ival_e3_q; - reg ival_e4_q; - reg ival_e5_q; - wire [127: 0] newx_e2; - wire [127: 0] newx_e3; - wire [127: 0] newx_e4; - wire [127: 0] newy_e2; - wire [127: 0] newy_e3; - wire [127: 0] newy_e4; - reg [127: 0] qm_e2_q; - reg [127: 0] qn_e2_q; - wire [127: 0] sha1_xin_e2; - wire [ 31: 0] sha1_yin_e2; - wire [ 31: 0] sha1_zin_e2; - wire sha1c_e2; - reg sha1c_e2_q; - reg sha1c_e3_q; - reg sha1c_e4_q; - reg sha1c_e5_q; - wire sha1cpm_e2; - wire sha1cpm_e3; - wire sha1cpm_e4; - wire sha1cpm_e5; - wire [127: 0] sha1cpm_x_e2; - wire [127: 0] sha1cpm_x_e3; - wire [127: 0] sha1cpm_x_e4; - wire [127: 0] sha1cpm_x_e5; - wire [127: 0] sha1cpm_y_e2; - wire [127: 0] sha1cpm_y_e3; - wire [127: 0] sha1cpm_y_e4; -// verilint unused_sigs off - wire [ 31: 0] sha1cpm_y_e5; -// verilint unused_sigs on - wire sha1m_e2; - reg sha1m_e2_q; - reg sha1m_e3_q; - reg sha1m_e4_q; - reg sha1m_e5_q; - wire sha1p_e2; - reg sha1p_e2_q; - reg sha1p_e3_q; - reg sha1p_e4_q; - reg sha1p_e5_q; - wire [127: 0] sha256_xin_e2; - wire [127: 0] sha256_yin_e2; - wire [ 31: 0] sha256_zin_e2; - wire sha256h2_e2; - reg sha256h2_e2_q; - reg sha256h2_e3_q; - reg sha256h2_e4_q; - reg sha256h2_e5_q; - wire sha256h_e2; - reg sha256h_e2_q; - reg sha256h_e3_q; - reg sha256h_e4_q; - reg sha256h_e5_q; - wire [127: 0] sha256h_x_e2; - wire [127: 0] sha256h_x_e3; - wire [127: 0] sha256h_x_e4; - wire [127: 0] sha256h_x_e5; - wire [127: 0] sha256h_y_e2; - wire [127: 0] sha256h_y_e3; - wire [127: 0] sha256h_y_e4; - wire [127: 0] sha256h_y_e5; - wire sha256hh2_e2; - wire sha256hh2_e3; - wire sha256hh2_e4; - wire sha256su1_e2; - reg sha256su1_e2_q; - reg sha256su1_e3_q; - reg sha256su1_e4_q; - reg sha256su1_e5_q; - wire [ 63: 0] sha256su1_x_e3; - wire [ 63: 0] sha256su1_x_e4; - wire [127: 0] x_e2; - wire [127: 0] x_e3; - reg [127: 0] x_e3_q; - wire [127: 0] x_e4; - reg [127: 0] x_e4_q; - wire [127: 0] x_e5; - reg [127: 0] x_e5_q; - wire [127: 0] y_e2; - wire [127: 0] y_e3; - reg [127: 0] y_e3_q; - wire [127: 0] y_e4; - reg [127: 0] y_e4_q; - wire [127: 0] y_e5; - reg [127: 0] y_e5_q; - wire [127: 0] z_e2; - wire [ 95: 0] z_e3; - reg [ 95: 0] z_e3_q; - wire [ 63: 0] z_e4; - reg [ 63: 0] z_e4_q; - wire [ 31: 0] z_e5; - reg [ 31: 0] z_e5_q; - -//# -//# Main Code -//# ========= -//# -// - -// set when ival_e1_q first received, and held until the 2nd uop (ival_e2_q) is received -assign firstop_recvd_e1 = (ival_e1_q | (firstop_recvd_e2_q & ~ival_e2_q)); - -// ival and instruction flops - -// reset flop since 1st uop of crypto pair can be flushed due to SWDW nuke, thus might -// have received ival_e2_q without ever receiving ival_e1_q (since it was flushed). thus -// want firstop_recvd_e2_q to be 0 (not X) to stop X-prop - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt or posedge cx_reset3) - begin: ufirstop_recvd_e2_q - if (cx_reset3 == 1'b1) - firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'b0}}; -`ifdef MAIA_XPROP_FLOP - else if (cx_reset3==1'b0) - firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1; - else - firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; -`else - else - firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1; -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// reset flop(s) since feeds into active signal used for RCG - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt or posedge cx_reset3) - begin: uival_e3_q - if (cx_reset3 == 1'b1) - ival_e3_q <= `MAIA_DFF_DELAY {1{1'b0}}; -`ifdef MAIA_XPROP_FLOP - else if (cx_reset3==1'b0) - ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q; - else - ival_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; -`else - else - ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q; -`endif - end - // verilint flop_checks on - // end of Macro DFF - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt or posedge cx_reset3) - begin: uival_e4_q - if (cx_reset3 == 1'b1) - ival_e4_q <= `MAIA_DFF_DELAY {1{1'b0}}; -`ifdef MAIA_XPROP_FLOP - else if (cx_reset3==1'b0) - ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q; - else - ival_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; -`else - else - ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q; -`endif - end - // verilint flop_checks on - // end of Macro DFF - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt or posedge cx_reset3) - begin: uival_e5_q - if (cx_reset3 == 1'b1) - ival_e5_q <= `MAIA_DFF_DELAY {1{1'b0}}; -`ifdef MAIA_XPROP_FLOP - else if (cx_reset3==1'b0) - ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q; - else - ival_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; -`else - else - ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q; -`endif - end - // verilint flop_checks on - // end of Macro DFF - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uinst_e2 - if (ival_e1_q==1'b1) begin - sha1c_e2_q <= `MAIA_DFF_DELAY sha1c_e1_q; - sha1p_e2_q <= `MAIA_DFF_DELAY sha1p_e1_q; - sha1m_e2_q <= `MAIA_DFF_DELAY sha1m_e1_q; - sha256h_e2_q <= `MAIA_DFF_DELAY sha256h_e1_q; - sha256h2_e2_q <= `MAIA_DFF_DELAY sha256h2_e1_q; - sha256su1_e2_q <= `MAIA_DFF_DELAY sha256su1_e1_q; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e1_q==1'b0)); - else begin - sha1c_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1p_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1m_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h2_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256su1_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// stop X-prop if 1st uop was nuked due to swdw_nuke and 2nd was issued - -assign sha1c_e2 = firstop_recvd_e2_q & sha1c_e2_q; -assign sha1p_e2 = firstop_recvd_e2_q & sha1p_e2_q; -assign sha1m_e2 = firstop_recvd_e2_q & sha1m_e2_q; -assign sha256h_e2 = firstop_recvd_e2_q & sha256h_e2_q; -assign sha256h2_e2 = firstop_recvd_e2_q & sha256h2_e2_q; -assign sha256su1_e2 = firstop_recvd_e2_q & sha256su1_e2_q; - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uinst_e3 - if (ival_e2_q==1'b1) begin - sha1c_e3_q <= `MAIA_DFF_DELAY sha1c_e2; - sha1p_e3_q <= `MAIA_DFF_DELAY sha1p_e2; - sha1m_e3_q <= `MAIA_DFF_DELAY sha1m_e2; - sha256h_e3_q <= `MAIA_DFF_DELAY sha256h_e2; - sha256h2_e3_q <= `MAIA_DFF_DELAY sha256h2_e2; - sha256su1_e3_q <= `MAIA_DFF_DELAY sha256su1_e2; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e2_q==1'b0)); - else begin - sha1c_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1p_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1m_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h2_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256su1_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uinst_e4 - if (ival_e3_q==1'b1) begin - sha1c_e4_q <= `MAIA_DFF_DELAY sha1c_e3_q; - sha1p_e4_q <= `MAIA_DFF_DELAY sha1p_e3_q; - sha1m_e4_q <= `MAIA_DFF_DELAY sha1m_e3_q; - sha256h_e4_q <= `MAIA_DFF_DELAY sha256h_e3_q; - sha256h2_e4_q <= `MAIA_DFF_DELAY sha256h2_e3_q; - sha256su1_e4_q <= `MAIA_DFF_DELAY sha256su1_e3_q; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e3_q==1'b0)); - else begin - sha1c_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1p_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1m_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h2_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256su1_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uinst_e5 - if (ival_e4_q==1'b1) begin - sha1c_e5_q <= `MAIA_DFF_DELAY sha1c_e4_q; - sha1p_e5_q <= `MAIA_DFF_DELAY sha1p_e4_q; - sha1m_e5_q <= `MAIA_DFF_DELAY sha1m_e4_q; - sha256h_e5_q <= `MAIA_DFF_DELAY sha256h_e4_q; - sha256h2_e5_q <= `MAIA_DFF_DELAY sha256h2_e4_q; - sha256su1_e5_q <= `MAIA_DFF_DELAY sha256su1_e4_q; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e4_q==1'b0)); - else begin - sha1c_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1p_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha1m_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256h2_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - sha256su1_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// E1 - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uops_e2 - if (ival_e1_q==1'b1) begin - qm_e2_q[127:0] <= `MAIA_DFF_DELAY qm_e1_q[127:0]; - qn_e2_q[127:0] <= `MAIA_DFF_DELAY qn_e1_q[127:0]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e1_q==1'b0)); - else begin - qm_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - qn_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// E2 -assign x_e2[127:0] = qd_e2_q[127:0]; -assign y_e2[127:0] = qn_e2_q[127:0]; -assign z_e2[127:0] = qm_e2_q[127:0]; - -assign sha1_xin_e2[127:0] = {128{sha1cpm_e2}} & x_e2[127:0]; -assign sha1_yin_e2[ 31:0] = { 32{sha1cpm_e2}} & y_e2[ 31:0]; -assign sha1_zin_e2[ 31:0] = { 32{sha1cpm_e2}} & z_e2[ 31:0]; - -// sha1 hash update - maia_cx_sha1cpm usha1cpm_e2( - .choose (sha1c_e2_q), - .parity (sha1p_e2_q), - .majority (sha1m_e2_q), - .x (sha1_xin_e2[127:0]), - .y (sha1_yin_e2[31:0]), - .z (sha1_zin_e2[31:0]), - .newx (sha1cpm_x_e2[127:0]), - .newy (sha1cpm_y_e2[31:0]) -); -assign sha1cpm_y_e2[127:32] = {96{sha1cpm_e2}} & y_e2[127:32]; - -assign sha256_xin_e2[127:0] = {128{sha256hh2_e2}} & x_e2[127:0]; -assign sha256_yin_e2[127:0] = {128{sha256hh2_e2}} & y_e2[127:0]; -assign sha256_zin_e2[ 31:0] = { 32{sha256hh2_e2}} & z_e2[ 31:0]; - -// sha256 hash update (1 and 2) - maia_cx_sha256h32 usha256h32_e2( - .x (sha256_xin_e2[127:0]), - .y (sha256_yin_e2[127:0]), - .z (sha256_zin_e2[31:0]), - .newx (sha256h_x_e2[127:0]), - .newy (sha256h_y_e2[127:0]) -); - -// mux results -assign sha1cpm_e2 = sha1c_e2 | sha1p_e2 | sha1m_e2; -assign sha256hh2_e2 = sha256h_e2 | sha256h2_e2; -assign newx_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_x_e2[127:0]) - | ({128{sha256hh2_e2}} & sha256h_x_e2[127:0]) - | ({128{sha256su1_e2}} & x_e2[127:0]); -assign newy_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_y_e2[127:0]) - | ({128{sha256hh2_e2}} & sha256h_y_e2[127:0]) - | ({128{sha256su1_e2}} & {z_e2[31:0], y_e2[127:32]}); - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uops_e3 - if (ival_e2_q==1'b1) begin - x_e3_q[127:0] <= `MAIA_DFF_DELAY newx_e2[127:0]; - y_e3_q[127:0] <= `MAIA_DFF_DELAY newy_e2[127:0]; - z_e3_q[95:0] <= `MAIA_DFF_DELAY z_e2[127:32]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e2_q==1'b0)); - else begin - x_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - y_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - z_e3_q[95:0] <= `MAIA_DFF_DELAY {96{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// E3 -assign x_e3[127:0] = x_e3_q[127:0]; -assign y_e3[127:0] = y_e3_q[127:0]; -assign z_e3[95:0] = z_e3_q[95:0]; - -// sha1 hash update - maia_cx_sha1cpm usha1cpm_e3( - .choose (sha1c_e3_q), - .parity (sha1p_e3_q), - .majority (sha1m_e3_q), - .x (x_e3[127:0]), - .y (y_e3[31:0]), - .z (z_e3[31:0]), - .newx (sha1cpm_x_e3[127:0]), - .newy (sha1cpm_y_e3[31:0]) -); -assign sha1cpm_y_e3[127:32] = y_e3[127:32]; - -// sha256 hash update (1 and 2) - maia_cx_sha256h32 usha256h32_e3( - .x (x_e3[127:0]), - .y (y_e3[127:0]), - .z (z_e3[31:0]), - .newx (sha256h_x_e3[127:0]), - .newy (sha256h_y_e3[127:0]) -); - -// sha256 schedule update 1, cycle 1 - maia_cx_sha256su1 usha256su1_e3( - .sha256su1_op (sha256su1_e3_q), - .x (x_e3[63:0]), // qd[63:0] - .y (y_e3[63:0]), // qn[95:32] - .z (z_e3[95:32]), // qm[127:64] - .newx (sha256su1_x_e3[63:0]) -); - -// mux results -assign sha1cpm_e3 = sha1c_e3_q | sha1p_e3_q | sha1m_e3_q; -assign sha256hh2_e3 = sha256h_e3_q | sha256h2_e3_q; -assign newx_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_x_e3[127:0]) - | ({128{sha256hh2_e3 }} & sha256h_x_e3[127:0]) - | ({128{sha256su1_e3_q}} & {x_e3[127:64], sha256su1_x_e3[63:0]}); -assign newy_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_y_e3[127:0]) - | ({128{sha256hh2_e3 }} & sha256h_y_e3[127:0]) - | ({128{sha256su1_e3_q}} & {y_e3[127:0]}); - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uops_e4 - if (ival_e3_q==1'b1) begin - x_e4_q[127:0] <= `MAIA_DFF_DELAY newx_e3[127:0]; - y_e4_q[127:0] <= `MAIA_DFF_DELAY newy_e3[127:0]; - z_e4_q[63:0] <= `MAIA_DFF_DELAY z_e3[95:32]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e3_q==1'b0)); - else begin - x_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - y_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - z_e4_q[63:0] <= `MAIA_DFF_DELAY {64{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// E4 -assign x_e4[127:0] = x_e4_q[127:0]; -assign y_e4[127:0] = y_e4_q[127:0]; -assign z_e4[63:0] = z_e4_q[63:0]; - -// sha1 hash update - maia_cx_sha1cpm usha1cpm_e4( - .choose (sha1c_e4_q), - .parity (sha1p_e4_q), - .majority (sha1m_e4_q), - .x (x_e4[127:0]), - .y (y_e4[31:0]), - .z (z_e4[31:0]), - .newx (sha1cpm_x_e4[127:0]), - .newy (sha1cpm_y_e4[31:0]) -); -assign sha1cpm_y_e4[127:32] = y_e4[127:32]; - -// sha256 hash update (1 and 2) - maia_cx_sha256h32 usha256h32_e4( - .x (x_e4[127:0]), - .y (y_e4[127:0]), - .z (z_e4[31:0]), - .newx (sha256h_x_e4[127:0]), - .newy (sha256h_y_e4[127:0]) -); - -// sha256 schedule update 1, cycle 2 - maia_cx_sha256su1 usha256su1_e4( - .sha256su1_op (sha256su1_e4_q), - .x (x_e4[127:64]), // qd[127:64] - .y (y_e4[127:64]), // {qm[31:0], qn[127:96]} - .z (x_e4[63:0]), // sha256su1_x_e3[63:0] - .newx (sha256su1_x_e4[63:0]) -); - -// mux results -assign sha1cpm_e4 = sha1c_e4_q | sha1p_e4_q | sha1m_e4_q; -assign sha256hh2_e4 = sha256h_e4_q | sha256h2_e4_q; -assign newx_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_x_e4[127:0]) - | ({128{sha256hh2_e4 }} & sha256h_x_e4[127:0]) - | ({128{sha256su1_e4_q}} & {sha256su1_x_e4[63:0], x_e4[63:0]}); -assign newy_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_y_e4[127:0]) - | ({128{sha256hh2_e4 }} & sha256h_y_e4[127:0]); - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: uops_e5 - if (ival_e4_q==1'b1) begin - x_e5_q[127:0] <= `MAIA_DFF_DELAY newx_e4[127:0]; - y_e5_q[127:0] <= `MAIA_DFF_DELAY newy_e4[127:0]; - z_e5_q[31:0] <= `MAIA_DFF_DELAY z_e4[63:32]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e4_q==1'b0)); - else begin - x_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - y_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - z_e5_q[31:0] <= `MAIA_DFF_DELAY {32{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - -// E5 -assign x_e5[127:0] = x_e5_q[127:0]; -assign y_e5[127:0] = y_e5_q[127:0]; -assign z_e5[31:0] = z_e5_q[31:0]; - -// sha1 hash update - maia_cx_sha1cpm usha1cpm_e5( - .choose (sha1c_e5_q), - .parity (sha1p_e5_q), - .majority (sha1m_e5_q), - .x (x_e5[127:0]), - .y (y_e5[31:0]), - .z (z_e5[31:0]), - .newx (sha1cpm_x_e5[127:0]), - .newy (sha1cpm_y_e5[31:0]) -); - -// sha256 hash update (1 and 2) - maia_cx_sha256h32 usha256h32_e5( - .x (x_e5[127:0]), - .y (y_e5[127:0]), - .z (z_e5[31:0]), - .newx (sha256h_x_e5[127:0]), - .newy (sha256h_y_e5[127:0]) -); - -// mux results -assign sha1cpm_e5 = sha1c_e5_q | sha1p_e5_q | sha1m_e5_q; -assign crypt3_out_e5[127:0] = ({128{sha1cpm_e5}} & sha1cpm_x_e5[127:0]) - | ({128{sha256h_e5_q}} & sha256h_x_e5[127:0]) - | ({128{sha256h2_e5_q}} & sha256h_y_e5[127:0]) - | ({128{sha256su1_e5_q}} & x_e5[127:0]); - - // Macro DFF called - // verilint flop_checks off - always @(posedge ck_gclkcx_crypt) - begin: ures_e6 - if (ival_e5_q==1'b1) begin - crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY crypt3_out_e5[127:0]; - end -`ifdef MAIA_XPROP_FLOP - else if ((ival_e5_q==1'b0)); - else begin - crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; - end -`endif - end - // verilint flop_checks on - // end of Macro DFF - - -//----------------------------------------------------------------------------- -// regional clock gating (RCG) terms -//----------------------------------------------------------------------------- - -assign crypt3_active = (ival_e1_q | - ival_e2_q | - ival_e3_q | - ival_e4_q | - ival_e5_q - ); - - -endmodule - -//ARMAUTO UNDEF START -`define MAIA_UNDEFINE -`include "maia_header.v" -`undef MAIA_UNDEFINE -//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/Makefile.inc b/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/Makefile.inc deleted file mode 100644 index 3edf5c4ec5..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/Makefile.inc +++ /dev/null @@ -1,67 +0,0 @@ -#----------------------------------------------------------------------------- -# The confidential and proprietary information contained in this file may -# only be used by a person authorised under and to the extent permitted -# by a subsisting licensing agreement from ARM Limited or its affiliates. -# -# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates. -# ALL RIGHTS RESERVED -# -# This entire notice must be reproduced on all copies of this file -# and copies of this file may only be made by a person if such person is -# permitted to do so under the terms of a subsisting license agreement -# from ARM Limited or its affiliates. -# -# Release Information : HERCULESAE-MP106-r0p1-00eac0 -# -#----------------------------------------------------------------------------- -# Makefile include file for AArch32 crypto. This must be included from the -# top-level Makefile; it is not a standalone Makefile. -#----------------------------------------------------------------------------- - -# Note these variables must only be used in places where Make reads their -# immediate values rather than their deferred values. This is because all -# the include files use the same variables and the deferred evaluation will -# yeild the last values set by the last include file. They can be used in the -# target and prerequisite sections of rule definitions, which are evaluated -# immediately, but not in the recipe, where evaluation is deferred. -srcdir := aarch32/crypto -common_srcdir := common/crypto -libdir := common/shared -dstdir := aarch32/crypto -target := $(dstdir)/crypto.elf -csrcs := $(wildcard $(common_srcdir)/*.c) -asmsrcs := $(wildcard $(srcdir)/*.s) -libsrcs := $(wildcard $(libdir)/*.c) -cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \ - $(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs)) -asmobjs := $(patsubst %.s,%.o,$(asmsrcs)) - -# Find common C files (the source files are not in the build target directory) -vpath %.c $(common_srcdir) $(libdir) - -# Change the CPU target to include crypto for all files that need compiling -$(asmobjs): ARCH = armv8-a+crypto - -$(asmobjs): %.o: %.s - @echo " [ASM ] $<" - @$(ASM32) $(ASM_OPTS_AARCH32) $< -o $@ - -$(cobjs): $(dstdir)/%.o: %.c - @echo " [CC $(CC32) ] $<" -ifeq ($(strip $(GCC)), yes) - @$(CC32) $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -mword-relocations -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@ -else - @$(CC32) -mfpu=none $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@ -endif - -# Link. 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z0MllMgS8F3^!)^Ue-@7u22Lu_6O-vKJywPWdVa!)V6gxO=^1Bez~SkGLxvnqaLM^C z4CJtbWiB1bSS1Kxce@aT;t?@g5wXaR&cR)+^|F-Loz~^7~GPi z<6%k8J_4MD;Fbs0!|uTa-;wMq86Atm_XkKaB8o_Fl#=^MpisbpmVk#hahxC5kX*hAc}?37)Z5% zapG?uP5-Ah`S)z{nTR~*AO)`*M#ysxc@ZYJMc)Yl0^3P{hs=W?1js6nfvBG$)OP~% l^B~d#AOx{q`oc+gAp=97-~Bq-{*k-1{}GaEUuWp{{{y)79|r&c diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto_functions.s b/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto_functions.s deleted file mode 100644 index e8befa71b4..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto_functions.s +++ /dev/null @@ -1,212 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited or its affiliates. -// -// (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited or its affiliates. -// -// Release Information : HERCULESAE-MP106-r0p1-00eac0 -// -//------------------------------------------------------------------------------ -// Description: -// -// This file defines assembler functions that are called from C in the main -// crypto test -//------------------------------------------------------------------------------ - - .section testcode, "ax", %progbits - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - - .macro aes128_key_expand_step rcon - VTBL.8 d26, {d22, d23}, d28 - VTBL.8 d27, {d22, d23}, d29 - AESE.8 q13, q12 - VMOV.I32 q15, #\rcon - VEOR q13, q13, q15 - VEXT.8 q15, q12, q11, #12 - VEOR q11, q11, q15 - VEXT.8 q15, q12, q15, #12 - VEOR q11, q11, q15 - VEXT.8 q15, q12, q15, #12 - VEOR q11, q11, q15 - VEOR q11, q11, q13 - .endm - -//------------------------------------------------------------------------------ -// Function: aes128_key_expand -//------------------------------------------------------------------------------ - -.global aes128_key_expand -.type aes128_key_expand, %function - -aes128_key_expand: - // C arguments: - // r0: const unsigned char *key_in - // r1: unsigned char *key_out - // Return: void - VLD1.8 {d22-d23}, [r0] - MOV r2, #0 - VDUP.8 q12, r2 - LDR r2, =0x0c0f0e0d - VDUP.32 q14, r2 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x01 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x02 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x04 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x08 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x10 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x20 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x40 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x80 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x1B - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - aes128_key_expand_step 0x36 - VST1.8 {d22}, [r1] - ADD r1, r1, #8 - VST1.8 {d23}, [r1] - ADD r1, r1, #8 - - BX lr - -//------------------------------------------------------------------------------ -// Function: aes128_ecb_encrypt -//------------------------------------------------------------------------------ - -.global aes128_ecb_encrypt -.type aes128_ecb_encrypt, %function - -aes128_ecb_encrypt: - // C arguments: - // r0: const unsigned char *key - // r1: const unsigned char *in_data - // r2: unsigned char *out_data - // r3: unsigned int size - // Return: void - VLD1.8 {d10-d13}, [r0] - ADD r0, r0, #32 - VLD1.8 {d14-d17}, [r0] - ADD r0, r0, #32 - VLD1.8 {d18-d21}, [r0] - ADD r0, r0, #32 - VLD1.8 {d22-d25}, [r0] - ADD r0, r0, #32 - VLD1.8 {d26-d29}, [r0] - ADD r0, r0, #32 - VLD1.8 {d30-d31}, [r0] - -aes128_ecb_enc_loop: - // Load data - VLD1.8 {d0-d3}, [r1] - ADD r1, r1, #32 - // Round 1 - AESE.8 q0, q5 - AESMC.8 q0, q0 - AESE.8 q1, q5 - AESMC.8 q1, q1 - // Round 2 - AESE.8 q0, q6 - AESMC.8 q0, q0 - AESE.8 q1, q6 - AESMC.8 q1, q1 - // Round 3 - AESE.8 q0, q7 - AESMC.8 q0, q0 - AESE.8 q1, q7 - AESMC.8 q1, q1 - // Round 4 - AESE.8 q0, q8 - AESMC.8 q0, q0 - AESE.8 q1, q8 - AESMC.8 q1, q1 - // Round 5 - AESE.8 q0, q9 - AESMC.8 q0, q0 - AESE.8 q1, q9 - AESMC.8 q1, q1 - // Round 6 - AESE.8 q0, q10 - AESMC.8 q0, q0 - AESE.8 q1, q10 - AESMC.8 q1, q1 - // Round 7 - AESE.8 q0, q11 - AESMC.8 q0, q0 - AESE.8 q1, q11 - AESMC.8 q1, q1 - // Round 8 - AESE.8 q0, q12 - AESMC.8 q0, q0 - AESE.8 q1, q12 - AESMC.8 q1, q1 - // Round 9 - AESE.8 q0, q13 - AESMC.8 q0, q0 - AESE.8 q1, q13 - AESMC.8 q1, q1 - - // Round 10 - AESE.8 q0, q14 - PLD [r1, #64] - AESE.8 q1, q14 - VEOR q0, q0, q15 - SUBS r3, r3, #16 - VST1.8 {d0-d1}, [r2] - ADD r2, r2, #16 - BEQ aes128_ecb_enc_exit - - VEOR q1, q1, q15 - SUBS r3, r3, #16 - VST1.8 {d2-d3}, [r2] - ADD r2, r2, #16 - BGT aes128_ecb_enc_loop - -aes128_ecb_enc_exit: - BX lr - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/Makefile.inc b/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/Makefile.inc deleted file mode 100644 index 0c07d79b03..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/Makefile.inc +++ /dev/null @@ -1,63 +0,0 @@ -#------------------------------------------------------------------------------- -# The confidential and proprietary information contained in this file may -# only be used by a person authorised under and to the extent permitted -# by a subsisting licensing agreement from ARM Limited or its affiliates. -# -# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates. -# ALL RIGHTS RESERVED -# -# This entire notice must be reproduced on all copies of this file -# and copies of this file may only be made by a person if such person is -# permitted to do so under the terms of a subsisting license agreement -# from ARM Limited or its affiliates. -# -# Release Information : HERCULESAE-MP106-r0p1-00eac0 -# -#------------------------------------------------------------------------------- -# Makefile include file for AArch64 crypto. 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They can be used in the -# target and prerequisite sections of rule definitions, which are evaluated -# immediately, but not in the recipe, where evaluation is deferred. -srcdir := aarch64/crypto -common_srcdir := common/crypto -libdir := common/shared -dstdir := aarch64/crypto -target := $(dstdir)/crypto.elf -asmsrcs := $(wildcard $(srcdir)/*.s) -csrcs := $(wildcard $(common_srcdir)/*.c) -libsrcs := $(wildcard $(libdir)/*.c) -asmobjs := $(patsubst %.s,%.o,$(asmsrcs)) -cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \ - $(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs)) - -# Find common C files (the source files are not in the build target directory) -vpath %.c $(common_srcdir) $(libdir) - -# Change the CPU target to include crypto for all files that need compiling -$(cobjs) $(asmobjs): ARCH = armv8-a+crypto - -$(asmobjs): %.o: %.s - @echo " [ASM ] $<" - @$(ASM64) $(ASM_OPTS_AARCH64) $< -o $@ - -$(cobjs): $(dstdir)/%.o: %.c - @echo " [CC ] $<" - @$(CC64) $(CC_OPTS_AARCH64) -I$(common_shared) $< -o $@ - -# Link. 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z91p}BKYB{5#pl|U2)Kz)tiSN>mbbgz@|17q{9O{-dWid7-0OJpBTn7+gQQen={wI& zh}WsLcof@#Uw9h@#jV|Z%^u+$NAVS2e2crkTw>DQRrf3X39vZ2t?=Sy+&dzk|J{YM zRDb;*>0RJI;#>Vvxk}^D<=FliCB$8Lj*t4qyu5UOU3<0<@z0Mae<2Ydobql@z+X7! zJvDz^IsKmE-%P;2ns)r}(|^bFXIH6ABG#@rUg!OilIHz10sr!< -#include -#include -#include - -#include "benchmark.h" - -static const uint8_t key[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, - 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}; - -extern const uint8_t aes128_ecb_encrypt_input[][4096]; -extern const uint8_t aes128_ecb_encrypt_ref_output[][4096]; -extern uint8_t aes128_ecb_encrypt_output[][4096]; - -// Function prototypes for asm functions -extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out); -extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size); - -extern uint32_t have_crypto; - -int main() -{ - int bs; - int i; - int fail = 0; - - uint8_t kv[176]; - - started(); - - if ( !have_crypto ) { - printf("Cryptographic extension not available on this PE.\n"); - exit(144); // something gross - } - - aes128_key_expand(key, kv); - - for (i = 0, bs = 16; bs <= 4096; i++, bs*=2) { - uint32_t cmpres; - - aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs); - - cmpres = (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0); - - aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs); - - cmpres |= (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0); - - if (cmpres != 0) - fail = 1; - } - - return fail; -} - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc deleted file mode 100644 index 901f74f773..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# The confidential and proprietary information contained in this file may -# only be used by a person authorised under and to the extent permitted -# by a subsisting licensing agreement from ARM Limited. -# -# (C) COPYRIGHT 2011-2013 ARM Limited. -# ALL RIGHTS RESERVED -# -# This entire notice must be reproduced on all copies of this file -# and copies of this file may only be made by a person if such person is -# permitted to do so under the terms of a subsisting license agreement -# from ARM Limited. -# -############################################################################### -# Makefile.inc for crypto64 -# setup source paths (crypto64) - -crypto64_base = crypto64 -crypto64_src = $(crypto64_base)/src -crypto64_obj = $(crypto64_base)/obj -crypto64_elf = $(crypto64_base)/elf - -#rules for crypto64 - -crypto64_asm_obj = $(incl_obj)/benchmark_boot_a64.o $(incl_obj)/vectors.o $(incl_obj)/num_cpus_a64.o $(crypto64_obj)/cryptolib_asm64.o -crypto64_c_obj = $(incl_obj)/sys_a64.o $(incl_obj)/stackheap_a64.o $(crypto64_obj)/cryptodata.o $(crypto64_obj)/crypto_test.o - -crypto64: clean_crypto64 $(crypto64_elf)/crypto64.elf - -$(crypto64_obj)/%.o: $(crypto64_src)/%.c - $(CC_A64) $(CC_A64_OPTS) $< -o $@ - -$(crypto64_obj)/%.o: $(crypto64_src)/%.s - $(AS_A64) $(AS_A64_OPTS) $< -o $@ - -$(crypto64_elf)/crypto64.elf: $(crypto64_asm_obj) $(crypto64_c_obj) - $(LINK_A64) $(LINK_A64_OPTS) $(crypto64_asm_obj) $(crypto64_c_obj) -o $@ - -clean_crypto64: - \rm -f $(crypto64_asm_obj) $(crypto64_c_obj) $(crypto64_elf)/crypto64.elf - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf deleted file mode 100644 index 8a1b9e22b50ff63c8b5b62a7f87a2af03c0257ec..0000000000000000000000000000000000000000 GIT binary patch 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z>!U&77sWsg7bnL>zuF%krDS11prblBDYs8_t-YrU6<#U81!4Btpy-V4-jy`B>0*hcu|n%Ec8_HHhLI_z{DX>aLqyx3Qh817z$`A2TIW&0Ptm1L zKvWF^=yBEhTBwadV|px6v{H2sJ#|pB_f;D^my+nItEM=P`mqu__EtwMI}itu%*3S< z&={f!9#qD`C;mR<5LHWI@&>c!J_c`yDJS%S=%Ak%RSyebLS8 zTQ)&izKWAfsq)|sas1*rXoK7Gli8N);!(6XSEDLEtVLhFVYtvgp -#include -#include - -#include "cryptolib.h" -#include "cryptodata.h" -#include "benchmark.h" - -#ifndef BLOCK_SIZE -#define BLOCK_SIZE 1024 -#endif - -#ifndef ITERATIONS -#define ITERATIONS 10 -#endif - -uint8_t get_aes_index( int block_size) -{ - uint8_t index = 0; - uint8_t i; - for (i=4; i<13; i++) - { - if ((block_size >> i) & 0x1) - { - index = i-4; - break; - } - } - return index; -} - -int main() -{ - uint32_t block_size; - uint8_t index; - uint32_t cmpres = 0; - uint8_t i; - - block_size = BLOCK_SIZE; - - uint8_t kv[176]; - printf("AES128-ECB encryption\n"); - index = get_aes_index(block_size); - BENCHSTART - for ( i = 0; i < ITERATIONS; i++) - { - aes128_key_expand(aes128_ecb_encrypt_key[index], kv); - LOOPSTART - aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[index], aes128_ecb_encrypt_output[index], block_size); - LOOPEND - } - cmpres |= memcmp(aes128_ecb_encrypt_output[index], aes128_ecb_encrypt_ref_output[index], block_size); - if (cmpres) - printf("AES128-ECB encryption failed\n"); - BENCHFINISHED -} - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c deleted file mode 100644 index e82d909e49..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c +++ /dev/null @@ -1,1591 +0,0 @@ -const unsigned char aes128_ecb_encrypt_key[][16] __attribute__((aligned(64))) = { - { 0x0a, 0x73, 0xd4, 0x55, 0x90, 0x00, 0x2f, 0xfc, 0xbf, 0x5d, 0x59, 0x92, 0x21, 0x10, 0xf2, 0x27 - }, - { 0xf5, 0x03, 0x1c, 0xe1, 0x1d, 0xbf, 0x4b, 0xa4, 0x6c, 0x7f, 0x50, 0x6f, 0xa8, 0xb3, 0xc5, 0xcf - }, - { 0x44, 0xf3, 0x3a, 0xcc, 0x56, 0x95, 0xf1, 0xa4, 0xe6, 0x5d, 0x3d, 0x7c, 0xe9, 0x53, 0xd2, 0x4f - }, - { 0x49, 0xa5, 0x1e, 0x2b, 0x9d, 0x86, 0x9a, 0x49, 0x63, 0xcb, 0x59, 0xcc, 0x74, 0xb7, 0x47, 0xc1 - }, - { 0x69, 0x3c, 0x5e, 0x36, 0x8c, 0x2e, 0x84, 0x01, 0xe2, 0x80, 0xae, 0x98, 0x48, 0x2c, 0x43, 0xa4 - }, - { 0x58, 0x3b, 0x3f, 0x1e, 0x59, 0x0a, 0x40, 0xc6, 0x92, 0x31, 0xc8, 0x29, 0xbf, 0xbd, 0x80, 0x70 - }, - { 0x79, 0xa7, 0x65, 0xe9, 0xad, 0x9f, 0x54, 0x3d, 0xf3, 0xd2, 0x78, 0xcb, 0x79, 0xa3, 0xb9, 0x40 - }, - { 0x7c, 0x6e, 0xba, 0x1d, 0xf1, 0xf7, 0xaf, 0x50, 0xde, 0xaa, 0x27, 0x4d, 0x9f, 0xcf, 0x44, 0xba - }, - { 0x3c, 0xaa, 0xb1, 0xb5, 0x49, 0x52, 0x3e, 0x4d, 0xd0, 0xb5, 0x73, 0x69, 0x48, 0x83, 0x0c, 0xa4 - }, - }; - -const unsigned char aes128_ecb_encrypt_input[][4096] __attribute__((aligned(64))) = { - { 0x95, 0x37, 0xcd, 0x23, 0x9e, 0x35, 0x01, 0x92, 0xed, 0x56, 0xe3, 0x97, 0x64, 0xe5, 0xb1, 0x3a - }, - { 0x51, 0xfa, 0xad, 0x26, 0xdf, 0xb1, 0x60, 0x90, 0x79, 0x45, 0xef, 0x42, 0x89, 0xa5, 0x91, 0x81, - 0x33, 0x16, 0x47, 0xb3, 0xc1, 0xab, 0x9a, 0x5f, 0x82, 0x8c, 0xa7, 0xef, 0x31, 0x97, 0x14, 0x91 - }, - { 0xee, 0x97, 0xfb, 0x63, 0x32, 0x8a, 0xf5, 0xa5, 0x90, 0xfa, 0x59, 0xfe, 0xa5, 0xcf, 0xa7, 0x14, - 0x2e, 0x35, 0x1c, 0xfe, 0xdb, 0xa0, 0x10, 0xd8, 0x49, 0xb3, 0x59, 0xfe, 0x24, 0x40, 0xe7, 0xb6, - 0xe2, 0x6d, 0x43, 0x6a, 0x93, 0x89, 0xfa, 0xb2, 0xc2, 0x01, 0x3d, 0x7e, 0x7a, 0x19, 0x7f, 0xdc, - 0x66, 0xb1, 0x38, 0x6a, 0x71, 0x4b, 0xb8, 0x48, 0xac, 0x9e, 0x51, 0x14, 0x39, 0x59, 0xef, 0x8a - }, - { 0x5d, 0xbe, 0x5b, 0x17, 0x95, 0xfc, 0x10, 0x45, 0xfb, 0xd9, 0x66, 0xc9, 0x58, 0x87, 0x84, 0x38, - 0x8e, 0x75, 0xe7, 0x3d, 0xc5, 0x5b, 0x41, 0x54, 0xc6, 0xae, 0x98, 0xbc, 0x24, 0x71, 0x08, 0x4f, - 0x1f, 0xbd, 0xf0, 0x8e, 0xee, 0x7a, 0xcc, 0x8e, 0x8d, 0xec, 0x6e, 0xcb, 0xa5, 0x5b, 0xf3, 0xe3, - 0x49, 0xaa, 0x04, 0x83, 0x0c, 0x8e, 0x16, 0xde, 0x18, 0xd9, 0x70, 0x70, 0x95, 0x0f, 0x9c, 0xad, - 0x61, 0x65, 0x47, 0x02, 0xce, 0x04, 0xf8, 0x2b, 0xd1, 0x4a, 0x57, 0x61, 0x73, 0x88, 0x82, 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0x12, 0x87, 0x6f - }, - }; - -const unsigned char aes128_ecb_encrypt_ref_output[][4096] __attribute__((aligned(64))) = { - { 0x24, 0x89, 0xab, 0xe4, 0x77, 0xdc, 0xdd, 0xcf, 0xeb, 0xc3, 0xca, 0xde, 0x5a, 0x52, 0x89, 0xaf - }, - { 0x8e, 0x25, 0x82, 0x01, 0x34, 0x2f, 0x89, 0x93, 0x12, 0x90, 0x47, 0xac, 0xc6, 0xc4, 0x8a, 0x62, - 0x54, 0xd2, 0x2b, 0xb5, 0x47, 0xc0, 0xdd, 0x20, 0x54, 0xe3, 0xd0, 0xbd, 0xf4, 0x81, 0xc4, 0x16 - }, - { 0x2c, 0x79, 0x73, 0x56, 0xbd, 0xa9, 0x2e, 0x0d, 0x33, 0x97, 0x94, 0x1d, 0xbc, 0x55, 0xc9, 0x59, - 0x11, 0x32, 0x0c, 0xc7, 0xbc, 0x82, 0xce, 0xc2, 0xd1, 0x06, 0xc7, 0xd0, 0x93, 0x47, 0x9d, 0x3d, - 0x08, 0x9a, 0xca, 0x5b, 0xd0, 0x8c, 0x95, 0x74, 0xc3, 0x96, 0x78, 0xcc, 0x73, 0x0b, 0x97, 0x3e, - 0x4a, 0xd9, 0x2c, 0x3c, 0x42, 0xf8, 0x66, 0x01, 0x58, 0x56, 0xb5, 0xcb, 0x15, 0xef, 0x05, 0x75 - }, - { 0xee, 0xc9, 0x6b, 0xcd, 0x43, 0xb8, 0xe2, 0x52, 0x47, 0xda, 0xca, 0x7f, 0x29, 0xa0, 0x01, 0xe0, - 0x44, 0x55, 0x22, 0x97, 0x65, 0x09, 0x82, 0xad, 0x4c, 0xd2, 0xf7, 0xf2, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - }, - }; - - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h deleted file mode 100644 index 79d8f125dd..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h +++ /dev/null @@ -1,5 +0,0 @@ -extern const unsigned char aes128_ecb_encrypt_key[][16]; -extern const unsigned char aes128_ecb_encrypt_input[][4096]; -extern const unsigned char aes128_ecb_encrypt_ref_output[][4096]; -extern unsigned char aes128_ecb_encrypt_output[][4096]; - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h deleted file mode 100644 index 706bb8d62e..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h +++ /dev/null @@ -1,26 +0,0 @@ -//----------------------------------------------------------------------------- -// The confidential and proprietary information contained in this file may -// only be used by a person authorised under and to the extent permitted -// by a subsisting licensing agreement from ARM Limited. -// -// (C) COPYRIGHT 2012-2013 ARM Limited. -// ALL RIGHTS RESERVED -// -// This entire notice must be reproduced on all copies of this file -// and copies of this file may only be made by a person if such person is -// permitted to do so under the terms of a subsisting license agreement -// from ARM Limited. -// -// SVN Information -// -// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $ -// -// Revision : $Revision: 241584 $ -// -// Release Information : -// -//----------------------------------------------------------------------------- - -extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out); -extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size); - diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s deleted file mode 100644 index 0cf39040cf..0000000000 --- a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s +++ /dev/null @@ -1,138 +0,0 @@ -;#----------------------------------------------------------------------------- -;# The confidential and proprietary information contained in this file may -;# only be used by a person authorised under and to the extent permitted -;# by a subsisting licensing agreement from ARM Limited. -;# -;# (C) COPYRIGHT 2012-2013 ARM Limited. -;# ALL RIGHTS RESERVED -;# -;# This entire notice must be reproduced on all copies of this file -;# and copies of this file may only be made by a person if such person is -;# permitted to do so under the terms of a subsisting license agreement -;# from ARM Limited. -;# -;# SVN Information -;# -;# Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $ -;# -;# Revision : $Revision: 241584 $ -;# -;# Release Information : -;# -;#----------------------------------------------------------------------------- - - .section aes_code, "ax" - - .global aes128_key_expand - .global aes128_ecb_encrypt - - .align 6 -rcon_array: - .word 0x00000001 - .word 0x00000002 - .word 0x00000004 - .word 0x00000008 - .word 0x00000010 - .word 0x00000020 - .word 0x00000040 - .word 0x00000080 - .word 0x0000001b - .word 0x00000036 - - .align 6 -;# void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out) - .type aes128_key_expand STT_FUNC -aes128_key_expand: - LD1 {v16.16B}, [x0] - MOVZ w2, #0x0e0d - DUP v17.16B, wzr - MOVK w2, #0x0c0f, lsl #16 - DUP v19.4S, w2 - ADR x3, rcon_array - MOV w4, #10 -exp: - TBL v18.16B, {v16.16B}, v19.16B - LD1R {v21.4S}, [x3], #4 - AESE v18.16B, v17.16B - EXT v20.16B, v17.16B, v16.16B, #12 - SHA1SU0 v21.4S, v18.4S, v17.4S - EOR v22.16B, v16.16B, v20.16B - ST1 {v16.16B}, [x1], #16 - SHA1SU0 v21.4S, v22.4S, v22.4S - - TBL v18.16B, {v21.16B}, v19.16B - LD1R {v16.4S}, [x3], #4 - AESE v18.16B, v17.16B - EXT v20.16B, v17.16B, v21.16B, #12 - SHA1SU0 v16.4S, v18.4S, v17.4S - EOR v22.16B, v21.16B, v20.16B - ST1 {v21.16B}, [x1], #16 - SUBS w4, w4, #2 - SHA1SU0 v16.4S, v22.4S, v22.4S - - B.NE exp - ST1 {v16.16B}, [x1] - RET - - .macro aes_enc_round keyreg - AESE v0.16B, \keyreg - AESMC v0.16B, v0.16B - AESE v1.16B, \keyreg - AESMC v1.16B, v1.16B - AESE v2.16B, \keyreg - AESMC v2.16B, v2.16B - .endm - - .macro aes_dec_round keyreg - AESD v0.16B, \keyreg - AESIMC v0.16B, v0.16B - AESD v1.16B, \keyreg - AESIMC v1.16B, v1.16B - AESD v2.16B, \keyreg - AESIMC v2.16B, v2.16B - .endm - -;# void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size) - .type aes128_ecb_encrypt STT_FUNC -aes128_ecb_encrypt: - ;# Load the key - LD1 {v16.16B-v19.16B}, [x0], #64 - LD1 {v20.16B-v23.16B}, [x0], #64 - LD1 {v24.16B-v26.16B}, [x0] - -load_ip: - ;# Load data - LD1 {v0.16B-v2.16B}, [x1], #48 - ;# Rounds 1-9 - aes_enc_round v16.16B - aes_enc_round v17.16B - aes_enc_round v18.16B - aes_enc_round v19.16B - aes_enc_round v20.16B - aes_enc_round v21.16B - aes_enc_round v22.16B - aes_enc_round v23.16B - aes_enc_round v24.16B - ;# Round 10 - AESE v0.16B, v25.16B - PRFM PLDL1KEEP, [x1, #64] - EOR v0.16B, v0.16B, v26.16B - SUBS x3, x3, #16 - ST1 {v0.16B}, [x2], #16 - B.EQ end_enc - - AESE v1.16B, v25.16B - EOR v1.16B, v1.16B, v26.16B - SUBS x3, x3, #16 - ST1 {v1.16B}, [x2], #16 - B.EQ end_enc - - AESE v2.16B, v25.16B - EOR v2.16B, v2.16B, v26.16B - SUBS x3, x3, #16 - ST1 {v2.16B}, [x2], #16 - B.GT load_ip -end_enc: - RET - - .end diff --git a/include/uapi/linux/loadpin.h b/include/uapi/linux/loadpin.h new file mode 100644 index 0000000000..daa6dbb8bb --- /dev/null +++ b/include/uapi/linux/loadpin.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (c) 2022, Google LLC + */ + +#ifndef _UAPI_LINUX_LOOP_LOADPIN_H +#define _UAPI_LINUX_LOOP_LOADPIN_H + +#define LOADPIN_IOC_MAGIC 'L' + +/** + * LOADPIN_IOC_SET_TRUSTED_VERITY_DIGESTS - Set up the root digests of verity devices + * that loadpin should trust. + * + * Takes a file descriptor from which to read the root digests of trusted verity devices. The file + * is expected to contain a list of digests in ASCII format, with one line per digest. The ioctl + * must be issued on the securityfs attribute 'loadpin/dm-verity' (which can be typically found + * under /sys/kernel/security/loadpin/dm-verity). + */ +#define LOADPIN_IOC_SET_TRUSTED_VERITY_DIGESTS _IOW(LOADPIN_IOC_MAGIC, 0x00, unsigned int) + +#endif /* _UAPI_LINUX_LOOP_LOADPIN_H */ diff --git a/include/uapi/linux/sev-guest.h b/include/uapi/linux/sev-guest.h new file mode 100644 index 0000000000..256aaeff7e --- /dev/null +++ b/include/uapi/linux/sev-guest.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Userspace interface for AMD SEV and SNP guest driver. + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + * SEV API specification is available at: https://developer.amd.com/sev/ + */ + +#ifndef __UAPI_LINUX_SEV_GUEST_H_ +#define __UAPI_LINUX_SEV_GUEST_H_ + +#include + +struct snp_report_req { + /* user data that should be included in the report */ + __u8 user_data[64]; + + /* The vmpl level to be included in the report */ + __u32 vmpl; + + /* Must be zero filled */ + __u8 rsvd[28]; +}; + +struct snp_report_resp { + /* response data, see SEV-SNP spec for the format */ + __u8 data[4000]; +}; + +struct snp_derived_key_req { + __u32 root_key_select; + __u32 rsvd; + __u64 guest_field_select; + __u32 vmpl; + __u32 guest_svn; + __u64 tcb_version; +}; + +struct snp_derived_key_resp { + /* response data, see SEV-SNP spec for the format */ + __u8 data[64]; +}; + +struct snp_guest_request_ioctl { + /* message version number (must be non-zero) */ + __u8 msg_version; + + /* Request and response structure address */ + __u64 req_data; + __u64 resp_data; + + /* firmware error code on failure (see psp-sev.h) */ + __u64 fw_err; +}; + +struct snp_ext_report_req { + struct snp_report_req data; + + /* where to copy the certificate blob */ + __u64 certs_address; + + /* length of the certificate blob */ + __u32 certs_len; +}; + +#define SNP_GUEST_REQ_IOC_TYPE 'S' + +/* Get SNP attestation report */ +#define SNP_GET_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x0, struct snp_guest_request_ioctl) + +/* Get a derived key from the root */ +#define SNP_GET_DERIVED_KEY _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x1, struct snp_guest_request_ioctl) + +/* Get SNP extended report as defined in the GHCB specification version 2. */ +#define SNP_GET_EXT_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x2, struct snp_guest_request_ioctl) + +#endif /* __UAPI_LINUX_SEV_GUEST_H_ */ diff --git a/include/uapi/linux/ublk_cmd.h b/include/uapi/linux/ublk_cmd.h new file mode 100644 index 0000000000..677edaab2b --- /dev/null +++ b/include/uapi/linux/ublk_cmd.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef USER_BLK_DRV_CMD_INC_H +#define USER_BLK_DRV_CMD_INC_H + +#include + +/* ublk server command definition */ + +/* + * Admin commands, issued by ublk server, and handled by ublk driver. + */ +#define UBLK_CMD_GET_QUEUE_AFFINITY 0x01 +#define UBLK_CMD_GET_DEV_INFO 0x02 +#define UBLK_CMD_ADD_DEV 0x04 +#define UBLK_CMD_DEL_DEV 0x05 +#define UBLK_CMD_START_DEV 0x06 +#define UBLK_CMD_STOP_DEV 0x07 +#define UBLK_CMD_SET_PARAMS 0x08 +#define UBLK_CMD_GET_PARAMS 0x09 + +/* + * IO commands, issued by ublk server, and handled by ublk driver. + * + * FETCH_REQ: issued via sqe(URING_CMD) beforehand for fetching IO request + * from ublk driver, should be issued only when starting device. After + * the associated cqe is returned, request's tag can be retrieved via + * cqe->userdata. + * + * COMMIT_AND_FETCH_REQ: issued via sqe(URING_CMD) after ublkserver handled + * this IO request, request's handling result is committed to ublk + * driver, meantime FETCH_REQ is piggyback, and FETCH_REQ has to be + * handled before completing io request. + * + * NEED_GET_DATA: only used for write requests to set io addr and copy data + * When NEED_GET_DATA is set, ublksrv has to issue UBLK_IO_NEED_GET_DATA + * command after ublk driver returns UBLK_IO_RES_NEED_GET_DATA. + * + * It is only used if ublksrv set UBLK_F_NEED_GET_DATA flag + * while starting a ublk device. + */ +#define UBLK_IO_FETCH_REQ 0x20 +#define UBLK_IO_COMMIT_AND_FETCH_REQ 0x21 +#define UBLK_IO_NEED_GET_DATA 0x22 + +/* only ABORT means that no re-fetch */ +#define UBLK_IO_RES_OK 0 +#define UBLK_IO_RES_NEED_GET_DATA 1 +#define UBLK_IO_RES_ABORT (-ENODEV) + +#define UBLKSRV_CMD_BUF_OFFSET 0 +#define UBLKSRV_IO_BUF_OFFSET 0x80000000 + +/* tag bit is 12bit, so at most 4096 IOs for each queue */ +#define UBLK_MAX_QUEUE_DEPTH 4096 + +/* + * zero copy requires 4k block size, and can remap ublk driver's io + * request into ublksrv's vm space + */ +#define UBLK_F_SUPPORT_ZERO_COPY (1ULL << 0) + +/* + * Force to complete io cmd via io_uring_cmd_complete_in_task so that + * performance comparison is done easily with using task_work_add + */ +#define UBLK_F_URING_CMD_COMP_IN_TASK (1ULL << 1) + +/* + * User should issue io cmd again for write requests to + * set io buffer address and copy data from bio vectors + * to the userspace io buffer. + * + * In this mode, task_work is not used. + */ +#define UBLK_F_NEED_GET_DATA (1UL << 2) + +/* device state */ +#define UBLK_S_DEV_DEAD 0 +#define UBLK_S_DEV_LIVE 1 + +/* shipped via sqe->cmd of io_uring command */ +struct ublksrv_ctrl_cmd { + /* sent to which device, must be valid */ + __u32 dev_id; + + /* sent to which queue, must be -1 if the cmd isn't for queue */ + __u16 queue_id; + /* + * cmd specific buffer, can be IN or OUT. + */ + __u16 len; + __u64 addr; + + /* inline data */ + __u64 data[2]; +}; + +struct ublksrv_ctrl_dev_info { + __u16 nr_hw_queues; + __u16 queue_depth; + __u16 state; + __u16 pad0; + + __u32 max_io_buf_bytes; + __u32 dev_id; + + __s32 ublksrv_pid; + __u32 pad1; + + __u64 flags; + + /* For ublksrv internal use, invisible to ublk driver */ + __u64 ublksrv_flags; + + __u64 reserved0; + __u64 reserved1; + __u64 reserved2; +}; + +#define UBLK_IO_OP_READ 0 +#define UBLK_IO_OP_WRITE 1 +#define UBLK_IO_OP_FLUSH 2 +#define UBLK_IO_OP_DISCARD 3 +#define UBLK_IO_OP_WRITE_SAME 4 +#define UBLK_IO_OP_WRITE_ZEROES 5 + +#define UBLK_IO_F_FAILFAST_DEV (1U << 8) +#define UBLK_IO_F_FAILFAST_TRANSPORT (1U << 9) +#define UBLK_IO_F_FAILFAST_DRIVER (1U << 10) +#define UBLK_IO_F_META (1U << 11) +#define UBLK_IO_F_FUA (1U << 13) +#define UBLK_IO_F_NOUNMAP (1U << 15) +#define UBLK_IO_F_SWAP (1U << 16) + +/* + * io cmd is described by this structure, and stored in share memory, indexed + * by request tag. + * + * The data is stored by ublk driver, and read by ublksrv after one fetch command + * returns. + */ +struct ublksrv_io_desc { + /* op: bit 0-7, flags: bit 8-31 */ + __u32 op_flags; + + __u32 nr_sectors; + + /* start sector for this io */ + __u64 start_sector; + + /* buffer address in ublksrv daemon vm space, from ublk driver */ + __u64 addr; +}; + +static inline __u8 ublksrv_get_op(const struct ublksrv_io_desc *iod) +{ + return iod->op_flags & 0xff; +} + +static inline __u32 ublksrv_get_flags(const struct ublksrv_io_desc *iod) +{ + return iod->op_flags >> 8; +} + +/* issued to ublk driver via /dev/ublkcN */ +struct ublksrv_io_cmd { + __u16 q_id; + + /* for fetch/commit which result */ + __u16 tag; + + /* io result, it is valid for COMMIT* command only */ + __s32 result; + + /* + * userspace buffer address in ublksrv daemon process, valid for + * FETCH* command only + */ + __u64 addr; +}; + +struct ublk_param_basic { +#define UBLK_ATTR_READ_ONLY (1 << 0) +#define UBLK_ATTR_ROTATIONAL (1 << 1) +#define UBLK_ATTR_VOLATILE_CACHE (1 << 2) +#define UBLK_ATTR_FUA (1 << 3) + __u32 attrs; + __u8 logical_bs_shift; + __u8 physical_bs_shift; + __u8 io_opt_shift; + __u8 io_min_shift; + + __u32 max_sectors; + __u32 chunk_sectors; + + __u64 dev_sectors; + __u64 virt_boundary_mask; +}; + +struct ublk_param_discard { + __u32 discard_alignment; + + __u32 discard_granularity; + __u32 max_discard_sectors; + + __u32 max_write_zeroes_sectors; + __u16 max_discard_segments; + __u16 reserved0; +}; + +struct ublk_params { + /* + * Total length of parameters, userspace has to set 'len' for both + * SET_PARAMS and GET_PARAMS command, and driver may update len + * if two sides use different version of 'ublk_params', same with + * 'types' fields. + */ + __u32 len; +#define UBLK_PARAM_TYPE_BASIC (1 << 0) +#define UBLK_PARAM_TYPE_DISCARD (1 << 1) + __u32 types; /* types of parameter included */ + + struct ublk_param_basic basic; + struct ublk_param_discard discard; +}; + +#endif diff --git a/include/uapi/rdma/erdma-abi.h b/include/uapi/rdma/erdma-abi.h new file mode 100644 index 0000000000..b7a0222f97 --- /dev/null +++ b/include/uapi/rdma/erdma-abi.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * Copyright (c) 2020-2022, Alibaba Group. + */ + +#ifndef __ERDMA_USER_H__ +#define __ERDMA_USER_H__ + +#include + +#define ERDMA_ABI_VERSION 1 + +struct erdma_ureq_create_cq { + __aligned_u64 db_record_va; + __aligned_u64 qbuf_va; + __u32 qbuf_len; + __u32 rsvd0; +}; + +struct erdma_uresp_create_cq { + __u32 cq_id; + __u32 num_cqe; +}; + +struct erdma_ureq_create_qp { + __aligned_u64 db_record_va; + __aligned_u64 qbuf_va; + __u32 qbuf_len; + __u32 rsvd0; +}; + +struct erdma_uresp_create_qp { + __u32 qp_id; + __u32 num_sqe; + __u32 num_rqe; + __u32 rq_offset; +}; + +struct erdma_uresp_alloc_ctx { + __u32 dev_id; + __u32 pad; + __u32 sdb_type; + __u32 sdb_offset; + __aligned_u64 sdb; + __aligned_u64 rdb; + __aligned_u64 cdb; +}; + +#endif diff --git a/include/uapi/scsi/scsi_bsg_mpi3mr.h b/include/uapi/scsi/scsi_bsg_mpi3mr.h new file mode 100644 index 0000000000..fdc3517f9e --- /dev/null +++ b/include/uapi/scsi/scsi_bsg_mpi3mr.h @@ -0,0 +1,582 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH Linux-syscall-note */ +/* + * Driver for Broadcom MPI3 Storage Controllers + * + * Copyright (C) 2017-2022 Broadcom Inc. + * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) + * + */ + +#ifndef SCSI_BSG_MPI3MR_H_INCLUDED +#define SCSI_BSG_MPI3MR_H_INCLUDED + +#include + +/* Definitions for BSG commands */ +#define MPI3MR_IOCTL_VERSION 0x06 + +#define MPI3MR_APP_DEFAULT_TIMEOUT (60) /*seconds*/ + +#define MPI3MR_BSG_ADPTYPE_UNKNOWN 0 +#define MPI3MR_BSG_ADPTYPE_AVGFAMILY 1 + +#define MPI3MR_BSG_ADPSTATE_UNKNOWN 0 +#define MPI3MR_BSG_ADPSTATE_OPERATIONAL 1 +#define MPI3MR_BSG_ADPSTATE_FAULT 2 +#define MPI3MR_BSG_ADPSTATE_IN_RESET 3 +#define MPI3MR_BSG_ADPSTATE_UNRECOVERABLE 4 + +#define MPI3MR_BSG_ADPRESET_UNKNOWN 0 +#define MPI3MR_BSG_ADPRESET_SOFT 1 +#define MPI3MR_BSG_ADPRESET_DIAG_FAULT 2 + +#define MPI3MR_BSG_LOGDATA_MAX_ENTRIES 400 +#define MPI3MR_BSG_LOGDATA_ENTRY_HEADER_SZ 4 + +#define MPI3MR_DRVBSG_OPCODE_UNKNOWN 0 +#define MPI3MR_DRVBSG_OPCODE_ADPINFO 1 +#define MPI3MR_DRVBSG_OPCODE_ADPRESET 2 +#define MPI3MR_DRVBSG_OPCODE_ALLTGTDEVINFO 4 +#define MPI3MR_DRVBSG_OPCODE_GETCHGCNT 5 +#define MPI3MR_DRVBSG_OPCODE_LOGDATAENABLE 6 +#define MPI3MR_DRVBSG_OPCODE_PELENABLE 7 +#define MPI3MR_DRVBSG_OPCODE_GETLOGDATA 8 +#define MPI3MR_DRVBSG_OPCODE_QUERY_HDB 9 +#define MPI3MR_DRVBSG_OPCODE_REPOST_HDB 10 +#define MPI3MR_DRVBSG_OPCODE_UPLOAD_HDB 11 +#define MPI3MR_DRVBSG_OPCODE_REFRESH_HDB_TRIGGERS 12 + + +#define MPI3MR_BSG_BUFTYPE_UNKNOWN 0 +#define MPI3MR_BSG_BUFTYPE_RAIDMGMT_CMD 1 +#define MPI3MR_BSG_BUFTYPE_RAIDMGMT_RESP 2 +#define MPI3MR_BSG_BUFTYPE_DATA_IN 3 +#define MPI3MR_BSG_BUFTYPE_DATA_OUT 4 +#define MPI3MR_BSG_BUFTYPE_MPI_REPLY 5 +#define MPI3MR_BSG_BUFTYPE_ERR_RESPONSE 6 +#define MPI3MR_BSG_BUFTYPE_MPI_REQUEST 0xFE + +#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_UNKNOWN 0 +#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_STATUS 1 +#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_ADDRESS 2 + +#define MPI3MR_HDB_BUFTYPE_UNKNOWN 0 +#define MPI3MR_HDB_BUFTYPE_TRACE 1 +#define MPI3MR_HDB_BUFTYPE_FIRMWARE 2 +#define MPI3MR_HDB_BUFTYPE_RESERVED 3 + +#define MPI3MR_HDB_BUFSTATUS_UNKNOWN 0 +#define MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED 1 +#define MPI3MR_HDB_BUFSTATUS_POSTED_UNPAUSED 2 +#define MPI3MR_HDB_BUFSTATUS_POSTED_PAUSED 3 +#define MPI3MR_HDB_BUFSTATUS_RELEASED 4 + +#define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0 +#define MPI3MR_HDB_TRIGGER_TYPE_DIAGFAULT 1 +#define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2 +#define MPI3MR_HDB_TRIGGER_TYPE_MASTER 3 + + +/* Supported BSG commands */ +enum command { + MPI3MR_DRV_CMD = 1, + MPI3MR_MPT_CMD = 2, +}; + +/** + * struct mpi3_driver_info_layout - Information about driver + * + * @information_length: Length of this structure in bytes + * @driver_signature: Driver Vendor name + * @os_name: Operating System Name + * @driver_name: Driver name + * @driver_version: Driver version + * @driver_release_date: Driver release date + * @driver_capabilities: Driver capabilities + */ +struct mpi3_driver_info_layout { + __le32 information_length; + __u8 driver_signature[12]; + __u8 os_name[16]; + __u8 os_version[12]; + __u8 driver_name[20]; + __u8 driver_version[32]; + __u8 driver_release_date[20]; + __le32 driver_capabilities; +}; + +/** + * struct mpi3mr_bsg_in_adpinfo - Adapter information request + * data returned by the driver. + * + * @adp_type: Adapter type + * @rsvd1: Reserved + * @pci_dev_id: PCI device ID of the adapter + * @pci_dev_hw_rev: PCI revision of the adapter + * @pci_subsys_dev_id: PCI subsystem device ID of the adapter + * @pci_subsys_ven_id: PCI subsystem vendor ID of the adapter + * @pci_dev: PCI device + * @pci_func: PCI function + * @pci_bus: PCI bus + * @rsvd2: Reserved + * @pci_seg_id: PCI segment ID + * @app_intfc_ver: version of the application interface definition + * @rsvd3: Reserved + * @rsvd4: Reserved + * @rsvd5: Reserved + * @driver_info: Driver Information (Version/Name) + */ +struct mpi3mr_bsg_in_adpinfo { + __u32 adp_type; + __u32 rsvd1; + __u32 pci_dev_id; + __u32 pci_dev_hw_rev; + __u32 pci_subsys_dev_id; + __u32 pci_subsys_ven_id; + __u32 pci_dev:5; + __u32 pci_func:3; + __u32 pci_bus:8; + __u16 rsvd2; + __u32 pci_seg_id; + __u32 app_intfc_ver; + __u8 adp_state; + __u8 rsvd3; + __u16 rsvd4; + __u32 rsvd5[2]; + struct mpi3_driver_info_layout driver_info; +}; + +/** + * struct mpi3mr_bsg_adp_reset - Adapter reset request + * payload data to the driver. + * + * @reset_type: Reset type + * @rsvd1: Reserved + * @rsvd2: Reserved + */ +struct mpi3mr_bsg_adp_reset { + __u8 reset_type; + __u8 rsvd1; + __u16 rsvd2; +}; + +/** + * struct mpi3mr_change_count - Topology change count + * returned by the driver. + * + * @change_count: Topology change count + * @rsvd: Reserved + */ +struct mpi3mr_change_count { + __u16 change_count; + __u16 rsvd; +}; + +/** + * struct mpi3mr_device_map_info - Target device mapping + * information + * + * @handle: Firmware device handle + * @perst_id: Persistent ID assigned by the firmware + * @target_id: Target ID assigned by the driver + * @bus_id: Bus ID assigned by the driver + * @rsvd1: Reserved + * @rsvd2: Reserved + */ +struct mpi3mr_device_map_info { + __u16 handle; + __u16 perst_id; + __u32 target_id; + __u8 bus_id; + __u8 rsvd1; + __u16 rsvd2; +}; + +/** + * struct mpi3mr_all_tgt_info - Target device mapping + * information returned by the driver + * + * @num_devices: The number of devices in driver's inventory + * @rsvd1: Reserved + * @rsvd2: Reserved + * @dmi: Variable length array of mapping information of targets + */ +struct mpi3mr_all_tgt_info { + __u16 num_devices; + __u16 rsvd1; + __u32 rsvd2; + struct mpi3mr_device_map_info dmi[1]; +}; + +/** + * struct mpi3mr_logdata_enable - Number of log data + * entries saved by the driver returned as payload data for + * enable logdata BSG request by the driver. + * + * @max_entries: Number of log data entries cached by the driver + * @rsvd: Reserved + */ +struct mpi3mr_logdata_enable { + __u16 max_entries; + __u16 rsvd; +}; + +/** + * struct mpi3mr_bsg_out_pel_enable - PEL enable request payload + * data to the driver. + * + * @pel_locale: PEL locale to the firmware + * @pel_class: PEL class to the firmware + * @rsvd: Reserved + */ +struct mpi3mr_bsg_out_pel_enable { + __u16 pel_locale; + __u8 pel_class; + __u8 rsvd; +}; + +/** + * struct mpi3mr_logdata_entry - Log data entry cached by the + * driver. + * + * @valid_entry: Is the entry valid + * @rsvd1: Reserved + * @rsvd2: Reserved + * @data: Variable length Log entry data + */ +struct mpi3mr_logdata_entry { + __u8 valid_entry; + __u8 rsvd1; + __u16 rsvd2; + __u8 data[1]; /* Variable length Array */ +}; + +/** + * struct mpi3mr_bsg_in_log_data - Log data entries saved by + * the driver returned as payload data for Get logdata request + * by the driver. + * + * @entry: Variable length Log data entry array + */ +struct mpi3mr_bsg_in_log_data { + struct mpi3mr_logdata_entry entry[1]; +}; + +/** + * struct mpi3mr_hdb_entry - host diag buffer entry. + * + * @buf_type: Buffer type + * @status: Buffer status + * @trigger_type: Trigger type + * @rsvd1: Reserved + * @size: Buffer size + * @rsvd2: Reserved + * @trigger_data: Trigger specific data + * @rsvd3: Reserved + * @rsvd4: Reserved + */ +struct mpi3mr_hdb_entry { + __u8 buf_type; + __u8 status; + __u8 trigger_type; + __u8 rsvd1; + __u16 size; + __u16 rsvd2; + __u64 trigger_data; + __u32 rsvd3; + __u32 rsvd4; +}; + + +/** + * struct mpi3mr_bsg_in_hdb_status - This structure contains + * return data for the BSG request to retrieve the number of host + * diagnostic buffers supported by the driver and their current + * status and additional status specific data if any in forms of + * multiple hdb entries. + * + * @num_hdb_types: Number of host diag buffer types supported + * @rsvd1: Reserved + * @rsvd2: Reserved + * @rsvd3: Reserved + * @entry: Variable length Diag buffer status entry array + */ +struct mpi3mr_bsg_in_hdb_status { + __u8 num_hdb_types; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; + struct mpi3mr_hdb_entry entry[1]; +}; + +/** + * struct mpi3mr_bsg_out_repost_hdb - Repost host diagnostic + * buffer request payload data to the driver. + * + * @buf_type: Buffer type + * @rsvd1: Reserved + * @rsvd2: Reserved + */ +struct mpi3mr_bsg_out_repost_hdb { + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; +}; + +/** + * struct mpi3mr_bsg_out_upload_hdb - Upload host diagnostic + * buffer request payload data to the driver. + * + * @buf_type: Buffer type + * @rsvd1: Reserved + * @rsvd2: Reserved + * @start_offset: Start offset of the buffer from where to copy + * @length: Length of the buffer to copy + */ +struct mpi3mr_bsg_out_upload_hdb { + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 start_offset; + __u32 length; +}; + +/** + * struct mpi3mr_bsg_out_refresh_hdb_triggers - Refresh host + * diagnostic buffer triggers request payload data to the driver. + * + * @page_type: Page type + * @rsvd1: Reserved + * @rsvd2: Reserved + */ +struct mpi3mr_bsg_out_refresh_hdb_triggers { + __u8 page_type; + __u8 rsvd1; + __u16 rsvd2; +}; +/** + * struct mpi3mr_bsg_drv_cmd - Generic bsg data + * structure for all driver specific requests. + * + * @mrioc_id: Controller ID + * @opcode: Driver specific opcode + * @rsvd1: Reserved + * @rsvd2: Reserved + */ +struct mpi3mr_bsg_drv_cmd { + __u8 mrioc_id; + __u8 opcode; + __u16 rsvd1; + __u32 rsvd2[4]; +}; +/** + * struct mpi3mr_bsg_in_reply_buf - MPI reply buffer returned + * for MPI Passthrough request . + * + * @mpi_reply_type: Type of MPI reply + * @rsvd1: Reserved + * @rsvd2: Reserved + * @reply_buf: Variable Length buffer based on mpirep type + */ +struct mpi3mr_bsg_in_reply_buf { + __u8 mpi_reply_type; + __u8 rsvd1; + __u16 rsvd2; + __u8 reply_buf[1]; +}; + +/** + * struct mpi3mr_buf_entry - User buffer descriptor for MPI + * Passthrough requests. + * + * @buf_type: Buffer type + * @rsvd1: Reserved + * @rsvd2: Reserved + * @buf_len: Buffer length + */ +struct mpi3mr_buf_entry { + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 buf_len; +}; +/** + * struct mpi3mr_bsg_buf_entry_list - list of user buffer + * descriptor for MPI Passthrough requests. + * + * @num_of_entries: Number of buffer descriptors + * @rsvd1: Reserved + * @rsvd2: Reserved + * @rsvd3: Reserved + * @buf_entry: Variable length array of buffer descriptors + */ +struct mpi3mr_buf_entry_list { + __u8 num_of_entries; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; + struct mpi3mr_buf_entry buf_entry[1]; +}; +/** + * struct mpi3mr_bsg_mptcmd - Generic bsg data + * structure for all MPI Passthrough requests . + * + * @mrioc_id: Controller ID + * @rsvd1: Reserved + * @timeout: MPI request timeout + * @buf_entry_list: Buffer descriptor list + */ +struct mpi3mr_bsg_mptcmd { + __u8 mrioc_id; + __u8 rsvd1; + __u16 timeout; + __u32 rsvd2; + struct mpi3mr_buf_entry_list buf_entry_list; +}; + +/** + * struct mpi3mr_bsg_packet - Generic bsg data + * structure for all supported requests . + * + * @cmd_type: represents drvrcmd or mptcmd + * @rsvd1: Reserved + * @rsvd2: Reserved + * @drvrcmd: driver request structure + * @mptcmd: mpt request structure + */ +struct mpi3mr_bsg_packet { + __u8 cmd_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; + union { + struct mpi3mr_bsg_drv_cmd drvrcmd; + struct mpi3mr_bsg_mptcmd mptcmd; + } cmd; +}; + + +/* MPI3: NVMe Encasulation related definitions */ +#ifndef MPI3_NVME_ENCAP_CMD_MAX +#define MPI3_NVME_ENCAP_CMD_MAX (1) +#endif + +struct mpi3_nvme_encapsulated_request { + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 change_count; + __le16 dev_handle; + __le16 encapsulated_command_length; + __le16 flags; + __le32 data_length; + __le32 reserved14[3]; + __le32 command[MPI3_NVME_ENCAP_CMD_MAX]; +}; + +struct mpi3_nvme_encapsulated_error_reply { + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 ioc_use_only08; + __le16 ioc_status; + __le32 ioc_log_info; + __le32 nvme_completion_entry[4]; +}; + +#define MPI3MR_NVME_PRP_SIZE 8 /* PRP size */ +#define MPI3MR_NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */ +#define MPI3MR_NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */ +#define MPI3MR_NVME_CMD_SGL_OFFSET 24 /* SGL offset in NVMe cmd */ +#define MPI3MR_NVME_DATA_FORMAT_PRP 0 +#define MPI3MR_NVME_DATA_FORMAT_SGL1 1 +#define MPI3MR_NVME_DATA_FORMAT_SGL2 2 + +/* MPI3: task management related definitions */ +struct mpi3_scsi_task_mgmt_request { + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 change_count; + __le16 dev_handle; + __le16 task_host_tag; + __u8 task_type; + __u8 reserved0f; + __le16 task_request_queue_id; + __le16 reserved12; + __le32 reserved14; + __u8 lun[8]; +}; + +#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08) +#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) +#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02) +#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) +#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) +#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) +#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) +#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08) +#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09) +#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a) +#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b) +struct mpi3_scsi_task_mgmt_reply { + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 ioc_use_only08; + __le16 ioc_status; + __le32 ioc_log_info; + __le32 termination_count; + __le32 response_data; + __le32 reserved18; +}; + +#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00) +#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a) +#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80) +#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81) + +/* MPI3: PEL related definitions */ +#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) +#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) +#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) +#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) +#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) +#define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) +#define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) +#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) +#define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) +#define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) +#define MPI3_PEL_CLASS_DEBUG (0x00) +#define MPI3_PEL_CLASS_PROGRESS (0x01) +#define MPI3_PEL_CLASS_INFORMATIONAL (0x02) +#define MPI3_PEL_CLASS_WARNING (0x03) +#define MPI3_PEL_CLASS_CRITICAL (0x04) +#define MPI3_PEL_CLASS_FATAL (0x05) +#define MPI3_PEL_CLASS_FAULT (0x06) + +/* MPI3: Function definitions */ +#define MPI3_BSG_FUNCTION_MGMT_PASSTHROUGH (0x0a) +#define MPI3_BSG_FUNCTION_SCSI_IO (0x20) +#define MPI3_BSG_FUNCTION_SCSI_TASK_MGMT (0x21) +#define MPI3_BSG_FUNCTION_SMP_PASSTHROUGH (0x22) +#define MPI3_BSG_FUNCTION_NVME_ENCAPSULATED (0x24) + +#endif diff --git a/include/uapi/sound/intel/avs/tokens.h b/include/uapi/sound/intel/avs/tokens.h new file mode 100644 index 0000000000..754f02b2f4 --- /dev/null +++ b/include/uapi/sound/intel/avs/tokens.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright(c) 2021 Intel Corporation. All rights reserved. + * + * Authors: Cezary Rojewski + * Amadeusz Slawinski + */ + +#ifndef __UAPI_SOUND_INTEL_AVS_TOKENS_H +#define __UAPI_SOUND_INTEL_AVS_TOKENS_H + +enum avs_tplg_token { + /* struct avs_tplg */ + AVS_TKN_MANIFEST_NAME_STRING = 1, + AVS_TKN_MANIFEST_VERSION_U32 = 2, + AVS_TKN_MANIFEST_NUM_LIBRARIES_U32 = 3, + AVS_TKN_MANIFEST_NUM_AFMTS_U32 = 4, + AVS_TKN_MANIFEST_NUM_MODCFGS_BASE_U32 = 5, + AVS_TKN_MANIFEST_NUM_MODCFGS_EXT_U32 = 6, + AVS_TKN_MANIFEST_NUM_PPLCFGS_U32 = 7, + AVS_TKN_MANIFEST_NUM_BINDINGS_U32 = 8, + + /* struct avs_tplg_library */ + AVS_TKN_LIBRARY_ID_U32 = 101, + AVS_TKN_LIBRARY_NAME_STRING = 102, + + /* struct avs_audio_format */ + AVS_TKN_AFMT_ID_U32 = 201, + AVS_TKN_AFMT_SAMPLE_RATE_U32 = 202, + AVS_TKN_AFMT_BIT_DEPTH_U32 = 203, + AVS_TKN_AFMT_CHANNEL_MAP_U32 = 204, + AVS_TKN_AFMT_CHANNEL_CFG_U32 = 205, + AVS_TKN_AFMT_INTERLEAVING_U32 = 206, + AVS_TKN_AFMT_NUM_CHANNELS_U32 = 207, + AVS_TKN_AFMT_VALID_BIT_DEPTH_U32 = 208, + AVS_TKN_AFMT_SAMPLE_TYPE_U32 = 209, + + /* struct avs_tplg_modcfg_base */ + AVS_TKN_MODCFG_BASE_ID_U32 = 301, + AVS_TKN_MODCFG_BASE_CPC_U32 = 302, + AVS_TKN_MODCFG_BASE_IBS_U32 = 303, + AVS_TKN_MODCFG_BASE_OBS_U32 = 304, + AVS_TKN_MODCFG_BASE_PAGES_U32 = 305, + + /* struct avs_tplg_modcfg_ext */ + AVS_TKN_MODCFG_EXT_ID_U32 = 401, + AVS_TKN_MODCFG_EXT_TYPE_UUID = 402, + AVS_TKN_MODCFG_CPR_OUT_AFMT_ID_U32 = 403, + AVS_TKN_MODCFG_CPR_FEATURE_MASK_U32 = 404, + AVS_TKN_MODCFG_CPR_DMA_TYPE_U32 = 405, + AVS_TKN_MODCFG_CPR_DMABUFF_SIZE_U32 = 406, + AVS_TKN_MODCFG_CPR_VINDEX_U8 = 407, + AVS_TKN_MODCFG_CPR_BLOB_FMT_ID_U32 = 408, + AVS_TKN_MODCFG_MICSEL_OUT_AFMT_ID_U32 = 409, + AVS_TKN_MODCFG_INTELWOV_CPC_LP_MODE_U32 = 410, + AVS_TKN_MODCFG_SRC_OUT_FREQ_U32 = 411, + AVS_TKN_MODCFG_MUX_REF_AFMT_ID_U32 = 412, + AVS_TKN_MODCFG_MUX_OUT_AFMT_ID_U32 = 413, + AVS_TKN_MODCFG_AEC_REF_AFMT_ID_U32 = 414, + AVS_TKN_MODCFG_AEC_OUT_AFMT_ID_U32 = 415, + AVS_TKN_MODCFG_AEC_CPC_LP_MODE_U32 = 416, + AVS_TKN_MODCFG_ASRC_OUT_FREQ_U32 = 417, + AVS_TKN_MODCFG_ASRC_MODE_U8 = 418, + AVS_TKN_MODCFG_ASRC_DISABLE_JITTER_U8 = 419, + AVS_TKN_MODCFG_UPDOWN_MIX_OUT_CHAN_CFG_U32 = 420, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_SELECT_U32 = 421, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_0_S32 = 422, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_1_S32 = 423, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_2_S32 = 424, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_3_S32 = 425, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_4_S32 = 426, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_5_S32 = 427, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_6_S32 = 428, + AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_7_S32 = 429, + AVS_TKN_MODCFG_UPDOWN_MIX_CHAN_MAP_U32 = 430, + AVS_TKN_MODCFG_EXT_NUM_INPUT_PINS_U16 = 431, + AVS_TKN_MODCFG_EXT_NUM_OUTPUT_PINS_U16 = 432, + + /* struct avs_tplg_pplcfg */ + AVS_TKN_PPLCFG_ID_U32 = 1401, + AVS_TKN_PPLCFG_REQ_SIZE_U16 = 1402, + AVS_TKN_PPLCFG_PRIORITY_U8 = 1403, + AVS_TKN_PPLCFG_LOW_POWER_BOOL = 1404, + AVS_TKN_PPLCFG_ATTRIBUTES_U16 = 1405, + AVS_TKN_PPLCFG_TRIGGER_U32 = 1406, + + /* struct avs_tplg_binding */ + AVS_TKN_BINDING_ID_U32 = 1501, + AVS_TKN_BINDING_TARGET_TPLG_NAME_STRING = 1502, + AVS_TKN_BINDING_TARGET_PATH_TMPL_ID_U32 = 1503, + AVS_TKN_BINDING_TARGET_PPL_ID_U32 = 1504, + AVS_TKN_BINDING_TARGET_MOD_ID_U32 = 1505, + AVS_TKN_BINDING_TARGET_MOD_PIN_U8 = 1506, + AVS_TKN_BINDING_MOD_ID_U32 = 1507, + AVS_TKN_BINDING_MOD_PIN_U8 = 1508, + AVS_TKN_BINDING_IS_SINK_U8 = 1509, + + /* struct avs_tplg_pipeline */ + AVS_TKN_PPL_ID_U32 = 1601, + AVS_TKN_PPL_PPLCFG_ID_U32 = 1602, + AVS_TKN_PPL_NUM_BINDING_IDS_U32 = 1603, + AVS_TKN_PPL_BINDING_ID_U32 = 1604, + + /* struct avs_tplg_module */ + AVS_TKN_MOD_ID_U32 = 1701, + AVS_TKN_MOD_MODCFG_BASE_ID_U32 = 1702, + AVS_TKN_MOD_IN_AFMT_ID_U32 = 1703, + AVS_TKN_MOD_CORE_ID_U8 = 1704, + AVS_TKN_MOD_PROC_DOMAIN_U8 = 1705, + AVS_TKN_MOD_MODCFG_EXT_ID_U32 = 1706, + + /* struct avs_tplg_path_template */ + AVS_TKN_PATH_TMPL_ID_U32 = 1801, + + /* struct avs_tplg_path */ + AVS_TKN_PATH_ID_U32 = 1901, + AVS_TKN_PATH_FE_FMT_ID_U32 = 1902, + AVS_TKN_PATH_BE_FMT_ID_U32 = 1903, + + /* struct avs_tplg_pin_format */ + AVS_TKN_PIN_FMT_INDEX_U32 = 2201, + AVS_TKN_PIN_FMT_IOBS_U32 = 2202, + AVS_TKN_PIN_FMT_AFMT_ID_U32 = 2203, +}; + +#endif diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h new file mode 100644 index 0000000000..1bba3fead2 --- /dev/null +++ b/include/ufs/ufs.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal Flash Storage Host controller driver + * Copyright (C) 2011-2013 Samsung India Software Operations + * + * Authors: + * Santosh Yaraganavi + * Vinayak Holikatti + */ + +#ifndef _UFS_H +#define _UFS_H + +#include +#include +#include + +#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) +#define QUERY_DESC_MAX_SIZE 255 +#define QUERY_DESC_MIN_SIZE 2 +#define QUERY_DESC_HDR_SIZE 2 +#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ + (sizeof(struct utp_upiu_header))) +#define UFS_SENSE_SIZE 18 + +#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ + cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ + (byte1 << 8) | (byte0)) +/* + * UFS device may have standard LUs and LUN id could be from 0x00 to + * 0x7F. Standard LUs use "Peripheral Device Addressing Format". + * UFS device may also have the Well Known LUs (also referred as W-LU) + * which again could be from 0x00 to 0x7F. For W-LUs, device only use + * the "Extended Addressing Format" which means the W-LUNs would be + * from 0xc100 (SCSI_W_LUN_BASE) onwards. + * This means max. LUN number reported from UFS device could be 0xC17F. + */ +#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F +#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID) +#define UFS_UPIU_WLUN_ID (1 << 7) +#define UFS_RPMB_UNIT 0xC4 + +/* WriteBooster buffer is available only for the logical unit from 0 to 7 */ +#define UFS_UPIU_MAX_WB_LUN_ID 8 + +/* + * WriteBooster buffer lifetime has a limit setted by vendor. + * If it is over the limit, WriteBooster feature will be disabled. + */ +#define UFS_WB_EXCEED_LIFETIME 0x0B + +/* Well known logical unit id in LUN field of UPIU */ +enum { + UFS_UPIU_REPORT_LUNS_WLUN = 0x81, + UFS_UPIU_UFS_DEVICE_WLUN = 0xD0, + UFS_UPIU_BOOT_WLUN = 0xB0, + UFS_UPIU_RPMB_WLUN = 0xC4, +}; + +/* + * UFS Protocol Information Unit related definitions + */ + +/* Task management functions */ +enum { + UFS_ABORT_TASK = 0x01, + UFS_ABORT_TASK_SET = 0x02, + UFS_CLEAR_TASK_SET = 0x04, + UFS_LOGICAL_RESET = 0x08, + UFS_QUERY_TASK = 0x80, + UFS_QUERY_TASK_SET = 0x81, +}; + +/* UTP UPIU Transaction Codes Initiator to Target */ +enum { + UPIU_TRANSACTION_NOP_OUT = 0x00, + UPIU_TRANSACTION_COMMAND = 0x01, + UPIU_TRANSACTION_DATA_OUT = 0x02, + UPIU_TRANSACTION_TASK_REQ = 0x04, + UPIU_TRANSACTION_QUERY_REQ = 0x16, +}; + +/* UTP UPIU Transaction Codes Target to Initiator */ +enum { + UPIU_TRANSACTION_NOP_IN = 0x20, + UPIU_TRANSACTION_RESPONSE = 0x21, + UPIU_TRANSACTION_DATA_IN = 0x22, + UPIU_TRANSACTION_TASK_RSP = 0x24, + UPIU_TRANSACTION_READY_XFER = 0x31, + UPIU_TRANSACTION_QUERY_RSP = 0x36, + UPIU_TRANSACTION_REJECT_UPIU = 0x3F, +}; + +/* UPIU Read/Write flags */ +enum { + UPIU_CMD_FLAGS_NONE = 0x00, + UPIU_CMD_FLAGS_WRITE = 0x20, + UPIU_CMD_FLAGS_READ = 0x40, +}; + +/* UPIU Task Attributes */ +enum { + UPIU_TASK_ATTR_SIMPLE = 0x00, + UPIU_TASK_ATTR_ORDERED = 0x01, + UPIU_TASK_ATTR_HEADQ = 0x02, + UPIU_TASK_ATTR_ACA = 0x03, +}; + +/* UPIU Query request function */ +enum { + UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, + UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, +}; + +/* Flag idn for Query Requests*/ +enum flag_idn { + QUERY_FLAG_IDN_FDEVICEINIT = 0x01, + QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, + QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, + QUERY_FLAG_IDN_BKOPS_EN = 0x04, + QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, + QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, + QUERY_FLAG_IDN_RESERVED2 = 0x07, + QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, + QUERY_FLAG_IDN_BUSY_RTC = 0x09, + QUERY_FLAG_IDN_RESERVED3 = 0x0A, + QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, + QUERY_FLAG_IDN_WB_EN = 0x0E, + QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F, + QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10, + QUERY_FLAG_IDN_HPB_RESET = 0x11, + QUERY_FLAG_IDN_HPB_EN = 0x12, +}; + +/* Attribute idn for Query requests */ +enum attr_idn { + QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, + QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01, + QUERY_ATTR_IDN_POWER_MODE = 0x02, + QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, + QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, + QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, + QUERY_ATTR_IDN_PURGE_STATUS = 0x06, + QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, + QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, + QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, + QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, + QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, + QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, + QUERY_ATTR_IDN_EE_CONTROL = 0x0D, + QUERY_ATTR_IDN_EE_STATUS = 0x0E, + QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, + QUERY_ATTR_IDN_CNTX_CONF = 0x10, + QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, + QUERY_ATTR_IDN_RESERVED2 = 0x12, + QUERY_ATTR_IDN_RESERVED3 = 0x13, + QUERY_ATTR_IDN_FFU_STATUS = 0x14, + QUERY_ATTR_IDN_PSA_STATE = 0x15, + QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, + QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17, + QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18, + QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19, + QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A, + QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C, + QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D, + QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E, + QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F, +}; + +/* Descriptor idn for Query requests */ +enum desc_idn { + QUERY_DESC_IDN_DEVICE = 0x0, + QUERY_DESC_IDN_CONFIGURATION = 0x1, + QUERY_DESC_IDN_UNIT = 0x2, + QUERY_DESC_IDN_RFU_0 = 0x3, + QUERY_DESC_IDN_INTERCONNECT = 0x4, + QUERY_DESC_IDN_STRING = 0x5, + QUERY_DESC_IDN_RFU_1 = 0x6, + QUERY_DESC_IDN_GEOMETRY = 0x7, + QUERY_DESC_IDN_POWER = 0x8, + QUERY_DESC_IDN_HEALTH = 0x9, + QUERY_DESC_IDN_MAX, +}; + +enum desc_header_offset { + QUERY_DESC_LENGTH_OFFSET = 0x00, + QUERY_DESC_DESC_TYPE_OFFSET = 0x01, +}; + +/* Unit descriptor parameters offsets in bytes*/ +enum unit_desc_param { + UNIT_DESC_PARAM_LEN = 0x0, + UNIT_DESC_PARAM_TYPE = 0x1, + UNIT_DESC_PARAM_UNIT_INDEX = 0x2, + UNIT_DESC_PARAM_LU_ENABLE = 0x3, + UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4, + UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5, + UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6, + UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7, + UNIT_DESC_PARAM_MEM_TYPE = 0x8, + UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9, + UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA, + UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB, + UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13, + UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17, + UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18, + UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20, + UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22, + UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23, + UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25, + UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27, + UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29, +}; + +/* Device descriptor parameters offsets in bytes*/ +enum device_desc_param { + DEVICE_DESC_PARAM_LEN = 0x0, + DEVICE_DESC_PARAM_TYPE = 0x1, + DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, + DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, + DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, + DEVICE_DESC_PARAM_PRTCL = 0x5, + DEVICE_DESC_PARAM_NUM_LU = 0x6, + DEVICE_DESC_PARAM_NUM_WLU = 0x7, + DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, + DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, + DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, + DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, + DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, + DEVICE_DESC_PARAM_SEC_LU = 0xD, + DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, + DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, + DEVICE_DESC_PARAM_SPEC_VER = 0x10, + DEVICE_DESC_PARAM_MANF_DATE = 0x12, + DEVICE_DESC_PARAM_MANF_NAME = 0x14, + DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, + DEVICE_DESC_PARAM_SN = 0x16, + DEVICE_DESC_PARAM_OEM_ID = 0x17, + DEVICE_DESC_PARAM_MANF_ID = 0x18, + DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, + DEVICE_DESC_PARAM_UD_LEN = 0x1B, + DEVICE_DESC_PARAM_RTT_CAP = 0x1C, + DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, + DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, + DEVICE_DESC_PARAM_FFU_TMT = 0x20, + DEVICE_DESC_PARAM_Q_DPTH = 0x21, + DEVICE_DESC_PARAM_DEV_VER = 0x22, + DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, + DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, + DEVICE_DESC_PARAM_PSA_TMT = 0x29, + DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, + DEVICE_DESC_PARAM_HPB_VER = 0x40, + DEVICE_DESC_PARAM_HPB_CONTROL = 0x42, + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F, + DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53, + DEVICE_DESC_PARAM_WB_TYPE = 0x54, + DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55, +}; + +/* Interconnect descriptor parameters offsets in bytes*/ +enum interconnect_desc_param { + INTERCONNECT_DESC_PARAM_LEN = 0x0, + INTERCONNECT_DESC_PARAM_TYPE = 0x1, + INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2, + INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4, +}; + +/* Geometry descriptor parameters offsets in bytes*/ +enum geometry_desc_param { + GEOMETRY_DESC_PARAM_LEN = 0x0, + GEOMETRY_DESC_PARAM_TYPE = 0x1, + GEOMETRY_DESC_PARAM_DEV_CAP = 0x4, + GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC, + GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD, + GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11, + GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12, + GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13, + GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14, + GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15, + GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16, + GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17, + GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18, + GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19, + GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A, + GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B, + GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C, + GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D, + GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E, + GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20, + GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24, + GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26, + GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A, + GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C, + GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30, + GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32, + GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36, + GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38, + GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C, + GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E, + GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42, + GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44, + GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48, + GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49, + GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A, + GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B, + GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F, + GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53, + GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54, + GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55, + GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56, +}; + +/* Health descriptor parameters offsets in bytes*/ +enum health_desc_param { + HEALTH_DESC_PARAM_LEN = 0x0, + HEALTH_DESC_PARAM_TYPE = 0x1, + HEALTH_DESC_PARAM_EOL_INFO = 0x2, + HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3, + HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4, +}; + +/* WriteBooster buffer mode */ +enum { + WB_BUF_MODE_LU_DEDICATED = 0x0, + WB_BUF_MODE_SHARED = 0x1, +}; + +/* + * Logical Unit Write Protect + * 00h: LU not write protected + * 01h: LU write protected when fPowerOnWPEn =1 + * 02h: LU permanently write protected when fPermanentWPEn =1 + */ +enum ufs_lu_wp_type { + UFS_LU_NO_WP = 0x00, + UFS_LU_POWER_ON_WP = 0x01, + UFS_LU_PERM_WP = 0x02, +}; + +/* bActiveICCLevel parameter current units */ +enum { + UFSHCD_NANO_AMP = 0, + UFSHCD_MICRO_AMP = 1, + UFSHCD_MILI_AMP = 2, + UFSHCD_AMP = 3, +}; + +/* Possible values for dExtendedUFSFeaturesSupport */ +enum { + UFS_DEV_LOW_TEMP_NOTIF = BIT(4), + UFS_DEV_HIGH_TEMP_NOTIF = BIT(5), + UFS_DEV_EXT_TEMP_NOTIF = BIT(6), + UFS_DEV_HPB_SUPPORT = BIT(7), + UFS_DEV_WRITE_BOOSTER_SUP = BIT(8), +}; +#define UFS_DEV_HPB_SUPPORT_VERSION 0x310 + +#define POWER_DESC_MAX_ACTV_ICC_LVLS 16 + +/* Attribute bActiveICCLevel parameter bit masks definitions */ +#define ATTR_ICC_LVL_UNIT_OFFSET 14 +#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET) +#define ATTR_ICC_LVL_VALUE_MASK 0x3FF + +/* Power descriptor parameters offsets in bytes */ +enum power_desc_param_offset { + PWR_DESC_LEN = 0x0, + PWR_DESC_TYPE = 0x1, + PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2, + PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22, + PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42, +}; + +/* Exception event mask values */ +enum { + MASK_EE_STATUS = 0xFFFF, + MASK_EE_DYNCAP_EVENT = BIT(0), + MASK_EE_SYSPOOL_EVENT = BIT(1), + MASK_EE_URGENT_BKOPS = BIT(2), + MASK_EE_TOO_HIGH_TEMP = BIT(3), + MASK_EE_TOO_LOW_TEMP = BIT(4), + MASK_EE_WRITEBOOSTER_EVENT = BIT(5), + MASK_EE_PERFORMANCE_THROTTLING = BIT(6), +}; +#define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP) + +/* Background operation status */ +enum bkops_status { + BKOPS_STATUS_NO_OP = 0x0, + BKOPS_STATUS_NON_CRITICAL = 0x1, + BKOPS_STATUS_PERF_IMPACT = 0x2, + BKOPS_STATUS_CRITICAL = 0x3, + BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL, +}; + +/* UTP QUERY Transaction Specific Fields OpCode */ +enum query_opcode { + UPIU_QUERY_OPCODE_NOP = 0x0, + UPIU_QUERY_OPCODE_READ_DESC = 0x1, + UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, + UPIU_QUERY_OPCODE_READ_ATTR = 0x3, + UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, + UPIU_QUERY_OPCODE_READ_FLAG = 0x5, + UPIU_QUERY_OPCODE_SET_FLAG = 0x6, + UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, + UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, +}; + +/* bRefClkFreq attribute values */ +enum ufs_ref_clk_freq { + REF_CLK_FREQ_19_2_MHZ = 0, + REF_CLK_FREQ_26_MHZ = 1, + REF_CLK_FREQ_38_4_MHZ = 2, + REF_CLK_FREQ_52_MHZ = 3, + REF_CLK_FREQ_INVAL = -1, +}; + +/* Query response result code */ +enum { + QUERY_RESULT_SUCCESS = 0x00, + QUERY_RESULT_NOT_READABLE = 0xF6, + QUERY_RESULT_NOT_WRITEABLE = 0xF7, + QUERY_RESULT_ALREADY_WRITTEN = 0xF8, + QUERY_RESULT_INVALID_LENGTH = 0xF9, + QUERY_RESULT_INVALID_VALUE = 0xFA, + QUERY_RESULT_INVALID_SELECTOR = 0xFB, + QUERY_RESULT_INVALID_INDEX = 0xFC, + QUERY_RESULT_INVALID_IDN = 0xFD, + QUERY_RESULT_INVALID_OPCODE = 0xFE, + QUERY_RESULT_GENERAL_FAILURE = 0xFF, +}; + +/* UTP Transfer Request Command Type (CT) */ +enum { + UPIU_COMMAND_SET_TYPE_SCSI = 0x0, + UPIU_COMMAND_SET_TYPE_UFS = 0x1, + UPIU_COMMAND_SET_TYPE_QUERY = 0x2, +}; + +/* UTP Transfer Request Command Offset */ +#define UPIU_COMMAND_TYPE_OFFSET 28 + +/* Offset of the response code in the UPIU header */ +#define UPIU_RSP_CODE_OFFSET 8 + +enum { + MASK_SCSI_STATUS = 0xFF, + MASK_TASK_RESPONSE = 0xFF00, + MASK_RSP_UPIU_RESULT = 0xFFFF, + MASK_QUERY_DATA_SEG_LEN = 0xFFFF, + MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF, + MASK_RSP_EXCEPTION_EVENT = 0x10000, + MASK_TM_SERVICE_RESP = 0xFF, + MASK_TM_FUNC = 0xFF, +}; + +/* Task management service response */ +enum { + UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00, + UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04, + UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08, + UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05, + UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09, +}; + +/* UFS device power modes */ +enum ufs_dev_pwr_mode { + UFS_ACTIVE_PWR_MODE = 1, + UFS_SLEEP_PWR_MODE = 2, + UFS_POWERDOWN_PWR_MODE = 3, + UFS_DEEPSLEEP_PWR_MODE = 4, +}; + +#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10) + +/** + * struct utp_cmd_rsp - Response UPIU structure + * @residual_transfer_count: Residual transfer count DW-3 + * @reserved: Reserved double words DW-4 to DW-7 + * @sense_data_len: Sense data length DW-8 U16 + * @sense_data: Sense data field DW-8 to DW-12 + */ +struct utp_cmd_rsp { + __be32 residual_transfer_count; + __be32 reserved[4]; + __be16 sense_data_len; + u8 sense_data[UFS_SENSE_SIZE]; +}; + +struct ufshpb_active_field { + __be16 active_rgn; + __be16 active_srgn; +}; +#define HPB_ACT_FIELD_SIZE 4 + +/** + * struct utp_hpb_rsp - Response UPIU structure + * @residual_transfer_count: Residual transfer count DW-3 + * @reserved1: Reserved double words DW-4 to DW-7 + * @sense_data_len: Sense data length DW-8 U16 + * @desc_type: Descriptor type of sense data + * @additional_len: Additional length of sense data + * @hpb_op: HPB operation type + * @lun: LUN of response UPIU + * @active_rgn_cnt: Active region count + * @inactive_rgn_cnt: Inactive region count + * @hpb_active_field: Recommended to read HPB region and subregion + * @hpb_inactive_field: To be inactivated HPB region and subregion + */ +struct utp_hpb_rsp { + __be32 residual_transfer_count; + __be32 reserved1[4]; + __be16 sense_data_len; + u8 desc_type; + u8 additional_len; + u8 hpb_op; + u8 lun; + u8 active_rgn_cnt; + u8 inactive_rgn_cnt; + struct ufshpb_active_field hpb_active_field[2]; + __be16 hpb_inactive_field[2]; +}; +#define UTP_HPB_RSP_SIZE 40 + +/** + * struct utp_upiu_rsp - general upiu response structure + * @header: UPIU header structure DW-0 to DW-2 + * @sr: fields structure for scsi command DW-3 to DW-12 + * @qr: fields structure for query request DW-3 to DW-7 + */ +struct utp_upiu_rsp { + struct utp_upiu_header header; + union { + struct utp_cmd_rsp sr; + struct utp_hpb_rsp hr; + struct utp_upiu_query qr; + }; +}; + +/** + * struct ufs_query_req - parameters for building a query request + * @query_func: UPIU header query function + * @upiu_req: the query request data + */ +struct ufs_query_req { + u8 query_func; + struct utp_upiu_query upiu_req; +}; + +/** + * struct ufs_query_resp - UPIU QUERY + * @response: device response code + * @upiu_res: query response data + */ +struct ufs_query_res { + u8 response; + struct utp_upiu_query upiu_res; +}; + +/* + * VCCQ & VCCQ2 current requirement when UFS device is in sleep state + * and link is in Hibern8 state. + */ +#define UFS_VREG_LPM_LOAD_UA 1000 /* uA */ + +struct ufs_vreg { + struct regulator *reg; + const char *name; + bool always_on; + bool enabled; + int max_uA; +}; + +struct ufs_vreg_info { + struct ufs_vreg *vcc; + struct ufs_vreg *vccq; + struct ufs_vreg *vccq2; + struct ufs_vreg *vdd_hba; +}; + +struct ufs_dev_info { + bool f_power_on_wp_en; + /* Keeps information if any of the LU is power on write protected */ + bool is_lu_power_on_wp; + /* Maximum number of general LU supported by the UFS device */ + u8 max_lu_supported; + u16 wmanufacturerid; + /*UFS device Product Name */ + u8 *model; + u16 wspecversion; + u32 clk_gating_wait_us; + + /* UFS HPB related flag */ + bool hpb_enabled; + + /* UFS WB related flags */ + bool wb_enabled; + bool wb_buf_flush_enabled; + u8 wb_dedicated_lu; + u8 wb_buffer_type; + + bool b_rpm_dev_flush_capable; + u8 b_presrv_uspc_en; +}; + +/* + * This enum is used in string mapping in include/trace/events/ufs.h. + */ +enum ufs_trace_str_t { + UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP, + UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR, + UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR +}; + +/* + * Transaction Specific Fields (TSF) type in the UPIU package, this enum is + * used in include/trace/events/ufs.h for UFS command trace. + */ +enum ufs_trace_tsf_t { + UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT +}; + +#endif /* End of Header */ diff --git a/include/ufs/ufs_quirks.h b/include/ufs/ufs_quirks.h new file mode 100644 index 0000000000..bcb4f004be --- /dev/null +++ b/include/ufs/ufs_quirks.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#ifndef _UFS_QUIRKS_H_ +#define _UFS_QUIRKS_H_ + +/* return true if s1 is a prefix of s2 */ +#define STR_PRFX_EQUAL(s1, s2) !strncmp(s1, s2, strlen(s1)) + +#define UFS_ANY_VENDOR 0xFFFF +#define UFS_ANY_MODEL "ANY_MODEL" + +#define UFS_VENDOR_MICRON 0x12C +#define UFS_VENDOR_SAMSUNG 0x1CE +#define UFS_VENDOR_SKHYNIX 0x1AD +#define UFS_VENDOR_TOSHIBA 0x198 +#define UFS_VENDOR_WDC 0x145 + +/** + * ufs_dev_quirk - ufs device quirk info + * @card: ufs card details + * @quirk: device quirk + */ +struct ufs_dev_quirk { + u16 wmanufacturerid; + const u8 *model; + unsigned int quirk; +}; + +/* + * Some vendor's UFS device sends back to back NACs for the DL data frames + * causing the host controller to raise the DFES error status. Sometimes + * such UFS devices send back to back NAC without waiting for new + * retransmitted DL frame from the host and in such cases it might be possible + * the Host UniPro goes into bad state without raising the DFES error + * interrupt. If this happens then all the pending commands would timeout + * only after respective SW command (which is generally too large). + * + * We can workaround such device behaviour like this: + * - As soon as SW sees the DL NAC error, it should schedule the error handler + * - Error handler would sleep for 50ms to see if there are any fatal errors + * raised by UFS controller. + * - If there are fatal errors then SW does normal error recovery. + * - If there are no fatal errors then SW sends the NOP command to device + * to check if link is alive. + * - If NOP command times out, SW does normal error recovery + * - If NOP command succeed, skip the error handling. + * + * If DL NAC error is seen multiple times with some vendor's UFS devices then + * enable this quirk to initiate quick error recovery and also silence related + * error logs to reduce spamming of kernel logs. + */ +#define UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS (1 << 2) + +/* + * Few Toshiba UFS device models advertise RX_MIN_ACTIVATETIME_CAPABILITY as + * 600us which may not be enough for reliable hibern8 exit hardware sequence + * from UFS device. + * To workaround this issue, host should set its PA_TACTIVATE time to 1ms even + * if device advertises RX_MIN_ACTIVATETIME_CAPABILITY less than 1ms. + */ +#define UFS_DEVICE_QUIRK_PA_TACTIVATE (1 << 4) + +/* + * It seems some UFS devices may keep drawing more than sleep current + * (atleast for 500us) from UFS rails (especially from VCCQ rail). + * To avoid this situation, add 2ms delay before putting these UFS + * rails in LPM mode. + */ +#define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6) + +/* + * Some UFS devices require host PA_TACTIVATE to be lower than device + * PA_TACTIVATE, enabling this quirk ensure this. + */ +#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7) + +/* + * The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for + * some vendors. + * Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime. + * Gear switch can be issued by host controller as an error recovery and any + * software delay will not help on this case so we need to increase + * PA_SaveConfigTime to >32us as per vendor recommendation. + */ +#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8) + +/* + * Some UFS devices require VS_DebugSaveConfigTime is 0x10, + * enabling this quirk ensure this. + */ +#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9) + +/* + * Some pre-3.1 UFS devices can support extended features by upgrading + * the firmware. Enable this quirk to make UFS core driver probe and enable + * supported features on such devices. + */ +#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10) + +/* + * Some UFS devices require delay after VCC power rail is turned-off. + * Enable this quirk to introduce 5ms delays after VCC power-off during + * suspend flow. + */ +#define UFS_DEVICE_QUIRK_DELAY_AFTER_LPM (1 << 11) + +/* + * Some UFS devices require L2P entry should be swapped before being sent to the + * UFS device for HPB READ command. + */ +#define UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ (1 << 12) + +#endif /* UFS_QUIRKS_H_ */ diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h new file mode 100644 index 0000000000..7fe1a926cd --- /dev/null +++ b/include/ufs/ufshcd.h @@ -0,0 +1,1245 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal Flash Storage Host controller driver + * Copyright (C) 2011-2013 Samsung India Software Operations + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * Authors: + * Santosh Yaraganavi + * Vinayak Holikatti + */ + +#ifndef _UFSHCD_H +#define _UFSHCD_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UFSHCD "ufshcd" + +struct ufs_hba; + +enum dev_cmd_type { + DEV_CMD_TYPE_NOP = 0x0, + DEV_CMD_TYPE_QUERY = 0x1, +}; + +enum ufs_event_type { + /* uic specific errors */ + UFS_EVT_PA_ERR = 0, + UFS_EVT_DL_ERR, + UFS_EVT_NL_ERR, + UFS_EVT_TL_ERR, + UFS_EVT_DME_ERR, + + /* fatal errors */ + UFS_EVT_AUTO_HIBERN8_ERR, + UFS_EVT_FATAL_ERR, + UFS_EVT_LINK_STARTUP_FAIL, + UFS_EVT_RESUME_ERR, + UFS_EVT_SUSPEND_ERR, + UFS_EVT_WL_SUSP_ERR, + UFS_EVT_WL_RES_ERR, + + /* abnormal events */ + UFS_EVT_DEV_RESET, + UFS_EVT_HOST_RESET, + UFS_EVT_ABORT, + + UFS_EVT_CNT, +}; + +/** + * struct uic_command - UIC command structure + * @command: UIC command + * @argument1: UIC command argument 1 + * @argument2: UIC command argument 2 + * @argument3: UIC command argument 3 + * @cmd_active: Indicate if UIC command is outstanding + * @done: UIC command completion + */ +struct uic_command { + u32 command; + u32 argument1; + u32 argument2; + u32 argument3; + int cmd_active; + struct completion done; +}; + +/* Used to differentiate the power management options */ +enum ufs_pm_op { + UFS_RUNTIME_PM, + UFS_SYSTEM_PM, + UFS_SHUTDOWN_PM, +}; + +/* Host <-> Device UniPro Link state */ +enum uic_link_state { + UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ + UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ + UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ + UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ +}; + +#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) +#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ + UIC_LINK_ACTIVE_STATE) +#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ + UIC_LINK_HIBERN8_STATE) +#define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ + UIC_LINK_BROKEN_STATE) +#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) +#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ + UIC_LINK_ACTIVE_STATE) +#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ + UIC_LINK_HIBERN8_STATE) +#define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ + UIC_LINK_BROKEN_STATE) + +#define ufshcd_set_ufs_dev_active(h) \ + ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) +#define ufshcd_set_ufs_dev_sleep(h) \ + ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) +#define ufshcd_set_ufs_dev_poweroff(h) \ + ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) +#define ufshcd_set_ufs_dev_deepsleep(h) \ + ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) +#define ufshcd_is_ufs_dev_active(h) \ + ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) +#define ufshcd_is_ufs_dev_sleep(h) \ + ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) +#define ufshcd_is_ufs_dev_poweroff(h) \ + ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) +#define ufshcd_is_ufs_dev_deepsleep(h) \ + ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) + +/* + * UFS Power management levels. + * Each level is in increasing order of power savings, except DeepSleep + * which is lower than PowerDown with power on but not PowerDown with + * power off. + */ +enum ufs_pm_level { + UFS_PM_LVL_0, + UFS_PM_LVL_1, + UFS_PM_LVL_2, + UFS_PM_LVL_3, + UFS_PM_LVL_4, + UFS_PM_LVL_5, + UFS_PM_LVL_6, + UFS_PM_LVL_MAX +}; + +struct ufs_pm_lvl_states { + enum ufs_dev_pwr_mode dev_state; + enum uic_link_state link_state; +}; + +/** + * struct ufshcd_lrb - local reference block + * @utr_descriptor_ptr: UTRD address of the command + * @ucd_req_ptr: UCD address of the command + * @ucd_rsp_ptr: Response UPIU address for this command + * @ucd_prdt_ptr: PRDT address of the command + * @utrd_dma_addr: UTRD dma address for debug + * @ucd_prdt_dma_addr: PRDT dma address for debug + * @ucd_rsp_dma_addr: UPIU response dma address for debug + * @ucd_req_dma_addr: UPIU request dma address for debug + * @cmd: pointer to SCSI command + * @scsi_status: SCSI status of the command + * @command_type: SCSI, UFS, Query. + * @task_tag: Task tag of the command + * @lun: LUN of the command + * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) + * @issue_time_stamp: time stamp for debug purposes + * @compl_time_stamp: time stamp for statistics + * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) + * @data_unit_num: the data unit number for the first block for inline crypto + * @req_abort_skip: skip request abort task flag + */ +struct ufshcd_lrb { + struct utp_transfer_req_desc *utr_descriptor_ptr; + struct utp_upiu_req *ucd_req_ptr; + struct utp_upiu_rsp *ucd_rsp_ptr; + struct ufshcd_sg_entry *ucd_prdt_ptr; + + dma_addr_t utrd_dma_addr; + dma_addr_t ucd_req_dma_addr; + dma_addr_t ucd_rsp_dma_addr; + dma_addr_t ucd_prdt_dma_addr; + + struct scsi_cmnd *cmd; + int scsi_status; + + int command_type; + int task_tag; + u8 lun; /* UPIU LUN id field is only 8-bit wide */ + bool intr_cmd; + ktime_t issue_time_stamp; + ktime_t compl_time_stamp; +#ifdef CONFIG_SCSI_UFS_CRYPTO + int crypto_key_slot; + u64 data_unit_num; +#endif + + bool req_abort_skip; +}; + +/** + * struct ufs_query - holds relevant data structures for query request + * @request: request upiu and function + * @descriptor: buffer for sending/receiving descriptor + * @response: response upiu and response + */ +struct ufs_query { + struct ufs_query_req request; + u8 *descriptor; + struct ufs_query_res response; +}; + +/** + * struct ufs_dev_cmd - all assosiated fields with device management commands + * @type: device management command type - Query, NOP OUT + * @lock: lock to allow one command at a time + * @complete: internal commands completion + * @query: Device management query information + */ +struct ufs_dev_cmd { + enum dev_cmd_type type; + struct mutex lock; + struct completion *complete; + struct ufs_query query; +}; + +/** + * struct ufs_clk_info - UFS clock related info + * @list: list headed by hba->clk_list_head + * @clk: clock node + * @name: clock name + * @max_freq: maximum frequency supported by the clock + * @min_freq: min frequency that can be used for clock scaling + * @curr_freq: indicates the current frequency that it is set to + * @keep_link_active: indicates that the clk should not be disabled if + * link is active + * @enabled: variable to check against multiple enable/disable + */ +struct ufs_clk_info { + struct list_head list; + struct clk *clk; + const char *name; + u32 max_freq; + u32 min_freq; + u32 curr_freq; + bool keep_link_active; + bool enabled; +}; + +enum ufs_notify_change_status { + PRE_CHANGE, + POST_CHANGE, +}; + +struct ufs_pa_layer_attr { + u32 gear_rx; + u32 gear_tx; + u32 lane_rx; + u32 lane_tx; + u32 pwr_rx; + u32 pwr_tx; + u32 hs_rate; +}; + +struct ufs_pwr_mode_info { + bool is_valid; + struct ufs_pa_layer_attr info; +}; + +/** + * struct ufs_hba_variant_ops - variant specific callbacks + * @name: variant name + * @init: called when the driver is initialized + * @exit: called to cleanup everything done in init + * @get_ufs_hci_version: called to get UFS HCI version + * @clk_scale_notify: notifies that clks are scaled up/down + * @setup_clocks: called before touching any of the controller registers + * @hce_enable_notify: called before and after HCE enable bit is set to allow + * variant specific Uni-Pro initialization. + * @link_startup_notify: called before and after Link startup is carried out + * to allow variant specific Uni-Pro initialization. + * @pwr_change_notify: called before and after a power mode change + * is carried out to allow vendor spesific capabilities + * to be set. + * @setup_xfer_req: called before any transfer request is issued + * to set some things + * @setup_task_mgmt: called before any task management request is issued + * to set some things + * @hibern8_notify: called around hibern8 enter/exit + * @apply_dev_quirks: called to apply device specific quirks + * @fixup_dev_quirks: called to modify device specific quirks + * @suspend: called during host controller PM callback + * @resume: called during host controller PM callback + * @dbg_register_dump: used to dump controller debug information + * @phy_initialization: used to initialize phys + * @device_reset: called to issue a reset pulse on the UFS device + * @config_scaling_param: called to configure clock scaling parameters + * @program_key: program or evict an inline encryption key + * @event_notify: called to notify important events + */ +struct ufs_hba_variant_ops { + const char *name; + int (*init)(struct ufs_hba *); + void (*exit)(struct ufs_hba *); + u32 (*get_ufs_hci_version)(struct ufs_hba *); + int (*clk_scale_notify)(struct ufs_hba *, bool, + enum ufs_notify_change_status); + int (*setup_clocks)(struct ufs_hba *, bool, + enum ufs_notify_change_status); + int (*hce_enable_notify)(struct ufs_hba *, + enum ufs_notify_change_status); + int (*link_startup_notify)(struct ufs_hba *, + enum ufs_notify_change_status); + int (*pwr_change_notify)(struct ufs_hba *, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *, + struct ufs_pa_layer_attr *); + void (*setup_xfer_req)(struct ufs_hba *hba, int tag, + bool is_scsi_cmd); + void (*setup_task_mgmt)(struct ufs_hba *, int, u8); + void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, + enum ufs_notify_change_status); + int (*apply_dev_quirks)(struct ufs_hba *hba); + void (*fixup_dev_quirks)(struct ufs_hba *hba); + int (*suspend)(struct ufs_hba *, enum ufs_pm_op, + enum ufs_notify_change_status); + int (*resume)(struct ufs_hba *, enum ufs_pm_op); + void (*dbg_register_dump)(struct ufs_hba *hba); + int (*phy_initialization)(struct ufs_hba *); + int (*device_reset)(struct ufs_hba *hba); + void (*config_scaling_param)(struct ufs_hba *hba, + struct devfreq_dev_profile *profile, + struct devfreq_simple_ondemand_data *data); + int (*program_key)(struct ufs_hba *hba, + const union ufs_crypto_cfg_entry *cfg, int slot); + void (*event_notify)(struct ufs_hba *hba, + enum ufs_event_type evt, void *data); +}; + +/* clock gating state */ +enum clk_gating_state { + CLKS_OFF, + CLKS_ON, + REQ_CLKS_OFF, + REQ_CLKS_ON, +}; + +/** + * struct ufs_clk_gating - UFS clock gating related info + * @gate_work: worker to turn off clocks after some delay as specified in + * delay_ms + * @ungate_work: worker to turn on clocks that will be used in case of + * interrupt context + * @state: the current clocks state + * @delay_ms: gating delay in ms + * @is_suspended: clk gating is suspended when set to 1 which can be used + * during suspend/resume + * @delay_attr: sysfs attribute to control delay_attr + * @enable_attr: sysfs attribute to enable/disable clock gating + * @is_enabled: Indicates the current status of clock gating + * @is_initialized: Indicates whether clock gating is initialized or not + * @active_reqs: number of requests that are pending and should be waited for + * completion before gating clocks. + * @clk_gating_workq: workqueue for clock gating work. + */ +struct ufs_clk_gating { + struct delayed_work gate_work; + struct work_struct ungate_work; + enum clk_gating_state state; + unsigned long delay_ms; + bool is_suspended; + struct device_attribute delay_attr; + struct device_attribute enable_attr; + bool is_enabled; + bool is_initialized; + int active_reqs; + struct workqueue_struct *clk_gating_workq; +}; + +struct ufs_saved_pwr_info { + struct ufs_pa_layer_attr info; + bool is_valid; +}; + +/** + * struct ufs_clk_scaling - UFS clock scaling related data + * @active_reqs: number of requests that are pending. If this is zero when + * devfreq ->target() function is called then schedule "suspend_work" to + * suspend devfreq. + * @tot_busy_t: Total busy time in current polling window + * @window_start_t: Start time (in jiffies) of the current polling window + * @busy_start_t: Start time of current busy period + * @enable_attr: sysfs attribute to enable/disable clock scaling + * @saved_pwr_info: UFS power mode may also be changed during scaling and this + * one keeps track of previous power mode. + * @workq: workqueue to schedule devfreq suspend/resume work + * @suspend_work: worker to suspend devfreq + * @resume_work: worker to resume devfreq + * @min_gear: lowest HS gear to scale down to + * @is_enabled: tracks if scaling is currently enabled or not, controlled by + * clkscale_enable sysfs node + * @is_allowed: tracks if scaling is currently allowed or not, used to block + * clock scaling which is not invoked from devfreq governor + * @is_initialized: Indicates whether clock scaling is initialized or not + * @is_busy_started: tracks if busy period has started or not + * @is_suspended: tracks if devfreq is suspended or not + */ +struct ufs_clk_scaling { + int active_reqs; + unsigned long tot_busy_t; + ktime_t window_start_t; + ktime_t busy_start_t; + struct device_attribute enable_attr; + struct ufs_saved_pwr_info saved_pwr_info; + struct workqueue_struct *workq; + struct work_struct suspend_work; + struct work_struct resume_work; + u32 min_gear; + bool is_enabled; + bool is_allowed; + bool is_initialized; + bool is_busy_started; + bool is_suspended; +}; + +#define UFS_EVENT_HIST_LENGTH 8 +/** + * struct ufs_event_hist - keeps history of errors + * @pos: index to indicate cyclic buffer position + * @val: cyclic buffer for registers value + * @tstamp: cyclic buffer for time stamp + * @cnt: error counter + */ +struct ufs_event_hist { + int pos; + u32 val[UFS_EVENT_HIST_LENGTH]; + ktime_t tstamp[UFS_EVENT_HIST_LENGTH]; + unsigned long long cnt; +}; + +/** + * struct ufs_stats - keeps usage/err statistics + * @last_intr_status: record the last interrupt status. + * @last_intr_ts: record the last interrupt timestamp. + * @hibern8_exit_cnt: Counter to keep track of number of exits, + * reset this after link-startup. + * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. + * Clear after the first successful command completion. + * @event: array with event history. + */ +struct ufs_stats { + u32 last_intr_status; + ktime_t last_intr_ts; + + u32 hibern8_exit_cnt; + ktime_t last_hibern8_exit_tstamp; + struct ufs_event_hist event[UFS_EVT_CNT]; +}; + +/** + * enum ufshcd_state - UFS host controller state + * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command + * processing. + * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process + * SCSI commands. + * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. + * SCSI commands may be submitted to the controller. + * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail + * newly submitted SCSI commands with error code DID_BAD_TARGET. + * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery + * failed. Fail all SCSI commands with error code DID_ERROR. + */ +enum ufshcd_state { + UFSHCD_STATE_RESET, + UFSHCD_STATE_OPERATIONAL, + UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, + UFSHCD_STATE_EH_SCHEDULED_FATAL, + UFSHCD_STATE_ERROR, +}; + +enum ufshcd_quirks { + /* Interrupt aggregation support is broken */ + UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, + + /* + * delay before each dme command is required as the unipro + * layer has shown instabilities + */ + UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, + + /* + * If UFS host controller is having issue in processing LCC (Line + * Control Command) coming from device then enable this quirk. + * When this quirk is enabled, host controller driver should disable + * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE + * attribute of device to 0). + */ + UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, + + /* + * The attribute PA_RXHSUNTERMCAP specifies whether or not the + * inbound Link supports unterminated line in HS mode. Setting this + * attribute to 1 fixes moving to HS gear. + */ + UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, + + /* + * This quirk needs to be enabled if the host controller only allows + * accessing the peer dme attributes in AUTO mode (FAST AUTO or + * SLOW AUTO). + */ + UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, + + /* + * This quirk needs to be enabled if the host controller doesn't + * advertise the correct version in UFS_VER register. If this quirk + * is enabled, standard UFS host driver will call the vendor specific + * ops (get_ufs_hci_version) to get the correct version. + */ + UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, + + /* + * Clear handling for transfer/task request list is just opposite. + */ + UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, + + /* + * This quirk needs to be enabled if host controller doesn't allow + * that the interrupt aggregation timer and counter are reset by s/w. + */ + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, + + /* + * This quirks needs to be enabled if host controller cannot be + * enabled via HCE register. + */ + UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, + + /* + * This quirk needs to be enabled if the host controller regards + * resolution of the values of PRDTO and PRDTL in UTRD as byte. + */ + UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, + + /* + * This quirk needs to be enabled if the host controller reports + * OCS FATAL ERROR with device error through sense data + */ + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it doesn't work. + */ + UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, + + /* + * This quirk needs to disable manual flush for write booster + */ + UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, + + /* + * This quirk needs to disable unipro timeout values + * before power mode change + */ + UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, + + /* + * This quirk allows only sg entries aligned with page size. + */ + UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, + + /* + * This quirk needs to be enabled if the host controller does not + * support UIC command + */ + UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, + + /* + * This quirk needs to be enabled if the host controller cannot + * support physical host configuration. + */ + UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, + + /* + * This quirk needs to be enabled if the host controller has + * 64-bit addressing supported capability but it doesn't work. + */ + UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it's FASTAUTO only. + */ + UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, +}; + +enum ufshcd_caps { + /* Allow dynamic clk gating */ + UFSHCD_CAP_CLK_GATING = 1 << 0, + + /* Allow hiberb8 with clk gating */ + UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, + + /* Allow dynamic clk scaling */ + UFSHCD_CAP_CLK_SCALING = 1 << 2, + + /* Allow auto bkops to enabled during runtime suspend */ + UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, + + /* + * This capability allows host controller driver to use the UFS HCI's + * interrupt aggregation capability. + * CAUTION: Enabling this might reduce overall UFS throughput. + */ + UFSHCD_CAP_INTR_AGGR = 1 << 4, + + /* + * This capability allows the device auto-bkops to be always enabled + * except during suspend (both runtime and suspend). + * Enabling this capability means that device will always be allowed + * to do background operation when it's active but it might degrade + * the performance of ongoing read/write operations. + */ + UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, + + /* + * This capability allows host controller driver to automatically + * enable runtime power management by itself instead of waiting + * for userspace to control the power management. + */ + UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, + + /* + * This capability allows the host controller driver to turn-on + * WriteBooster, if the underlying device supports it and is + * provisioned to be used. This would increase the write performance. + */ + UFSHCD_CAP_WB_EN = 1 << 7, + + /* + * This capability allows the host controller driver to use the + * inline crypto engine, if it is present + */ + UFSHCD_CAP_CRYPTO = 1 << 8, + + /* + * This capability allows the controller regulators to be put into + * lpm mode aggressively during clock gating. + * This would increase power savings. + */ + UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, + + /* + * This capability allows the host controller driver to use DeepSleep, + * if it is supported by the UFS device. The host controller driver must + * support device hardware reset via the hba->device_reset() callback, + * in order to exit DeepSleep state. + */ + UFSHCD_CAP_DEEPSLEEP = 1 << 10, + + /* + * This capability allows the host controller driver to use temperature + * notification if it is supported by the UFS device. + */ + UFSHCD_CAP_TEMP_NOTIF = 1 << 11, +}; + +struct ufs_hba_variant_params { + struct devfreq_dev_profile devfreq_profile; + struct devfreq_simple_ondemand_data ondemand_data; + u16 hba_enable_delay_us; + u32 wb_flush_threshold; +}; + +#ifdef CONFIG_SCSI_UFS_HPB +/** + * struct ufshpb_dev_info - UFSHPB device related info + * @num_lu: the number of user logical unit to check whether all lu finished + * initialization + * @rgn_size: device reported HPB region size + * @srgn_size: device reported HPB sub-region size + * @slave_conf_cnt: counter to check all lu finished initialization + * @hpb_disabled: flag to check if HPB is disabled + * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value + * @is_legacy: flag to check HPB 1.0 + * @control_mode: either host or device + */ +struct ufshpb_dev_info { + int num_lu; + int rgn_size; + int srgn_size; + atomic_t slave_conf_cnt; + bool hpb_disabled; + u8 max_hpb_single_cmd; + bool is_legacy; + u8 control_mode; +}; +#endif + +struct ufs_hba_monitor { + unsigned long chunk_size; + + unsigned long nr_sec_rw[2]; + ktime_t total_busy[2]; + + unsigned long nr_req[2]; + /* latencies*/ + ktime_t lat_sum[2]; + ktime_t lat_max[2]; + ktime_t lat_min[2]; + + u32 nr_queued[2]; + ktime_t busy_start_ts[2]; + + ktime_t enabled_ts; + bool enabled; +}; + +/** + * struct ufs_hba - per adapter private structure + * @mmio_base: UFSHCI base register address + * @ucdl_base_addr: UFS Command Descriptor base address + * @utrdl_base_addr: UTP Transfer Request Descriptor base address + * @utmrdl_base_addr: UTP Task Management Descriptor base address + * @ucdl_dma_addr: UFS Command Descriptor DMA address + * @utrdl_dma_addr: UTRDL DMA address + * @utmrdl_dma_addr: UTMRDL DMA address + * @host: Scsi_Host instance of the driver + * @dev: device handle + * @ufs_device_wlun: WLUN that controls the entire UFS device. + * @hwmon_device: device instance registered with the hwmon core. + * @curr_dev_pwr_mode: active UFS device power mode. + * @uic_link_state: active state of the link to the UFS device. + * @rpm_lvl: desired UFS power management level during runtime PM. + * @spm_lvl: desired UFS power management level during system PM. + * @pm_op_in_progress: whether or not a PM operation is in progress. + * @ahit: value of Auto-Hibernate Idle Timer register. + * @lrb: local reference block + * @outstanding_tasks: Bits representing outstanding task requests + * @outstanding_lock: Protects @outstanding_reqs. + * @outstanding_reqs: Bits representing outstanding transfer requests + * @capabilities: UFS Controller Capabilities + * @nutrs: Transfer Request Queue depth supported by controller + * @nutmrs: Task Management Queue depth supported by controller + * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. + * @ufs_version: UFS Version to which controller complies + * @vops: pointer to variant specific operations + * @vps: pointer to variant specific parameters + * @priv: pointer to variant specific private data + * @irq: Irq number of the controller + * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. + * @dev_ref_clk_freq: reference clock frequency + * @quirks: bitmask with information about deviations from the UFSHCI standard. + * @dev_quirks: bitmask with information about deviations from the UFS standard. + * @tmf_tag_set: TMF tag set. + * @tmf_queue: Used to allocate TMF tags. + * @tmf_rqs: array with pointers to TMF requests while these are in progress. + * @active_uic_cmd: handle of active UIC command + * @uic_cmd_mutex: mutex for UIC command + * @uic_async_done: completion used during UIC processing + * @ufshcd_state: UFSHCD state + * @eh_flags: Error handling flags + * @intr_mask: Interrupt Mask Bits + * @ee_ctrl_mask: Exception event control mask + * @ee_drv_mask: Exception event mask for driver + * @ee_usr_mask: Exception event mask for user (set via debugfs) + * @ee_ctrl_mutex: Used to serialize exception event information. + * @is_powered: flag to check if HBA is powered + * @shutting_down: flag to check if shutdown has been invoked + * @host_sem: semaphore used to serialize concurrent contexts + * @eh_wq: Workqueue that eh_work works on + * @eh_work: Worker to handle UFS errors that require s/w attention + * @eeh_work: Worker to handle exception events + * @errors: HBA errors + * @uic_error: UFS interconnect layer error status + * @saved_err: sticky error mask + * @saved_uic_err: sticky UIC error mask + * @ufs_stats: various error counters + * @force_reset: flag to force eh_work perform a full reset + * @force_pmc: flag to force a power mode change + * @silence_err_logs: flag to silence error logs + * @dev_cmd: ufs device management command information + * @last_dme_cmd_tstamp: time stamp of the last completed DME command + * @nop_out_timeout: NOP OUT timeout value + * @dev_info: information about the UFS device + * @auto_bkops_enabled: to track whether bkops is enabled in device + * @vreg_info: UFS device voltage regulator information + * @clk_list_head: UFS host controller clocks list node head + * @req_abort_count: number of times ufshcd_abort() has been called + * @lanes_per_direction: number of lanes per data direction between the UFS + * controller and the UFS device. + * @pwr_info: holds current power mode + * @max_pwr_info: keeps the device max valid pwm + * @clk_gating: information related to clock gating + * @caps: bitmask with information about UFS controller capabilities + * @devfreq: frequency scaling information owned by the devfreq core + * @clk_scaling: frequency scaling information owned by the UFS driver + * @is_sys_suspended: whether or not the entire system has been suspended + * @urgent_bkops_lvl: keeps track of urgent bkops level for device + * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for + * device is known or not. + * @clk_scaling_lock: used to serialize device commands and clock scaling + * @desc_size: descriptor sizes reported by device + * @scsi_block_reqs_cnt: reference counting for scsi block requests + * @bsg_dev: struct device associated with the BSG queue + * @bsg_queue: BSG queue associated with the UFS controller + * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power + * management) after the UFS device has finished a WriteBooster buffer + * flush or auto BKOP. + * @ufshpb_dev: information related to HPB (Host Performance Booster). + * @monitor: statistics about UFS commands + * @crypto_capabilities: Content of crypto capabilities register (0x100) + * @crypto_cap_array: Array of crypto capabilities + * @crypto_cfg_register: Start of the crypto cfg array + * @crypto_profile: the crypto profile of this hba (if applicable) + * @debugfs_root: UFS controller debugfs root directory + * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay + * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore + * ee_ctrl_mask + * @luns_avail: number of regular and well known LUNs supported by the UFS + * device + * @complete_put: whether or not to call ufshcd_rpm_put() from inside + * ufshcd_resume_complete() + */ +struct ufs_hba { + void __iomem *mmio_base; + + /* Virtual memory reference */ + struct utp_transfer_cmd_desc *ucdl_base_addr; + struct utp_transfer_req_desc *utrdl_base_addr; + struct utp_task_req_desc *utmrdl_base_addr; + + /* DMA memory reference */ + dma_addr_t ucdl_dma_addr; + dma_addr_t utrdl_dma_addr; + dma_addr_t utmrdl_dma_addr; + + struct Scsi_Host *host; + struct device *dev; + struct scsi_device *ufs_device_wlun; + +#ifdef CONFIG_SCSI_UFS_HWMON + struct device *hwmon_device; +#endif + + enum ufs_dev_pwr_mode curr_dev_pwr_mode; + enum uic_link_state uic_link_state; + /* Desired UFS power management level during runtime PM */ + enum ufs_pm_level rpm_lvl; + /* Desired UFS power management level during system PM */ + enum ufs_pm_level spm_lvl; + int pm_op_in_progress; + + /* Auto-Hibernate Idle Timer register value */ + u32 ahit; + + struct ufshcd_lrb *lrb; + + unsigned long outstanding_tasks; + spinlock_t outstanding_lock; + unsigned long outstanding_reqs; + + u32 capabilities; + int nutrs; + int nutmrs; + u32 reserved_slot; + u32 ufs_version; + const struct ufs_hba_variant_ops *vops; + struct ufs_hba_variant_params *vps; + void *priv; + unsigned int irq; + bool is_irq_enabled; + enum ufs_ref_clk_freq dev_ref_clk_freq; + + unsigned int quirks; /* Deviations from standard UFSHCI spec. */ + + /* Device deviations from standard UFS device spec. */ + unsigned int dev_quirks; + + struct blk_mq_tag_set tmf_tag_set; + struct request_queue *tmf_queue; + struct request **tmf_rqs; + + struct uic_command *active_uic_cmd; + struct mutex uic_cmd_mutex; + struct completion *uic_async_done; + + enum ufshcd_state ufshcd_state; + u32 eh_flags; + u32 intr_mask; + u16 ee_ctrl_mask; + u16 ee_drv_mask; + u16 ee_usr_mask; + struct mutex ee_ctrl_mutex; + bool is_powered; + bool shutting_down; + struct semaphore host_sem; + + /* Work Queues */ + struct workqueue_struct *eh_wq; + struct work_struct eh_work; + struct work_struct eeh_work; + + /* HBA Errors */ + u32 errors; + u32 uic_error; + u32 saved_err; + u32 saved_uic_err; + struct ufs_stats ufs_stats; + bool force_reset; + bool force_pmc; + bool silence_err_logs; + + /* Device management request data */ + struct ufs_dev_cmd dev_cmd; + ktime_t last_dme_cmd_tstamp; + int nop_out_timeout; + + /* Keeps information of the UFS device connected to this host */ + struct ufs_dev_info dev_info; + bool auto_bkops_enabled; + struct ufs_vreg_info vreg_info; + struct list_head clk_list_head; + + /* Number of requests aborts */ + int req_abort_count; + + /* Number of lanes available (1 or 2) for Rx/Tx */ + u32 lanes_per_direction; + struct ufs_pa_layer_attr pwr_info; + struct ufs_pwr_mode_info max_pwr_info; + + struct ufs_clk_gating clk_gating; + /* Control to enable/disable host capabilities */ + u32 caps; + + struct devfreq *devfreq; + struct ufs_clk_scaling clk_scaling; + bool is_sys_suspended; + + enum bkops_status urgent_bkops_lvl; + bool is_urgent_bkops_lvl_checked; + + struct rw_semaphore clk_scaling_lock; + unsigned char desc_size[QUERY_DESC_IDN_MAX]; + atomic_t scsi_block_reqs_cnt; + + struct device bsg_dev; + struct request_queue *bsg_queue; + struct delayed_work rpm_dev_flush_recheck_work; + +#ifdef CONFIG_SCSI_UFS_HPB + struct ufshpb_dev_info ufshpb_dev; +#endif + + struct ufs_hba_monitor monitor; + +#ifdef CONFIG_SCSI_UFS_CRYPTO + union ufs_crypto_capabilities crypto_capabilities; + union ufs_crypto_cap_entry *crypto_cap_array; + u32 crypto_cfg_register; + struct blk_crypto_profile crypto_profile; +#endif +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + struct delayed_work debugfs_ee_work; + u32 debugfs_ee_rate_limit_ms; +#endif + u32 luns_avail; + bool complete_put; +}; + +/* Returns true if clocks can be gated. Otherwise false */ +static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_CLK_GATING; +} +static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; +} +static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_CLK_SCALING; +} +static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; +} +static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; +} + +static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) +{ + return (hba->caps & UFSHCD_CAP_INTR_AGGR) && + !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); +} + +static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) +{ + return !!(ufshcd_is_link_hibern8(hba) && + (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); +} + +static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) +{ + return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && + !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); +} + +static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) +{ + return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); +} + +static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_WB_EN; +} + +#define ufshcd_writel(hba, val, reg) \ + writel((val), (hba)->mmio_base + (reg)) +#define ufshcd_readl(hba, reg) \ + readl((hba)->mmio_base + (reg)) + +/** + * ufshcd_rmwl - perform read/modify/write for a controller register + * @hba: per adapter instance + * @mask: mask to apply on read value + * @val: actual value to write + * @reg: register address + */ +static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) +{ + u32 tmp; + + tmp = ufshcd_readl(hba, reg); + tmp &= ~mask; + tmp |= (val & mask); + ufshcd_writel(hba, tmp, reg); +} + +int ufshcd_alloc_host(struct device *, struct ufs_hba **); +void ufshcd_dealloc_host(struct ufs_hba *); +int ufshcd_hba_enable(struct ufs_hba *hba); +int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); +int ufshcd_link_recovery(struct ufs_hba *hba); +int ufshcd_make_hba_operational(struct ufs_hba *hba); +void ufshcd_remove(struct ufs_hba *); +int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); +int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); +void ufshcd_delay_us(unsigned long us, unsigned long tolerance); +void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); +void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); +void ufshcd_hba_stop(struct ufs_hba *hba); +void ufshcd_schedule_eh_work(struct ufs_hba *hba); + +static inline void check_upiu_size(void) +{ + BUILD_BUG_ON(ALIGNED_UPIU_SIZE < + GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); +} + +/** + * ufshcd_set_variant - set variant specific data to the hba + * @hba: per adapter instance + * @variant: pointer to variant specific data + */ +static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) +{ + BUG_ON(!hba); + hba->priv = variant; +} + +/** + * ufshcd_get_variant - get variant specific data from the hba + * @hba: per adapter instance + */ +static inline void *ufshcd_get_variant(struct ufs_hba *hba) +{ + BUG_ON(!hba); + return hba->priv; +} + +#ifdef CONFIG_PM +extern int ufshcd_runtime_suspend(struct device *dev); +extern int ufshcd_runtime_resume(struct device *dev); +#endif +#ifdef CONFIG_PM_SLEEP +extern int ufshcd_system_suspend(struct device *dev); +extern int ufshcd_system_resume(struct device *dev); +#endif +extern int ufshcd_shutdown(struct ufs_hba *hba); +extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, + int agreed_gear, + int adapt_val); +extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + u8 attr_set, u32 mib_val, u8 peer); +extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); +extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *desired_pwr_mode); +extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); + +/* UIC command interfaces for DME primitives */ +#define DME_LOCAL 0 +#define DME_PEER 1 +#define ATTR_SET_NOR 0 /* NORMAL */ +#define ATTR_SET_ST 1 /* STATIC */ + +static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, + mib_val, DME_LOCAL); +} + +static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, + mib_val, DME_LOCAL); +} + +static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, + mib_val, DME_PEER); +} + +static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, + u32 mib_val) +{ + return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, + mib_val, DME_PEER); +} + +static inline int ufshcd_dme_get(struct ufs_hba *hba, + u32 attr_sel, u32 *mib_val) +{ + return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); +} + +static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, + u32 attr_sel, u32 *mib_val) +{ + return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); +} + +static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) +{ + return (pwr_info->pwr_rx == FAST_MODE || + pwr_info->pwr_rx == FASTAUTO_MODE) && + (pwr_info->pwr_tx == FAST_MODE || + pwr_info->pwr_tx == FASTAUTO_MODE); +} + +static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) +{ + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); +} + +/* Expose Query-Request API */ +int ufshcd_query_descriptor_retry(struct ufs_hba *hba, + enum query_opcode opcode, + enum desc_idn idn, u8 index, + u8 selector, + u8 *desc_buf, int *buf_len); +int ufshcd_read_desc_param(struct ufs_hba *hba, + enum desc_idn desc_id, + int desc_index, + u8 param_offset, + u8 *param_read_buf, + u8 param_size); +int ufshcd_query_attr_retry(struct ufs_hba *hba, enum query_opcode opcode, + enum attr_idn idn, u8 index, u8 selector, + u32 *attr_val); +int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, + enum attr_idn idn, u8 index, u8 selector, u32 *attr_val); +int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, + enum flag_idn idn, u8 index, bool *flag_res); + +void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); +void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, + const struct ufs_dev_quirk *fixups); +#define SD_ASCII_STD true +#define SD_RAW false +int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, + u8 **buf, bool ascii); + +int ufshcd_hold(struct ufs_hba *hba, bool async); +void ufshcd_release(struct ufs_hba *hba); + +void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); + +void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, + int *desc_length); + +u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); + +int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); + +int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); + +int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, + struct utp_upiu_req *req_upiu, + struct utp_upiu_req *rsp_upiu, + int msgcode, + u8 *desc_buff, int *buff_len, + enum query_opcode desc_op); + +int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); +int ufshcd_suspend_prepare(struct device *dev); +int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); +void ufshcd_resume_complete(struct device *dev); + +/* Wrapper functions for safely calling variant operations */ +static inline int ufshcd_vops_init(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->init) + return hba->vops->init(hba); + + return 0; +} + +static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->phy_initialization) + return hba->vops->phy_initialization(hba); + + return 0; +} + +extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; + +int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, + const char *prefix); + +int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); +int ufshcd_write_ee_control(struct ufs_hba *hba); +int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, + const u16 *other_mask, u16 set, u16 clr); + +#endif /* End of Header */ diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h new file mode 100644 index 0000000000..f525566a08 --- /dev/null +++ b/include/ufs/ufshci.h @@ -0,0 +1,506 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal Flash Storage Host controller driver + * Copyright (C) 2011-2013 Samsung India Software Operations + * + * Authors: + * Santosh Yaraganavi + * Vinayak Holikatti + */ + +#ifndef _UFSHCI_H +#define _UFSHCI_H + +#include + +enum { + TASK_REQ_UPIU_SIZE_DWORDS = 8, + TASK_RSP_UPIU_SIZE_DWORDS = 8, + ALIGNED_UPIU_SIZE = 512, +}; + +/* UFSHCI Registers */ +enum { + REG_CONTROLLER_CAPABILITIES = 0x00, + REG_UFS_VERSION = 0x08, + REG_CONTROLLER_DEV_ID = 0x10, + REG_CONTROLLER_PROD_ID = 0x14, + REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, + REG_INTERRUPT_STATUS = 0x20, + REG_INTERRUPT_ENABLE = 0x24, + REG_CONTROLLER_STATUS = 0x30, + REG_CONTROLLER_ENABLE = 0x34, + REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, + REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, + REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, + REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, + REG_UIC_ERROR_CODE_DME = 0x48, + REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, + REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, + REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, + REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, + REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, + REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, + REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, + REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, + REG_UTP_TASK_REQ_DOOR_BELL = 0x78, + REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, + REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, + REG_UIC_COMMAND = 0x90, + REG_UIC_COMMAND_ARG_1 = 0x94, + REG_UIC_COMMAND_ARG_2 = 0x98, + REG_UIC_COMMAND_ARG_3 = 0x9C, + + UFSHCI_REG_SPACE_SIZE = 0xA0, + + REG_UFS_CCAP = 0x100, + REG_UFS_CRYPTOCAP = 0x104, + + UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, +}; + +/* Controller capability masks */ +enum { + MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, + MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, + MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, + MASK_64_ADDRESSING_SUPPORT = 0x01000000, + MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, + MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, + MASK_CRYPTO_SUPPORT = 0x10000000, +}; + +#define UFS_MASK(mask, offset) ((mask) << (offset)) + +/* UFS Version 08h */ +#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) +#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) + +/* + * Controller UFSHCI version + * - 2.x and newer use the following scheme: + * major << 8 + minor << 4 + * - 1.x has been converted to match this in + * ufshcd_get_ufs_version() + */ +static inline u32 ufshci_version(u32 major, u32 minor) +{ + return (major << 8) + (minor << 4); +} + +/* + * HCDDID - Host Controller Identification Descriptor + * - Device ID and Device Class 10h + */ +#define DEVICE_CLASS UFS_MASK(0xFFFF, 0) +#define DEVICE_ID UFS_MASK(0xFF, 24) + +/* + * HCPMID - Host Controller Identification Descriptor + * - Product/Manufacturer ID 14h + */ +#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) +#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) + +/* AHIT - Auto-Hibernate Idle Timer */ +#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) +#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) +#define UFSHCI_AHIBERN8_SCALE_FACTOR 10 +#define UFSHCI_AHIBERN8_MAX (1023 * 100000) + +/* + * IS - Interrupt Status - 20h + */ +#define UTP_TRANSFER_REQ_COMPL 0x1 +#define UIC_DME_END_PT_RESET 0x2 +#define UIC_ERROR 0x4 +#define UIC_TEST_MODE 0x8 +#define UIC_POWER_MODE 0x10 +#define UIC_HIBERNATE_EXIT 0x20 +#define UIC_HIBERNATE_ENTER 0x40 +#define UIC_LINK_LOST 0x80 +#define UIC_LINK_STARTUP 0x100 +#define UTP_TASK_REQ_COMPL 0x200 +#define UIC_COMMAND_COMPL 0x400 +#define DEVICE_FATAL_ERROR 0x800 +#define CONTROLLER_FATAL_ERROR 0x10000 +#define SYSTEM_BUS_FATAL_ERROR 0x20000 +#define CRYPTO_ENGINE_FATAL_ERROR 0x40000 + +#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ + UIC_HIBERNATE_EXIT) + +#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ + UIC_POWER_MODE) + +#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) + +#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) + +#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ + CONTROLLER_FATAL_ERROR |\ + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR |\ + UIC_LINK_LOST) + +/* HCS - Host Controller Status 30h */ +#define DEVICE_PRESENT 0x1 +#define UTP_TRANSFER_REQ_LIST_READY 0x2 +#define UTP_TASK_REQ_LIST_READY 0x4 +#define UIC_COMMAND_READY 0x8 +#define HOST_ERROR_INDICATOR 0x10 +#define DEVICE_ERROR_INDICATOR 0x20 +#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) + +#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ + UTP_TASK_REQ_LIST_READY |\ + UIC_COMMAND_READY) + +enum { + PWR_OK = 0x0, + PWR_LOCAL = 0x01, + PWR_REMOTE = 0x02, + PWR_BUSY = 0x03, + PWR_ERROR_CAP = 0x04, + PWR_FATAL_ERROR = 0x05, +}; + +/* HCE - Host Controller Enable 34h */ +#define CONTROLLER_ENABLE 0x1 +#define CONTROLLER_DISABLE 0x0 +#define CRYPTO_GENERAL_ENABLE 0x2 + +/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ +#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 +#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F +#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF +#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 + +/* UECDL - Host UIC Error Code Data Link Layer 3Ch */ +#define UIC_DATA_LINK_LAYER_ERROR 0x80000000 +#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF +#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 +#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 +#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 +#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 +#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 +#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 +#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 + +/* UECN - Host UIC Error Code Network Layer 40h */ +#define UIC_NETWORK_LAYER_ERROR 0x80000000 +#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 +#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 +#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 +#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 + +/* UECT - Host UIC Error Code Transport Layer 44h */ +#define UIC_TRANSPORT_LAYER_ERROR 0x80000000 +#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F +#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 +#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 +#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 +#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 +#define UIC_TRANSPORT_BAD_TC 0x10 +#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 +#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 + +/* UECDME - Host UIC Error Code DME 48h */ +#define UIC_DME_ERROR 0x80000000 +#define UIC_DME_ERROR_CODE_MASK 0x1 + +/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ +#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF +#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) +#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 +#define INT_AGGR_STATUS_BIT 0x100000 +#define INT_AGGR_PARAM_WRITE 0x1000000 +#define INT_AGGR_ENABLE 0x80000000 + +/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ +#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 + +/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ +#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 + +/* UICCMD - UIC Command */ +#define COMMAND_OPCODE_MASK 0xFF +#define GEN_SELECTOR_INDEX_MASK 0xFFFF + +#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) +#define RESET_LEVEL 0xFF + +#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) +#define CONFIG_RESULT_CODE_MASK 0xFF +#define GENERIC_ERROR_CODE_MASK 0xFF + +/* GenSelectorIndex calculation macros for M-PHY attributes */ +#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) +#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) + +#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ + ((sel) & 0xFFFF)) +#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) +#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) +#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) + +/* Link Status*/ +enum link_status { + UFSHCD_LINK_IS_DOWN = 1, + UFSHCD_LINK_IS_UP = 2, +}; + +/* UIC Commands */ +enum uic_cmd_dme { + UIC_CMD_DME_GET = 0x01, + UIC_CMD_DME_SET = 0x02, + UIC_CMD_DME_PEER_GET = 0x03, + UIC_CMD_DME_PEER_SET = 0x04, + UIC_CMD_DME_POWERON = 0x10, + UIC_CMD_DME_POWEROFF = 0x11, + UIC_CMD_DME_ENABLE = 0x12, + UIC_CMD_DME_RESET = 0x14, + UIC_CMD_DME_END_PT_RST = 0x15, + UIC_CMD_DME_LINK_STARTUP = 0x16, + UIC_CMD_DME_HIBER_ENTER = 0x17, + UIC_CMD_DME_HIBER_EXIT = 0x18, + UIC_CMD_DME_TEST_MODE = 0x1A, +}; + +/* UIC Config result code / Generic error code */ +enum { + UIC_CMD_RESULT_SUCCESS = 0x00, + UIC_CMD_RESULT_INVALID_ATTR = 0x01, + UIC_CMD_RESULT_FAILURE = 0x01, + UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, + UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, + UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, + UIC_CMD_RESULT_BAD_INDEX = 0x05, + UIC_CMD_RESULT_LOCKED_ATTR = 0x06, + UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, + UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, + UIC_CMD_RESULT_BUSY = 0x09, + UIC_CMD_RESULT_DME_FAILURE = 0x0A, +}; + +#define MASK_UIC_COMMAND_RESULT 0xFF + +#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) +#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) + +/* Interrupt disable masks */ +enum { + /* Interrupt disable mask for UFSHCI v1.0 */ + INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, + INTERRUPT_MASK_RW_VER_10 = 0x30000, + + /* Interrupt disable mask for UFSHCI v1.1 */ + INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, + + /* Interrupt disable mask for UFSHCI v2.1 */ + INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, +}; + +/* CCAP - Crypto Capability 100h */ +union ufs_crypto_capabilities { + __le32 reg_val; + struct { + u8 num_crypto_cap; + u8 config_count; + u8 reserved; + u8 config_array_ptr; + }; +}; + +enum ufs_crypto_key_size { + UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, + UFS_CRYPTO_KEY_SIZE_128 = 0x1, + UFS_CRYPTO_KEY_SIZE_192 = 0x2, + UFS_CRYPTO_KEY_SIZE_256 = 0x3, + UFS_CRYPTO_KEY_SIZE_512 = 0x4, +}; + +enum ufs_crypto_alg { + UFS_CRYPTO_ALG_AES_XTS = 0x0, + UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, + UFS_CRYPTO_ALG_AES_ECB = 0x2, + UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, +}; + +/* x-CRYPTOCAP - Crypto Capability X */ +union ufs_crypto_cap_entry { + __le32 reg_val; + struct { + u8 algorithm_id; + u8 sdus_mask; /* Supported data unit size mask */ + u8 key_size; + u8 reserved; + }; +}; + +#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) +#define UFS_CRYPTO_KEY_MAX_SIZE 64 +/* x-CRYPTOCFG - Crypto Configuration X */ +union ufs_crypto_cfg_entry { + __le32 reg_val[32]; + struct { + u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; + u8 data_unit_size; + u8 crypto_cap_idx; + u8 reserved_1; + u8 config_enable; + u8 reserved_multi_host; + u8 reserved_2; + u8 vsb[2]; + u8 reserved_3[56]; + }; +}; + +/* + * Request Descriptor Definitions + */ + +/* Transfer request command type */ +enum { + UTP_CMD_TYPE_SCSI = 0x0, + UTP_CMD_TYPE_UFS = 0x1, + UTP_CMD_TYPE_DEV_MANAGE = 0x2, +}; + +/* To accommodate UFS2.0 required Command type */ +enum { + UTP_CMD_TYPE_UFS_STORAGE = 0x1, +}; + +enum { + UTP_SCSI_COMMAND = 0x00000000, + UTP_NATIVE_UFS_COMMAND = 0x10000000, + UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, + UTP_REQ_DESC_INT_CMD = 0x01000000, + UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, +}; + +/* UTP Transfer Request Data Direction (DD) */ +enum { + UTP_NO_DATA_TRANSFER = 0x00000000, + UTP_HOST_TO_DEVICE = 0x02000000, + UTP_DEVICE_TO_HOST = 0x04000000, +}; + +/* Overall command status values */ +enum utp_ocs { + OCS_SUCCESS = 0x0, + OCS_INVALID_CMD_TABLE_ATTR = 0x1, + OCS_INVALID_PRDT_ATTR = 0x2, + OCS_MISMATCH_DATA_BUF_SIZE = 0x3, + OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, + OCS_PEER_COMM_FAILURE = 0x5, + OCS_ABORTED = 0x6, + OCS_FATAL_ERROR = 0x7, + OCS_DEVICE_FATAL_ERROR = 0x8, + OCS_INVALID_CRYPTO_CONFIG = 0x9, + OCS_GENERAL_CRYPTO_ERROR = 0xA, + OCS_INVALID_COMMAND_STATUS = 0x0F, +}; + +enum { + MASK_OCS = 0x0F, +}; + +/* The maximum length of the data byte count field in the PRDT is 256KB */ +#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) +/* The granularity of the data byte count field in the PRDT is 32-bit */ +#define PRDT_DATA_BYTE_COUNT_PAD 4 + +/** + * struct ufshcd_sg_entry - UFSHCI PRD Entry + * @addr: Physical address; DW-0 and DW-1. + * @reserved: Reserved for future use DW-2 + * @size: size of physical segment DW-3 + */ +struct ufshcd_sg_entry { + __le64 addr; + __le32 reserved; + __le32 size; +}; + +/** + * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) + * @command_upiu: Command UPIU Frame address + * @response_upiu: Response UPIU Frame address + * @prd_table: Physical Region Descriptor + */ +struct utp_transfer_cmd_desc { + u8 command_upiu[ALIGNED_UPIU_SIZE]; + u8 response_upiu[ALIGNED_UPIU_SIZE]; + struct ufshcd_sg_entry prd_table[SG_ALL]; +}; + +/** + * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD + * @dword0: Descriptor Header DW0 + * @dword1: Descriptor Header DW1 + * @dword2: Descriptor Header DW2 + * @dword3: Descriptor Header DW3 + */ +struct request_desc_header { + __le32 dword_0; + __le32 dword_1; + __le32 dword_2; + __le32 dword_3; +}; + +/** + * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) + * @header: UTRD header DW-0 to DW-3 + * @command_desc_base_addr_lo: UCD base address low DW-4 + * @command_desc_base_addr_hi: UCD base address high DW-5 + * @response_upiu_length: response UPIU length DW-6 + * @response_upiu_offset: response UPIU offset DW-6 + * @prd_table_length: Physical region descriptor length DW-7 + * @prd_table_offset: Physical region descriptor offset DW-7 + */ +struct utp_transfer_req_desc { + + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-5*/ + __le32 command_desc_base_addr_lo; + __le32 command_desc_base_addr_hi; + + /* DW 6 */ + __le16 response_upiu_length; + __le16 response_upiu_offset; + + /* DW 7 */ + __le16 prd_table_length; + __le16 prd_table_offset; +}; + +/* + * UTMRD structure. + */ +struct utp_task_req_desc { + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-11 - Task request UPIU structure */ + struct { + struct utp_upiu_header req_header; + __be32 input_param1; + __be32 input_param2; + __be32 input_param3; + __be32 __reserved1[2]; + } upiu_req; + + /* DW 12-19 - Task Management Response UPIU structure */ + struct { + struct utp_upiu_header rsp_header; + __be32 output_param1; + __be32 output_param2; + __be32 __reserved2[3]; + } upiu_rsp; +}; + +#endif /* End of Header */ diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h new file mode 100644 index 0000000000..6c553f98fe --- /dev/null +++ b/include/ufs/unipro.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + */ + +#ifndef _UNIPRO_H_ +#define _UNIPRO_H_ + +/* + * M-TX Configuration Attributes + */ +#define TX_HIBERN8TIME_CAPABILITY 0x000F +#define TX_MODE 0x0021 +#define TX_HSRATE_SERIES 0x0022 +#define TX_HSGEAR 0x0023 +#define TX_PWMGEAR 0x0024 +#define TX_AMPLITUDE 0x0025 +#define TX_HS_SLEWRATE 0x0026 +#define TX_SYNC_SOURCE 0x0027 +#define TX_HS_SYNC_LENGTH 0x0028 +#define TX_HS_PREPARE_LENGTH 0x0029 +#define TX_LS_PREPARE_LENGTH 0x002A +#define TX_HIBERN8_CONTROL 0x002B +#define TX_LCC_ENABLE 0x002C +#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D +#define TX_BYPASS_8B10B_ENABLE 0x002E +#define TX_DRIVER_POLARITY 0x002F +#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 +#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 +#define TX_LCC_SEQUENCER 0x0032 +#define TX_MIN_ACTIVATETIME 0x0033 +#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 +#define TX_REFCLKFREQ 0x00EB +#define TX_CFGCLKFREQVAL 0x00EC +#define CFGEXTRATTR 0x00F0 +#define DITHERCTRL2 0x00F1 + +/* + * M-RX Configuration Attributes + */ +#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B +#define RX_HS_G1_PREP_LENGTH_CAP 0x008C +#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +#define RX_HIBERN8TIME_CAPABILITY 0x0092 +#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 +#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 +#define RX_HS_G2_PREP_LENGTH_CAP 0x0096 +#define RX_HS_G3_PREP_LENGTH_CAP 0x0097 +#define RX_ADV_GRANULARITY_CAP 0x0098 +#define RX_HIBERN8TIME_CAP 0x0092 +#define RX_ADV_HIBERN8TIME_CAP 0x0099 +#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A +#define RX_MODE 0x00A1 +#define RX_HSRATE_SERIES 0x00A2 +#define RX_HSGEAR 0x00A3 +#define RX_PWMGEAR 0x00A4 +#define RX_LS_TERMINATED_ENABLE 0x00A5 +#define RX_HS_UNTERMINATED_ENABLE 0x00A6 +#define RX_ENTER_HIBERN8 0x00A7 +#define RX_BYPASS_8B10B_ENABLE 0x00A8 +#define RX_TERMINATION_FORCE_ENABLE 0x00A9 +#define RXCALCTRL 0x00B4 +#define RXSQCTRL 0x00B5 +#define CFGRXCDR8 0x00BA +#define CFGRXOVR8 0x00BD +#define CFGRXOVR6 0x00BF +#define RXDIRECTCTRL2 0x00C7 +#define CFGRXOVR4 0x00E9 +#define RX_REFCLKFREQ 0x00EB +#define RX_CFGCLKFREQVAL 0x00EC +#define CFGWIDEINLN 0x00F0 +#define ENARXDIRECTCFG4 0x00F2 +#define ENARXDIRECTCFG3 0x00F3 +#define ENARXDIRECTCFG2 0x00F4 + + +#define is_mphy_tx_attr(attr) (attr < RX_MODE) +#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) +#define SYNC_LEN_FINE(x) ((x) & 0x3F) +#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) +#define PREP_LEN(x) ((x) & 0xF) + +#define RX_MIN_ACTIVATETIME_UNIT_US 100 +#define HIBERN8TIME_UNIT_US 100 + +/* + * Common Block Attributes + */ +#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) +#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) +#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) +#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) +#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) +#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) +#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) +#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) +#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) +#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) + +#define UNIPRO_CB_OFFSET(x) (0x8000 | x) + +/* + * PHY Adapter attributes + */ +#define PA_PHY_TYPE 0x1500 +#define PA_AVAILTXDATALANES 0x1520 +#define PA_MAXTXSPEEDFAST 0x1521 +#define PA_MAXTXSPEEDSLOW 0x1522 +#define PA_MAXRXSPEEDFAST 0x1541 +#define PA_MAXRXSPEEDSLOW 0x1542 +#define PA_TXLINKSTARTUPHS 0x1544 +#define PA_AVAILRXDATALANES 0x1540 +#define PA_MINRXTRAILINGCLOCKS 0x1543 +#define PA_LOCAL_TX_LCC_ENABLE 0x155E +#define PA_ACTIVETXDATALANES 0x1560 +#define PA_CONNECTEDTXDATALANES 0x1561 +#define PA_TXFORCECLOCK 0x1562 +#define PA_TXPWRMODE 0x1563 +#define PA_TXTRAILINGCLOCKS 0x1564 +#define PA_TXSPEEDFAST 0x1565 +#define PA_TXSPEEDSLOW 0x1566 +#define PA_TXPWRSTATUS 0x1567 +#define PA_TXGEAR 0x1568 +#define PA_TXTERMINATION 0x1569 +#define PA_HSSERIES 0x156A +#define PA_LEGACYDPHYESCDL 0x1570 +#define PA_PWRMODE 0x1571 +#define PA_ACTIVERXDATALANES 0x1580 +#define PA_CONNECTEDRXDATALANES 0x1581 +#define PA_RXPWRSTATUS 0x1582 +#define PA_RXGEAR 0x1583 +#define PA_RXTERMINATION 0x1584 +#define PA_MAXRXPWMGEAR 0x1586 +#define PA_MAXRXHSGEAR 0x1587 +#define PA_PACPREQTIMEOUT 0x1590 +#define PA_PACPREQEOBTIMEOUT 0x1591 +#define PA_REMOTEVERINFO 0x15A0 +#define PA_LOGICALLANEMAP 0x15A1 +#define PA_SLEEPNOCONFIGTIME 0x15A2 +#define PA_STALLNOCONFIGTIME 0x15A3 +#define PA_SAVECONFIGTIME 0x15A4 +#define PA_RXHSUNTERMCAP 0x15A5 +#define PA_RXLSTERMCAP 0x15A6 +#define PA_GRANULARITY 0x15AA +#define PA_HIBERN8TIME 0x15A7 +#define PA_LOCALVERINFO 0x15A9 +#define PA_GRANULARITY 0x15AA +#define PA_TACTIVATE 0x15A8 +#define PA_PWRMODEUSERDATA0 0x15B0 +#define PA_PWRMODEUSERDATA1 0x15B1 +#define PA_PWRMODEUSERDATA2 0x15B2 +#define PA_PWRMODEUSERDATA3 0x15B3 +#define PA_PWRMODEUSERDATA4 0x15B4 +#define PA_PWRMODEUSERDATA5 0x15B5 +#define PA_PWRMODEUSERDATA6 0x15B6 +#define PA_PWRMODEUSERDATA7 0x15B7 +#define PA_PWRMODEUSERDATA8 0x15B8 +#define PA_PWRMODEUSERDATA9 0x15B9 +#define PA_PWRMODEUSERDATA10 0x15BA +#define PA_PWRMODEUSERDATA11 0x15BB +#define PA_PACPFRAMECOUNT 0x15C0 +#define PA_PACPERRORCOUNT 0x15C1 +#define PA_PHYTESTCONTROL 0x15C2 +#define PA_TXHSADAPTTYPE 0x15D4 + +/* Adpat type for PA_TXHSADAPTTYPE attribute */ +#define PA_REFRESH_ADAPT 0x00 +#define PA_INITIAL_ADAPT 0x01 +#define PA_NO_ADAPT 0x03 + +#define PA_TACTIVATE_TIME_UNIT_US 10 +#define PA_HIBERN8_TIME_UNIT_US 100 + +/*Other attributes*/ +#define VS_POWERSTATE 0xD083 +#define VS_MPHYCFGUPDT 0xD085 +#define VS_DEBUGOMC 0xD09E + +#define PA_GRANULARITY_MIN_VAL 1 +#define PA_GRANULARITY_MAX_VAL 6 + +/* PHY Adapter Protocol Constants */ +#define PA_MAXDATALANES 4 + +#define DL_FC0ProtectionTimeOutVal_Default 8191 +#define DL_TC0ReplayTimeOutVal_Default 65535 +#define DL_AFC0ReqTimeOutVal_Default 32767 +#define DL_FC1ProtectionTimeOutVal_Default 8191 +#define DL_TC1ReplayTimeOutVal_Default 65535 +#define DL_AFC1ReqTimeOutVal_Default 32767 + +#define DME_LocalFC0ProtectionTimeOutVal 0xD041 +#define DME_LocalTC0ReplayTimeOutVal 0xD042 +#define DME_LocalAFC0ReqTimeOutVal 0xD043 + +/* PA power modes */ +enum { + FAST_MODE = 1, + SLOW_MODE = 2, + FASTAUTO_MODE = 4, + SLOWAUTO_MODE = 5, + UNCHANGED = 7, +}; + +#define PWRMODE_MASK 0xF +#define PWRMODE_RX_OFFSET 4 + +/* PA TX/RX Frequency Series */ +enum { + PA_HS_MODE_A = 1, + PA_HS_MODE_B = 2, +}; + +enum ufs_pwm_gear_tag { + UFS_PWM_DONT_CHANGE, /* Don't change Gear */ + UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ + UFS_PWM_G2, /* PWM Gear 2 */ + UFS_PWM_G3, /* PWM Gear 3 */ + UFS_PWM_G4, /* PWM Gear 4 */ + UFS_PWM_G5, /* PWM Gear 5 */ + UFS_PWM_G6, /* PWM Gear 6 */ + UFS_PWM_G7, /* PWM Gear 7 */ +}; + +enum ufs_hs_gear_tag { + UFS_HS_DONT_CHANGE, /* Don't change Gear */ + UFS_HS_G1, /* HS Gear 1 (default for reset) */ + UFS_HS_G2, /* HS Gear 2 */ + UFS_HS_G3, /* HS Gear 3 */ + UFS_HS_G4, /* HS Gear 4 */ + UFS_HS_G5 /* HS Gear 5 */ +}; + +enum ufs_unipro_ver { + UFS_UNIPRO_VER_RESERVED = 0, + UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ + UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ + UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ + UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ + UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ + UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ + /* UniPro version field mask in PA_LOCALVERINFO */ + UFS_UNIPRO_VER_MASK = 0xF, +}; + +/* + * Data Link Layer Attributes + */ +#define DL_TXPREEMPTIONCAP 0x2000 +#define DL_TC0TXMAXSDUSIZE 0x2001 +#define DL_TC0RXINITCREDITVAL 0x2002 +#define DL_TC1TXMAXSDUSIZE 0x2003 +#define DL_TC1RXINITCREDITVAL 0x2004 +#define DL_TC0TXBUFFERSIZE 0x2005 +#define DL_TC1TXBUFFERSIZE 0x2006 +#define DL_TC0TXFCTHRESHOLD 0x2040 +#define DL_FC0PROTTIMEOUTVAL 0x2041 +#define DL_TC0REPLAYTIMEOUTVAL 0x2042 +#define DL_AFC0REQTIMEOUTVAL 0x2043 +#define DL_AFC0CREDITTHRESHOLD 0x2044 +#define DL_TC0OUTACKTHRESHOLD 0x2045 +#define DL_PEERTC0PRESENT 0x2046 +#define DL_PEERTC0RXINITCREVAL 0x2047 +#define DL_TC1TXFCTHRESHOLD 0x2060 +#define DL_FC1PROTTIMEOUTVAL 0x2061 +#define DL_TC1REPLAYTIMEOUTVAL 0x2062 +#define DL_AFC1REQTIMEOUTVAL 0x2063 +#define DL_AFC1CREDITTHRESHOLD 0x2064 +#define DL_TC1OUTACKTHRESHOLD 0x2065 +#define DL_PEERTC1PRESENT 0x2066 +#define DL_PEERTC1RXINITCREVAL 0x2067 + +/* + * Network Layer Attributes + */ +#define N_DEVICEID 0x3000 +#define N_DEVICEID_VALID 0x3001 +#define N_TC0TXMAXSDUSIZE 0x3020 +#define N_TC1TXMAXSDUSIZE 0x3021 + +/* + * Transport Layer Attributes + */ +#define T_NUMCPORTS 0x4000 +#define T_NUMTESTFEATURES 0x4001 +#define T_CONNECTIONSTATE 0x4020 +#define T_PEERDEVICEID 0x4021 +#define T_PEERCPORTID 0x4022 +#define T_TRAFFICCLASS 0x4023 +#define T_PROTOCOLID 0x4024 +#define T_CPORTFLAGS 0x4025 +#define T_TXTOKENVALUE 0x4026 +#define T_RXTOKENVALUE 0x4027 +#define T_LOCALBUFFERSPACE 0x4028 +#define T_PEERBUFFERSPACE 0x4029 +#define T_CREDITSTOSEND 0x402A +#define T_CPORTMODE 0x402B +#define T_TC0TXMAXSDUSIZE 0x4060 +#define T_TC1TXMAXSDUSIZE 0x4061 + +/* CPort setting */ +#define E2EFC_ON (1 << 0) +#define E2EFC_OFF (0 << 0) +#define CSD_N_ON (0 << 1) +#define CSD_N_OFF (1 << 1) +#define CSV_N_ON (0 << 2) +#define CSV_N_OFF (1 << 2) +#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF) + +/* CPort connection state */ +enum { + CPORT_IDLE = 0, + CPORT_CONNECTED, +}; + +#endif /* _UNIPRO_H_ */ diff --git a/include/xen/arm/xen-ops.h b/include/xen/arm/xen-ops.h new file mode 100644 index 0000000000..b0766a6603 --- /dev/null +++ b/include/xen/arm/xen-ops.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_ARM_XEN_OPS_H +#define _ASM_ARM_XEN_OPS_H + +#include +#include + +static inline void xen_setup_dma_ops(struct device *dev) +{ +#ifdef CONFIG_XEN + if (xen_is_grant_dma_device(dev)) + xen_grant_setup_dma_ops(dev); + else if (xen_swiotlb_detect()) + dev->dma_ops = &xen_swiotlb_dma_ops; +#endif +} + +#endif /* _ASM_ARM_XEN_OPS_H */ diff --git a/rdp-acceleraed/.github/workflows/c-cpp.yml b/rdp-acceleraed/.github/workflows/c-cpp.yml deleted file mode 100644 index e3233268f7..0000000000 --- a/rdp-acceleraed/.github/workflows/c-cpp.yml +++ /dev/null @@ -1,23 +0,0 @@ -name: C/C++ CI - -on: - push: - branches: [ master ] - pull_request: - branches: [ master ] - -jobs: - build: - - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v2 - - name: configure - run: ./configure - - name: make - run: make - - name: make check - run: make check - - name: make distcheck - run: make distcheck diff --git a/rdp-acceleraed/.gitignore b/rdp-acceleraed/.gitignore deleted file mode 100644 index 61fa5b3604..0000000000 --- a/rdp-acceleraed/.gitignore +++ /dev/null @@ -1,18 +0,0 @@ -# Compiled Object files -*.slo -*.lo -*.o - -# Compiled Dynamic libraries -*.so -*.dylib - -# Compiled Static libraries -*.lai -*.la -*.a -/Server/build -/nbproject/private/ -/nbproject -/Server/config.h -/ffmpeg diff --git a/rdp-acceleraed/LICENSE b/rdp-acceleraed/LICENSE deleted file mode 100644 index 7e908c47fa..0000000000 --- a/rdp-acceleraed/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -The MIT License (MIT) - -Copyright (c) 2014 jean343 - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. \ No newline at end of file diff --git a/rdp-acceleraed/README.md b/rdp-acceleraed/README.md deleted file mode 100644 index 47da2b1fd1..0000000000 --- a/rdp-acceleraed/README.md +++ /dev/null @@ -1,71 +0,0 @@ -RPI-GPU-rdpClient -================= - -Video on youtube: http://youtu.be/3HJuHhiXxuE - -Hardware accelerated raspberry pi client for windows PC. -It is more a proof-of-concept to show that OpenMAX can be used as a RDP viewer rather than a finished product. -There is no authentication, use at your own risk. - -It uses a NVIDIA graphic card to encode H.264 video, and OpenMAX to display the video. It can achieve 1080P 60FPS RDP on a RPI with a relatively low latency of ~200ms on two monitors. -When the GPU is not accessible on the server, it falls back to CPU encoding at a lower FPS, around 10FPS depending on the CPU. -It uses DXGI for accelerated desktop capture in Windows 8 -It can work in a Virtual machine in order to be a true thin client. - -### To compile the client on the Raspberry PI ### - -It needs the following packages. I started on a clean version of the Raspberian OS. - -``` -sudo apt-get install cmake -sudo apt-get install libboost-thread-dev libboost-system-dev -sudo apt-get install libx11-dev -``` - -To compile ilclient: -``` -cd /opt/vc/src/hello_pi -sudo ./rebuild.sh -``` - -To compile the RDP client: -``` -git clone https://github.com/jean343/RPI-GPU-rdpClient.git -cd RPI-GPU-rdpClient/RPI-Client -mkdir build && cd build/ -cmake .. -make -``` - -### To run the client ### -./client - -###To compile the server in windows### -- See the guide at https://github.com/jean343/RPI-GPU-rdpClient/blob/master/WindowsCompileGuide.md -- Optional, FFMPEG for a CPU fallback if the graphic card is unavailable - - Download FFMPEG from http://ffmpeg.zeranoe.com/builds/, need the dev and shared - - Set FFMPEG_ROOT to the root of FFMPEG dev folder - - Add the bin folder of the shared zip to your path, or copy the DLLs - -### To run the server ### -./server monitor 0 port 8080 - -### Contribute ### - -Want to be part of the project? Great! All are welcome! We will get there quicker together :) -Whether you find a bug, have a great feature request feel free to get in touch. - -### Known issues and limitations ### -- There is no audio -- There is no authentication, use only in a local LAN or under a VPN. -- The software falls back to CPU encoding in a Virtual Machine, it is fast as it uses the x264 superfast preset, but the H.264 quality is reduced. - -### NOTES ### -From https://github.com/Hexxeh/rpi-update, update your pi: -``` -sudo rpi-update -``` -Update software: -``` -sudo apt-get update && sudo apt-get upgrade -``` diff --git a/rdp-acceleraed/RPI-Client/CMakeLists.txt b/rdp-acceleraed/RPI-Client/CMakeLists.txt deleted file mode 100644 index b9cc643851..0000000000 --- a/rdp-acceleraed/RPI-Client/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -cmake_minimum_required(VERSION 2.8) -project( client ) - -FIND_PACKAGE( Boost REQUIRED COMPONENTS thread ) - -include_directories("/opt/vc/include/interface/vcos/pthreads/;/opt/vc/include/interface/vmcs_host/linux") - - -add_executable( client client.cpp ) -include_directories(/opt/vc/include /opt/vc/src/hello_pi/libs/ilclient/ ${Boost_INCLUDE_DIR}) -target_link_libraries( client X11 /opt/vc/src/hello_pi/libs/ilclient/libilclient.a boost_system /opt/vc/lib/libbcm_host.so /opt/vc/lib/libopenmaxil.so /opt/vc/lib/libvcos.so /opt/vc/lib/libGLESv2.so /opt/vc/lib/libEGL.so ${Boost_LIBRARIES} ) \ No newline at end of file diff --git a/rdp-acceleraed/RPI-Client/client.cpp b/rdp-acceleraed/RPI-Client/client.cpp deleted file mode 100644 index 358f940e98..0000000000 --- a/rdp-acceleraed/RPI-Client/client.cpp +++ /dev/null @@ -1,371 +0,0 @@ -/* -Copyright (c) 2012, Broadcom Europe Ltd -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the copyright holder nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -// -// Copyright (c) 2003-2013 Christopher M. Kohlhoff (chris at kohlhoff dot com) -// -// Distributed under the Boost Software License, Version 1.0. (See accompanying -// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) -// - -#include -#include -#include - -#include "bcm_host.h" - -extern "C" { - #include "ilclient.h" -} - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mouse.h" - -using boost::asio::ip::tcp; -using namespace std; - -enum { - max_length = 1024 -}; - -static int start_decode_video(char* host, char* port) { - OMX_VIDEO_PARAM_PORTFORMATTYPE format; - OMX_TIME_CONFIG_CLOCKSTATETYPE cstate; - COMPONENT_T *video_decode = NULL, *video_scheduler = NULL, *video_render = NULL, *clock = NULL; - COMPONENT_T * list[5]; - TUNNEL_T tunnel[4]; - ILCLIENT_T *client; - int status = 0; - unsigned int data_len = 0; - - memset(list, 0, sizeof (list)); - memset(tunnel, 0, sizeof (tunnel)); - - - if ((client = ilclient_init()) == NULL) { - return -3; - } - - if (OMX_Init() != OMX_ErrorNone) { - ilclient_destroy(client); - return -4; - } - - // create video_decode - if (ilclient_create_component(client, &video_decode, "video_decode", (ILCLIENT_CREATE_FLAGS_T)(ILCLIENT_DISABLE_ALL_PORTS | ILCLIENT_ENABLE_INPUT_BUFFERS)) != 0) - status = -14; - list[0] = video_decode; - - // create video_render - if (status == 0 && ilclient_create_component(client, &video_render, "video_render", ILCLIENT_DISABLE_ALL_PORTS) != 0) - status = -14; - list[1] = video_render; - - // create clock - if (status == 0 && ilclient_create_component(client, &clock, "clock", ILCLIENT_DISABLE_ALL_PORTS) != 0) - status = -14; - list[2] = clock; - - memset(&cstate, 0, sizeof (cstate)); - cstate.nSize = sizeof (cstate); - cstate.nVersion.nVersion = OMX_VERSION; - cstate.eState = OMX_TIME_ClockStateWaitingForStartTime; - cstate.nWaitMask = 1; - if (clock != NULL && OMX_SetParameter(ILC_GET_HANDLE(clock), OMX_IndexConfigTimeClockState, &cstate) != OMX_ErrorNone) - status = -13; - - // create video_scheduler - if (status == 0 && ilclient_create_component(client, &video_scheduler, "video_scheduler", ILCLIENT_DISABLE_ALL_PORTS) != 0) - status = -14; - list[3] = video_scheduler; - - set_tunnel(tunnel, video_decode, 131, video_scheduler, 10); - set_tunnel(tunnel + 1, video_scheduler, 11, video_render, 90); - set_tunnel(tunnel + 2, clock, 80, video_scheduler, 12); - - // setup clock tunnel first - if (status == 0 && ilclient_setup_tunnel(tunnel + 2, 0, 0) != 0) - status = -15; - else - ilclient_change_component_state(clock, OMX_StateExecuting); - - if (status == 0) - ilclient_change_component_state(video_decode, OMX_StateIdle); - - memset(&format, 0, sizeof (OMX_VIDEO_PARAM_PORTFORMATTYPE)); - format.nSize = sizeof (OMX_VIDEO_PARAM_PORTFORMATTYPE); - format.nVersion.nVersion = OMX_VERSION; - format.nPortIndex = 130; - format.eCompressionFormat = OMX_VIDEO_CodingAVC; - - if (status == 0 && - OMX_SetParameter(ILC_GET_HANDLE(video_decode), OMX_IndexParamVideoPortFormat, &format) == OMX_ErrorNone && - ilclient_enable_port_buffers(video_decode, 130, NULL, NULL, NULL) == 0) { - OMX_BUFFERHEADERTYPE *buf; - int port_settings_changed = 0; - int first_packet = 1; - - ilclient_change_component_state(video_decode, OMX_StateExecuting); - - - boost::asio::io_service io_service; - - tcp::resolver resolver(io_service); - tcp::resolver::query query(tcp::v4(), host, port); - tcp::resolver::iterator iterator = resolver.resolve(query); - - tcp::socket s(io_service); - boost::asio::connect(s, iterator); - s.set_option(tcp::no_delay(true)); - - boost::asio::write(s, boost::asio::buffer("a", 2)); - - while ((buf = ilclient_get_input_buffer(video_decode, 130, 1)) != NULL) { - // feed data and wait until we get port settings changed - unsigned char *dest = buf->pBuffer; - - int bufferSize = std::min((int)buf->nAllocLen, 10 * 1024); - data_len += boost::asio::read(s, boost::asio::buffer(dest, bufferSize)); - - if (port_settings_changed == 0 && - ((data_len > 0 && ilclient_remove_event(video_decode, OMX_EventPortSettingsChanged, 131, 0, 0, 1) == 0) || - (data_len == 0 && ilclient_wait_for_event(video_decode, OMX_EventPortSettingsChanged, 131, 0, 0, 1, - ILCLIENT_EVENT_ERROR | ILCLIENT_PARAMETER_CHANGED, 10000) == 0))) { - port_settings_changed = 1; - - if (ilclient_setup_tunnel(tunnel, 0, 0) != 0) { - status = -7; - break; - } - - ilclient_change_component_state(video_scheduler, OMX_StateExecuting); - - // now setup tunnel to video_render - if (ilclient_setup_tunnel(tunnel + 1, 0, 1000) != 0) { - status = -12; - break; - } - - ilclient_change_component_state(video_render, OMX_StateExecuting); - } - if (!data_len) - break; - - buf->nFilledLen = data_len; - data_len = 0; - - buf->nOffset = 0; - if (first_packet) { - buf->nFlags = OMX_BUFFERFLAG_STARTTIME; - first_packet = 0; - } else - buf->nFlags = OMX_BUFFERFLAG_TIME_UNKNOWN; - - if (OMX_EmptyThisBuffer(ILC_GET_HANDLE(video_decode), buf) != OMX_ErrorNone) { - status = -6; - break; - } - } - - buf->nFilledLen = 0; - buf->nFlags = OMX_BUFFERFLAG_TIME_UNKNOWN | OMX_BUFFERFLAG_EOS; - - if (OMX_EmptyThisBuffer(ILC_GET_HANDLE(video_decode), buf) != OMX_ErrorNone) - status = -20; - - // wait for EOS from render - ilclient_wait_for_event(video_render, OMX_EventBufferFlag, 90, 0, OMX_BUFFERFLAG_EOS, 0, - ILCLIENT_BUFFER_FLAG_EOS, 10000); - - // need to flush the renderer to allow video_decode to disable its input port - ilclient_flush_tunnels(tunnel, 0); - - ilclient_disable_port_buffers(video_decode, 130, NULL, NULL, NULL); - } - - ilclient_disable_tunnel(tunnel); - ilclient_disable_tunnel(tunnel + 1); - ilclient_disable_tunnel(tunnel + 2); - ilclient_teardown_tunnels(tunnel); - - ilclient_state_transition(list, OMX_StateIdle); - ilclient_state_transition(list, OMX_StateLoaded); - - ilclient_cleanup_components(list); - - OMX_Deinit(); - - ilclient_destroy(client); - return status; -} - -char *key_name[] = { - "first", - "second (or middle)", - "third" -}; - -struct SendStruct { - int type; - int x; - int y; - int button; - int keycode; -}; - -static void FillRect( void *image, int pitch, int x, int y, int w, int h, int val ) -{ - int row; - int col; - - uint32_t *line = (uint32_t *)image + y * (pitch>>2) + x; - - for ( row = 0; row < h; row++ ) - { - for ( col = 0; col < w; col++ ) - { - line[col] = val; - } - line += (pitch>>2); - } -} - -void mouseKeyboardThread(char* host, char* port) -{ - boost::asio::io_service io_service; - - tcp::resolver resolver(io_service); - tcp::resolver::query query(tcp::v4(), host, port); - tcp::resolver::iterator iterator = resolver.resolve(query); - - tcp::socket s(io_service); - boost::asio::connect(s, iterator); - s.set_option(tcp::no_delay(true)); - - boost::asio::write(s, boost::asio::buffer("b", 2)); - - Display *display; - XEvent xevent; - Window window; - - if( (display = XOpenDisplay(NULL)) == NULL ) - return; - - - window = DefaultRootWindow(display); - XAllowEvents(display, AsyncBoth, CurrentTime); - - XGrabPointer(display, - window, - 1, - PointerMotionMask | ButtonPressMask | ButtonReleaseMask , - GrabModeAsync, - GrabModeAsync, - None, - None, - CurrentTime); - - XGrabKeyboard(display, window, false, GrabModeAsync, GrabModeAsync, CurrentTime); - - Mouse mouse; - - while(1) { - XNextEvent(display, &xevent); - int mykey; - SendStruct send; - SendStruct* sendPtr = &send; - switch (xevent.type) { - case MotionNotify: - send.type = 0; - send.x = xevent.xmotion.x_root; - send.y = xevent.xmotion.y_root; - - mouse.move(send.x, send.y); - - //printf("Mouse move : [%d, %d]\n", xevent.xmotion.x_root, xevent.xmotion.y_root); - break; - case ButtonPress: - send.type = 1; - send.button = xevent.xbutton.button; - //printf("Button pressed : %s\n", key_name[xevent.xbutton.button - 1]); - break; - case ButtonRelease: - send.type = 2; - send.button = xevent.xbutton.button; - //printf("Button released : %s\n", key_name[xevent.xbutton.button - 1]); - break; - case KeyPress: - mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0); - //printf("KeyPress : %s, %d\n", XKeysymToString(mykey), mykey); - - send.type = 3; - send.keycode = mykey; - - if (xevent.xkey.keycode == 27 || xevent.xkey.keycode == 9) { - return; - } - break; - case KeyRelease: - mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0); - - send.type = 4; - send.keycode = mykey; - - //printf("KeyRelease : %s, %d\n", XKeysymToString(mykey), mykey); - break; - } - boost::asio::write(s, boost::asio::buffer(sendPtr, sizeof(SendStruct))); - } - - mouse.close(); -} - -int main(int argc, char **argv) { - std::cout << "Version 0.9" << endl; - - if (argc != 3) - { - std::cerr << "Usage: ./client \n"; - return 1; - } - - char* host = argv[1]; - char* port = argv[2]; - - bcm_host_init(); - - boost::thread t(&mouseKeyboardThread, host, port); - start_decode_video(host, port); - t.join(); -} \ No newline at end of file diff --git a/rdp-acceleraed/RPI-Client/events.cpp b/rdp-acceleraed/RPI-Client/events.cpp deleted file mode 100644 index 25353a30fe..0000000000 --- a/rdp-acceleraed/RPI-Client/events.cpp +++ /dev/null @@ -1,71 +0,0 @@ -#include -#include -#include - -char *key_name[] = { - "first", - "second (or middle)", - "third" -}; - -struct SendStruct { - int type; - int x; - int y; -}; - -int main(int argc, char **argv) -{ - Display *display; - XEvent xevent; - Window window; - - if( (display = XOpenDisplay(NULL)) == NULL ) - return -1; - - - window = DefaultRootWindow(display); - XAllowEvents(display, AsyncBoth, CurrentTime); - - XGrabPointer(display, - window, - 1, - PointerMotionMask | ButtonPressMask | ButtonReleaseMask , - GrabModeAsync, - GrabModeAsync, - None, - None, - CurrentTime); - - XGrabKeyboard(display, window, false, GrabModeAsync, GrabModeAsync, CurrentTime); - - while(1) { - XNextEvent(display, &xevent); - int mykey; - switch (xevent.type) { - case MotionNotify: - printf("Mouse move : [%d, %d]\n", xevent.xmotion.x_root, xevent.xmotion.y_root); - break; - case ButtonPress: - printf("Button pressed : %s, %d\n", key_name[xevent.xbutton.button - 1], xevent.xbutton.button); - break; - case ButtonRelease: - printf("Button released : %s, %d\n", key_name[xevent.xbutton.button - 1], xevent.xbutton.button); - break; - case KeyPress: - mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0); - printf("KeyPress : %s, %d\n", XKeysymToString(mykey), mykey); - - if (xevent.xkey.keycode == 27 || xevent.xkey.keycode == 9) { - return 0; - } - break; - case KeyRelease: - mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0); - printf("KeyRelease : %s, %d\n", XKeysymToString(mykey), mykey); - break; - } - } - - return 0; -} \ No newline at end of file diff --git a/rdp-acceleraed/RPI-Client/mouse.h b/rdp-acceleraed/RPI-Client/mouse.h deleted file mode 100644 index 110b29ce5a..0000000000 --- a/rdp-acceleraed/RPI-Client/mouse.h +++ /dev/null @@ -1,127 +0,0 @@ -#pragma once -#include "bcm_host.h" - -typedef struct -{ - DISPMANX_DISPLAY_HANDLE_T display; - DISPMANX_MODEINFO_T info; - void *image; - DISPMANX_UPDATE_HANDLE_T update; - DISPMANX_RESOURCE_HANDLE_T resource; - DISPMANX_ELEMENT_HANDLE_T element; - uint32_t vc_image_ptr; - -} RECT_VARS_T; - -static RECT_VARS_T gRectVars; - -class Mouse { -public: - RECT_VARS_T *vars; - VC_IMAGE_TYPE_T type; - - Mouse(){ - type = VC_IMAGE_ARGB8888; - int width=6; - int height=6; - - uint32_t screen = 0; - int ret; - VC_RECT_T src_rect; - VC_RECT_T dst_rect; - - VC_DISPMANX_ALPHA_T alpha = { (DISPMANX_FLAGS_ALPHA_T)(DISPMANX_FLAGS_ALPHA_FROM_SOURCE | DISPMANX_FLAGS_ALPHA_FIXED_ALL_PIXELS) , - 255, //alpha 0->255 - 0 }; - - vars = &gRectVars; - - bcm_host_init(); - - printf("Open display[%i]...\n", screen ); - vars->display = vc_dispmanx_display_open( screen ); - - ret = vc_dispmanx_display_get_info( vars->display, &vars->info); - assert(ret == 0); - printf( "Display is %d x %d\n", vars->info.width, vars->info.height ); - - vars->resource = vc_dispmanx_resource_create( type, - width, - height, - &vars->vc_image_ptr ); - assert( vars->resource ); - - - - vars->update = vc_dispmanx_update_start( 10 ); - assert( vars->update ); - - vc_dispmanx_rect_set( &src_rect, 0, 0, width << 16, height << 16 ); - - // Full screen - vc_dispmanx_rect_set( &dst_rect, 0, 0, width, height ); - - vars->element = vc_dispmanx_element_add( vars->update, - vars->display, - 2000, // layer - &dst_rect, - vars->resource, - &src_rect, - DISPMANX_PROTECTION_NONE, - &alpha, - NULL, // clamp - DISPMANX_NO_ROTATE ); - - - vc_dispmanx_rect_set( &dst_rect, 0, 0, width, height); - - - uint16_t *image = (uint16_t *)calloc( 1, width*4*height ); - memset(image, 0xFF, width*4*height); - ret = vc_dispmanx_resource_write_data( vars->resource, - type, - width*4,//image.step, - image, - &dst_rect ); - - ret = vc_dispmanx_update_submit_sync( vars->update ); - assert( ret == 0 ); - } - - void move(int x, int y){ - int ret; - VC_RECT_T dst_rect; - - vars->update = vc_dispmanx_update_start( 10 ); - - vc_dispmanx_rect_set( &dst_rect, x, y, 6, 6); - ret = vc_dispmanx_element_change_attributes( - vars->update, - vars->element, - /*ELEMENT_CHANGE_DEST_RECT*/ (1<<2), - 0, - 0, - &dst_rect, - NULL, - DISPMANX_NO_HANDLE, - DISPMANX_NO_ROTATE); - assert( ret == DISPMANX_SUCCESS ); - - /* Submit asynchronously, otherwise the performance suffers a lot */ - ret = vc_dispmanx_update_submit( vars->update, 0, NULL ); - assert( ret == DISPMANX_SUCCESS ); - } - void close(){ - int ret; - vars->update = vc_dispmanx_update_start( 10 ); - assert( vars->update ); - ret = vc_dispmanx_element_remove( vars->update, vars->element ); - assert( ret == 0 ); - ret = vc_dispmanx_update_submit_sync( vars->update ); - assert( ret == 0 ); - ret = vc_dispmanx_resource_delete( vars->resource ); - assert( ret == 0 ); - ret = vc_dispmanx_display_close( vars->display ); - assert( ret == 0 ); - } -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/CMakeLists.txt b/rdp-acceleraed/Server/CMakeLists.txt deleted file mode 100644 index 14a5d5bda0..0000000000 --- a/rdp-acceleraed/Server/CMakeLists.txt +++ /dev/null @@ -1,121 +0,0 @@ -cmake_minimum_required(VERSION 2.8) -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_CURRENT_SOURCE_DIR}") - -project( server ) - -include_directories(${CMAKE_CURRENT_SOURCE_DIR}) - -SET(USE_CUDA on CACHE BOOL "Use CUDA") -SET(USE_WDDM on CACHE BOOL "Use WDDM for screen capture") - -SET(USE_NVENC on CACHE BOOL "Use Nvidia encoder") - -# BOOST -set(Boost_USE_STATIC_LIBS ON) -set(Boost_USE_MULTITHREADED ON) -find_package( Boost REQUIRED COMPONENTS thread ) -if(Boost_FOUND) - message("Boost found!") -endif() -include_directories(${Boost_INCLUDE_DIR}) -LINK_DIRECTORIES(${Boost_LIBRARY_DIRS}) - -# FFMPEG -set(FFMPEG_ROOT "" CACHE FILEPATH "Root of the FFMPEG directory, which has README.txt") -if (FFMPEG_ROOT) - FIND_PATH( FFMPEG_INCLUDE_DIR libavcodec/avcodec.h - ${FFMPEG_ROOT}/include - ) - include_directories(${FFMPEG_INCLUDE_DIR}) - - FIND_LIBRARY( FFMPEG_LIBRARY_avcodec avcodec - ${FFMPEG_ROOT}/lib - ) - FIND_LIBRARY( FFMPEG_LIBRARY_avutil avutil - ${FFMPEG_ROOT}/lib - ) - if (FFMPEG_LIBRARY_avcodec AND FFMPEG_LIBRARY_avutil) - set (FFMPEG_FOUND 1) - set (FFMPEG_LIBRARIES "${FFMPEG_LIBRARY_avcodec};${FFMPEG_LIBRARY_avutil}") - message("FFMPEG found!") - endif() -endif() - -# DXGI and CUDA -if (USE_CUDA) - find_package(CUDA) -endif() -if(CUDA_FOUND) - set (HAS_CUDA 1) - message("CUDA found!") - include_directories(${CUDA_TOOLKIT_INCLUDE}) - CUDA_ADD_LIBRARY(cudalib STATIC - color_conversion.h - color_conversion.cu - OPTIONS -arch sm_30 - ) - TARGET_LINK_LIBRARIES(cudalib ${CUDA_LIBRARIES}) - set (CUDA_LINK_LIBRARIES "${CUDA_CUDA_LIBRARY};${CUDA_CUDART_LIBRARY};cudalib") -endif() - -if (USE_WDDM OR USE_NVENC) - find_package( DirectX ) -endif() - -include_directories(${DXGI_INCLUDES}) -include_directories(${Boost_INCLUDE_DIRS}) - -if (USE_WDDM AND DIRECTX_FOUND) - set (HAS_WDDM 1) - SET(Capture_HEADER - wddm.h - WDDMCapture.h - ) - SET(Capture_LIBRARIES - "${DXGI_LIBRARIES}" - ) -else() - SET(Capture_HEADER - GDICapture.h - ) -endif() - -if (DIRECTX_FOUND AND USE_NVENC) - set (HAS_NVENC 1) - #files for NVEncoder - SET(ENCODER_SOURCE - NvEncoder/NvHWEncoder.cpp - ) - SET(ENCODER_HEADERS - NV_encoding.hpp - NvEncoder/NvEncoder.h - NvEncoder/NvHWEncoder.h - NvEncoder/nvEncodeAPI.h - ) -elseif (FFMPEG_FOUND) - set (HAS_FFMPEG 1) - SET(ENCODER_SOURCE - ) - SET(ENCODER_HEADERS - FFMPEG_encoding.hpp - ) - SET(ENCODER_LIBRARIES - "${FFMPEG_LIBRARIES}" - ) -endif() - -SET(COMMON_SOURCE - config.h - bounded_buffer.h - Capture.h - fps.h - monitor.h - params.h -) - -add_executable( server server.cpp ${COMMON_SOURCE} ${ENCODER_SOURCE} ${ENCODER_HEADERS} ${Capture_HEADER} ) - - -target_link_libraries( server ${Boost_LIBRARIES} ${ENCODER_LIBRARIES} ${Capture_LIBRARIES} ${CUDA_LINK_LIBRARIES}) - -CONFIGURE_FILE(${CMAKE_CURRENT_SOURCE_DIR}/config.h.in ${CMAKE_CURRENT_SOURCE_DIR}/config.h) \ No newline at end of file diff --git a/rdp-acceleraed/Server/Capture.h b/rdp-acceleraed/Server/Capture.h deleted file mode 100644 index 605e489850..0000000000 --- a/rdp-acceleraed/Server/Capture.h +++ /dev/null @@ -1,8 +0,0 @@ -#pragma once - -class Capture { -public: - virtual void init(UINT monitorID, RECT screen) = 0; - virtual int getNextFrame(RGBQUAD**) = 0; - virtual void doneNextFrame() = 0; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/FFMPEG_encoding.hpp b/rdp-acceleraed/Server/FFMPEG_encoding.hpp deleted file mode 100644 index 4b837c8ff7..0000000000 --- a/rdp-acceleraed/Server/FFMPEG_encoding.hpp +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2001 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#define __STDC_CONSTANT_MACROS - -extern "C" { - #include - #include - #include - #include - #include - #include - #include -}; - -using namespace boost::asio; -using ip::tcp; - -typedef boost::shared_ptr socket_ptr; - -uint8_t endcode[] = { 0, 0, 1, 0xb7 }; -class FFMPEG_encoding { -public: - void load(int width, int height, socket_ptr sock) { - this->sock = sock; - c = NULL; - codec_id = AV_CODEC_ID_H264; - i=0; - - avcodec_register_all(); - - /* find the mpeg1 video encoder */ - codec = avcodec_find_encoder(codec_id); - if (!codec) { - fprintf(stderr, "Codec not found\n"); - exit(1); - } - - c = avcodec_alloc_context3(codec); - if (!c) { - fprintf(stderr, "Could not allocate video codec context\n"); - exit(1); - } - - /* put sample parameters */ - c->bit_rate = 400000; - /* resolution must be a multiple of two */ - c->width = width; - c->height = height; - /* frames per second */ - AVRational r; - r.den=1; - r.num=25; - c->time_base = r; - /* emit one intra frame every ten frames - * check frame pict_type before passing frame - * to encoder, if frame->pict_type is AV_PICTURE_TYPE_I - * then gop_size is ignored and the output of encoder - * will always be I frame irrespective to gop_size - */ - c->gop_size = 10; - c->max_b_frames = 0; - c->refs = 0; - c->pix_fmt = AV_PIX_FMT_YUV420P;//AV_PIX_FMT_YUV444P; - - // ultrafast,superfast, veryfast, faster, fast, medium, slow, slower, veryslow - if (codec_id == AV_CODEC_ID_H264) { - av_opt_set(c->priv_data, "preset", "veryfast", 0); - av_opt_set(c->priv_data, "tune", "zerolatency", 0); - av_opt_set(c->priv_data, "movflags", "faststart", 0); - } - - /* open it */ - if (avcodec_open2(c, codec, NULL) < 0) { - fprintf(stderr, "Could not open codec\n"); - exit(1); - } - - frame = av_frame_alloc(); - if (!frame) { - fprintf(stderr, "Could not allocate video frame\n"); - exit(1); - } - frame->format = c->pix_fmt; - frame->width = c->width; - frame->height = c->height; - - /* the image can be allocated by any means and av_image_alloc() is - * just the most convenient way if av_malloc() is to be used */ - int ret = av_image_alloc(frame->data, frame->linesize, c->width, c->height, - c->pix_fmt, 32); - if (ret < 0) { - fprintf(stderr, "Could not allocate raw picture buffer\n"); - exit(1); - } - } - void write(int width, int height, RGBQUAD *pPixels) { - av_init_packet(&pkt); - pkt.data = NULL; // packet data will be allocated by the encoder - pkt.size = 0; - - fflush(stdout); - - for (int y = 0; y < c->height; y++) { - for (int x = 0; x < c->width; x++) { - - RGBQUAD px = pPixels[y*width+x]; - int Y = ( ( 66 * px.rgbRed + 129 * px.rgbGreen + 25 * px.rgbBlue + 128) >> 8) + 16; - int U = ( ( -38 * px.rgbRed - 74 * px.rgbGreen + 112 * px.rgbBlue + 128) >> 8) + 128; - int V = ( ( 112 * px.rgbRed - 94 * px.rgbGreen - 18 * px.rgbBlue + 128) >> 8) + 128; - - frame->data[0][y * frame->linesize[0] + x] = Y; - //frame->data[1][y * frame->linesize[0] + x] = U; - //frame->data[2][y * frame->linesize[0] + x] = V; - - frame->data[1][(y >> 1) * frame->linesize[1] + (x >> 1)] = U; - frame->data[2][(y >> 1) * frame->linesize[2] + (x >> 1)] = V; - } - } - - frame->pts = i; - i++; - /* encode the image */ - int got_output; - int ret = avcodec_encode_video2(c, &pkt, frame, &got_output); - if (ret < 0) { - fprintf(stderr, "Error encoding frame\n"); - exit(1); - } - - if (got_output) { - printf("Write frame (size=%5d)\n", pkt.size); - //fwrite(pkt.data, 1, pkt.size, f); - boost::asio::write(*sock, buffer((char*)pkt.data, pkt.size)); - av_free_packet(&pkt); - } - } - void close () { - /* get the delayed frames */ - /*for (got_output = 1; got_output; i++) { - fflush(stdout); - - int ret = avcodec_encode_video2(c, &pkt, NULL, &got_output); - if (ret < 0) { - fprintf(stderr, "Error encoding frame\n"); - exit(1); - } - - if (got_output) { - printf("Write frame %3d (size=%5d)\n", i, pkt.size); - fwrite(pkt.data, 1, pkt.size, f); - av_free_packet(&pkt); - } - }*/ - - /* add sequence end code to have a real mpeg file */ - //fwrite(endcode, 1, sizeof(endcode), f); - //fclose(f); - - avcodec_close(c); - av_free(c); - av_freep(&frame->data[0]); - av_frame_free(&frame); - } -private: - AVCodecID codec_id; - AVCodec *codec; - AVCodecContext *c; - AVFrame *frame; - AVPacket pkt; - socket_ptr sock; - int i; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/FindDirectX.cmake b/rdp-acceleraed/Server/FindDirectX.cmake deleted file mode 100644 index f018325b15..0000000000 --- a/rdp-acceleraed/Server/FindDirectX.cmake +++ /dev/null @@ -1,31 +0,0 @@ -FIND_PATH( DXGI_INCLUDE dxgi1_2.h - "C:/Program Files (x86)/Windows Kits/10/Include/10.0.17763.0/shared" - "C:/Program Files (x86)/Windows Kits/10/Include/10.0.17134.0/shared" - "C:/Program Files (x86)/Windows Kits/8.1/Include/shared" - "C:/Program Files (x86)/Windows Kits/8.0/Include/shared" - "C:/Program Files/Windows Kits/8.1/Include/shared" - "C:/Program Files/Windows Kits/8.0/Include/shared" -) -FIND_LIBRARY( DXGI_LIBRARY1 d3d11 - "C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17763.0/um/x64" - "C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17134.0/um/x64" - "C:/Program Files (x86)/Windows Kits/8.1/Lib/winv6.3/um/x86" - "C:/Program Files (x86)/Windows Kits/8.0/Lib/winv6.3/um/x86" - "C:/Program Files/Windows Kits/8.1/Lib/winv6.3/um/x86" - "C:/Program Files/Windows Kits/8.0/Lib/winv6.3/um/x86" -) -FIND_LIBRARY( DXGI_LIBRARY2 Dxgi - "C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17763.0/um/x64" - "C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17134.0/um/x64" - "C:/Program Files (x86)/Windows Kits/8.1/Lib/winv6.3/um/x86" - "C:/Program Files (x86)/Windows Kits/8.0/Lib/winv6.3/um/x86" - "C:/Program Files/Windows Kits/8.1/Lib/winv6.3/um/x86" - "C:/Program Files/Windows Kits/8.0/Lib/winv6.3/um/x86" -) - -if (DXGI_INCLUDE AND DXGI_LIBRARY1 AND DXGI_LIBRARY2 ) - set (DIRECTX_FOUND 1) - set (DXGI_INCLUDES "${DXGI_INCLUDE}") - set (DXGI_LIBRARIES "${DXGI_LIBRARY1};${DXGI_LIBRARY2}") - message("DIRECTX found!") -endif() \ No newline at end of file diff --git a/rdp-acceleraed/Server/GDICapture.h b/rdp-acceleraed/Server/GDICapture.h deleted file mode 100644 index d952fac09b..0000000000 --- a/rdp-acceleraed/Server/GDICapture.h +++ /dev/null @@ -1,63 +0,0 @@ -#pragma once - -#include "Capture.h" - -class GDICapture : public Capture { -public: - void init(UINT monitorID, RECT screen) - { - this->screen = screen; - hdc = GetDC(NULL); // get the desktop device context - hDest = CreateCompatibleDC(hdc); // create a device context to use yourself - - // get the height and width of the screen - height = screen.bottom - screen.top; - width = screen.right - screen.left; - - int virtualScreenHeight = GetSystemMetrics(SM_CYVIRTUALSCREEN); - int virtualScreenWidth = GetSystemMetrics(SM_CXVIRTUALSCREEN); - - // create a bitmap - hbDesktop = CreateCompatibleBitmap( hdc, virtualScreenWidth, virtualScreenHeight); - - // use the previously created device context with the bitmap - SelectObject(hDest, hbDesktop); - - bmi.bmiHeader.biSize = sizeof(bmi.bmiHeader); - bmi.bmiHeader.biWidth = width; - bmi.bmiHeader.biHeight = -height; - bmi.bmiHeader.biPlanes = 1; - bmi.bmiHeader.biBitCount = 32; - bmi.bmiHeader.biCompression = BI_RGB; - - pPixels = new RGBQUAD[width * height]; - - } - int getNextFrame(RGBQUAD** data) - { - // copy from the desktop device context to the bitmap device context - BitBlt( hDest, 0,0, width, height, hdc, screen.left, screen.top, SRCCOPY); - - GetDIBits( - hDest, - hbDesktop, - 0, - height, - pPixels, - &bmi, - DIB_RGB_COLORS - ); - *data = pPixels; - return 0; - } - void doneNextFrame() - { - } -private: - HDC hdc, hDest; - int width, height; - RECT screen; - RGBQUAD *pPixels; - HBITMAP hbDesktop; - BITMAPINFO bmi; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/NV_encoding.hpp b/rdp-acceleraed/Server/NV_encoding.hpp deleted file mode 100644 index bfe3b9249e..0000000000 --- a/rdp-acceleraed/Server/NV_encoding.hpp +++ /dev/null @@ -1,100 +0,0 @@ -using namespace boost::asio; -using ip::tcp; - -typedef boost::shared_ptr socket_ptr; - -#include "NvEncoder/NvEncoder.h" -#include "color_conversion.h" - -class NV_encoding { -public: - void load(int width, int height, socket_ptr sock, UINT monitorID) { - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - this->sock = sock; - this->width = width; - this->height = height; - cNvEncoder = new CNvEncoder(); - cNvEncoder->InitCuda(); - nvStatus = cNvEncoder->Initialize(NV_ENC_DEVICE_TYPE_CUDA); - nvStatus = cNvEncoder->CreateEncoder(width, height); - nvStatus = cNvEncoder->AllocateIOBuffers(width, height, false); - - dataPacket = new DataPacket(); - dataPacket->data = new uint8_t[width*height]; - - yuv[0] = new uint8_t[width*height]; - yuv[1] = new uint8_t[width*height / 4]; - yuv[2] = new uint8_t[width*height / 4]; - - // Init avi file - //char buffer[255]; - //sprintf(buffer, "C:\\Monitor%d.avi", monitorID); - //ofs.open(buffer, std::ofstream::out | std::ofstream::binary); - - } - void write(int width, int height, RGBQUAD *pPixels) { - - bool rc = RGB_to_YV12(width, height, pPixels, yuv[0], yuv[1], yuv[2]); - - if (!rc){ - // The Cuda function RGB_to_YV12 failed, do CPU conversion - for (int y = 0; y < height; y++) { - for (int x = 0; x < width; x++) { - - RGBQUAD px = pPixels[y*width+x]; - int Y = ( ( 66 * px.rgbRed + 129 * px.rgbGreen + 25 * px.rgbBlue + 128) >> 8) + 16; - int U = ( ( -38 * px.rgbRed - 74 * px.rgbGreen + 112 * px.rgbBlue + 128) >> 8) + 128; - int V = ( ( 112 * px.rgbRed - 94 * px.rgbGreen - 18 * px.rgbBlue + 128) >> 8) + 128; - - yuv[0][y * width + x] = Y; - yuv[1][(y >> 1) * (width >> 1) + (x >> 1)] = U; - yuv[2][(y >> 1) * (width >> 1) + (x >> 1)] = V; - } - } - } - - EncodeFrameConfig stEncodeFrame; - memset(&stEncodeFrame, 0, sizeof(stEncodeFrame)); - - stEncodeFrame.yuv[0] = yuv[0]; - stEncodeFrame.yuv[1] = yuv[1]; - stEncodeFrame.yuv[2] = yuv[2]; - - stEncodeFrame.stride[0] = width; - stEncodeFrame.stride[1] = width/2; - stEncodeFrame.stride[2] = width/2; - stEncodeFrame.width = width; - stEncodeFrame.height = height; - - cNvEncoder->EncodeFrame(&stEncodeFrame, dataPacket, false, width, height); - if (dataPacket->size > 0) { - printf("Write frame (size=%5d)\n", dataPacket->size); - - //ofs.write((char*)dataPacket->data, dataPacket->size); - - boost::asio::write(*sock, buffer((char*)dataPacket->data, dataPacket->size)); - } - } - void close () { - delete cNvEncoder; - delete dataPacket->data; - delete dataPacket; - for (int i = 0; i < 3; i ++) - { - if (yuv[i]) - { - delete [] yuv[i]; - } - } - } -private: - int width; - int height; - socket_ptr sock; - uint8_t *yuv[3]; - CNvEncoder* cNvEncoder; - DataPacket* dataPacket; - - //std::ofstream ofs; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/NvEncoder/NvEncoder.h b/rdp-acceleraed/Server/NvEncoder/NvEncoder.h deleted file mode 100644 index 840105b6d7..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/NvEncoder.h +++ /dev/null @@ -1,503 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#if defined(NV_WINDOWS) - #include - #include - #include -#pragma warning(disable : 4996) -#endif - -//#pragma comment (lib, "cuda.lib") -#pragma comment (lib, "d3d9.lib") -#pragma comment (lib, "d3d10.lib") -#pragma comment (lib, "d3d11.lib") - -#include "NvHWEncoder.h" -#include "nvEncodeAPI.h" -#include "nvUtils.h" - -#define MAX_ENCODE_QUEUE 32 -#define BITSTREAM_BUFFER_SIZE 2 * 1024 * 1024 - -#define SET_VER(configStruct, type) {configStruct.version = type##_VER;} - -template -class CNvQueue { - T** m_pBuffer; - unsigned int m_uSize; - unsigned int m_uPendingCount; - unsigned int m_uAvailableIdx; - unsigned int m_uPendingndex; -public: - CNvQueue(): m_pBuffer(NULL), m_uSize(0), m_uPendingCount(0), m_uAvailableIdx(0), - m_uPendingndex(0) - { - } - - ~CNvQueue() - { - delete[] m_pBuffer; - } - - bool Initialize(T *pItems, unsigned int uSize) - { - m_uSize = uSize; - m_uPendingCount = 0; - m_uAvailableIdx = 0; - m_uPendingndex = 0; - m_pBuffer = new T *[m_uSize]; - for (unsigned int i = 0; i < m_uSize; i++) - { - m_pBuffer[i] = &pItems[i]; - } - return true; - } - - - T * GetAvailable() - { - T *pItem = NULL; - if (m_uPendingCount == m_uSize) - { - return NULL; - } - pItem = m_pBuffer[m_uAvailableIdx]; - m_uAvailableIdx = (m_uAvailableIdx+1)%m_uSize; - m_uPendingCount += 1; - return pItem; - } - - T* GetPending() - { - if (m_uPendingCount == 0) - { - return NULL; - } - - T *pItem = m_pBuffer[m_uPendingndex]; - m_uPendingndex = (m_uPendingndex+1)%m_uSize; - m_uPendingCount -= 1; - return pItem; - } -}; - -typedef struct _EncodeFrameConfig -{ - uint8_t *yuv[3]; - uint32_t stride[3]; - uint32_t width; - uint32_t height; -}EncodeFrameConfig; - -typedef enum -{ - NV_ENC_DX9 = 0, - NV_ENC_DX11 = 1, - NV_ENC_CUDA = 2, - NV_ENC_DX10 = 3, -} NvEncodeDeviceType; - -class CNvEncoder -{ -public: - CNvEncoder() - { - m_pNvHWEncoder = new CNvHWEncoder; - m_pDevice = NULL; -#if defined (NV_WINDOWS) - m_pD3D = NULL; -#endif - m_cuContext = NULL; - - m_uEncodeBufferCount = 0; - memset(&m_stEncoderInput, 0, sizeof(m_stEncoderInput)); - memset(&m_stEOSOutputBfr, 0, sizeof(m_stEOSOutputBfr)); - - memset(&m_stEncodeBuffer, 0, sizeof(m_stEncodeBuffer)); - } - - ~CNvEncoder() - { - if (m_pNvHWEncoder) - { - delete m_pNvHWEncoder; - m_pNvHWEncoder = NULL; - } - } - - NVENCSTATUS InitCuda(uint32_t deviceID = 0) - { - CUresult cuResult; - CUdevice device; - CUcontext cuContextCurr; - int deviceCount = 0; - int SMminor = 0, SMmajor = 0; - - cuResult = cuInit(0); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuInit error:0x%x\n", cuResult); - assert(0); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - cuResult = cuDeviceGetCount(&deviceCount); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuDeviceGetCount error:0x%x\n", cuResult); - assert(0); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - // If dev is negative value, we clamp to 0 - if ((int)deviceID < 0) - deviceID = 0; - - if (deviceID >(unsigned int)deviceCount - 1) - { - PRINTERR("Invalid Device Id = %d\n", deviceID); - return NV_ENC_ERR_INVALID_ENCODERDEVICE; - } - - cuResult = cuDeviceGet(&device, deviceID); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuDeviceGet error:0x%x\n", cuResult); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - cuResult = cuDeviceComputeCapability(&SMmajor, &SMminor, deviceID); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuDeviceComputeCapability error:0x%x\n", cuResult); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - if (((SMmajor << 4) + SMminor) < 0x30) - { - PRINTERR("GPU %d does not have NVENC capabilities exiting\n", deviceID); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - cuResult = cuCtxCreate((CUcontext*)(&m_pDevice), 0, device); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuCtxCreate error:0x%x\n", cuResult); - assert(0); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - - cuResult = cuCtxPopCurrent(&cuContextCurr); - if (cuResult != CUDA_SUCCESS) - { - PRINTERR("cuCtxPopCurrent error:0x%x\n", cuResult); - assert(0); - return NV_ENC_ERR_NO_ENCODE_DEVICE; - } - return NV_ENC_SUCCESS; - } - NVENCSTATUS Initialize(NV_ENC_DEVICE_TYPE deviceType) { - NVENCSTATUS nvStatus = m_pNvHWEncoder->Initialize(m_pDevice, deviceType); - return nvStatus; - } - - NVENCSTATUS CreateEncoder(int width, int height){ - EncodeConfig encodeConfig; - - memset(&encodeConfig, 0, sizeof(EncodeConfig)); - - encodeConfig.width = width; - encodeConfig.height = height; - - // B = Encoding bitrate - int B = 1000 * 1024; // kbps - int fps = 20; - uint32_t maxFrameSize = B / fps; // bandwidth / frame rate - - encodeConfig.vbvSize = maxFrameSize; - - encodeConfig.endFrameIdx = INT_MAX; - encodeConfig.bitrate = encodeConfig.vbvSize * fps; - encodeConfig.vbvMaxBitrate = encodeConfig.vbvSize * fps; - - - encodeConfig.rcMode = NV_ENC_PARAMS_RC_VBR;//NV_ENC_PARAMS_RC_CONSTQP; - encodeConfig.gopLength = 200;//NVENC_INFINITE_GOPLENGTH; - encodeConfig.deviceType = NV_ENC_CUDA; - encodeConfig.codec = NV_ENC_H264; - encodeConfig.fps = fps; - encodeConfig.qp = 28; - encodeConfig.presetGUID = NV_ENC_PRESET_LOW_LATENCY_HQ_GUID;//NV_ENC_PRESET_LOW_LATENCY_HQ_GUID;//NV_ENC_PRESET_DEFAULT_GUID; - encodeConfig.pictureStruct = NV_ENC_PIC_STRUCT_FRAME; - encodeConfig.isYuv444 = 0; - - encodeConfig.presetGUID = m_pNvHWEncoder->GetPresetGUID(encodeConfig.encoderPreset, encodeConfig.codec); - - printf("Encoding input : \"%s\"\n", encodeConfig.inputFileName); - printf(" output : \"%s\"\n", encodeConfig.outputFileName); - printf(" codec : \"%s\"\n", encodeConfig.codec == NV_ENC_HEVC ? "HEVC" : "H264"); - printf(" size : %dx%d\n", encodeConfig.width, encodeConfig.height); - printf(" bitrate : %d bits/sec\n", encodeConfig.bitrate); - printf(" vbvMaxBitrate : %d bits/sec\n", encodeConfig.vbvMaxBitrate); - printf(" vbvSize : %d bits\n", encodeConfig.vbvSize); - printf(" fps : %d frames/sec\n", encodeConfig.fps); - printf(" rcMode : %s\n", encodeConfig.rcMode == NV_ENC_PARAMS_RC_CONSTQP ? "CONSTQP" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_VBR ? "VBR" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_CBR ? "CBR" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_VBR_MINQP ? "VBR MINQP" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_QUALITY ? "TWO_PASS_QUALITY" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP ? "TWO_PASS_FRAMESIZE_CAP" : - encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_VBR ? "TWO_PASS_VBR" : "UNKNOWN"); - if (encodeConfig.gopLength == NVENC_INFINITE_GOPLENGTH) - printf(" goplength : INFINITE GOP \n"); - else - printf(" goplength : %d \n", encodeConfig.gopLength); - printf(" B frames : %d \n", encodeConfig.numB); - printf(" QP : %d \n", encodeConfig.qp); - printf(" Input Format : %s\n", encodeConfig.isYuv444 ? "YUV 444" : "YUV 420"); - printf(" preset : %s\n", (encodeConfig.presetGUID == NV_ENC_PRESET_LOW_LATENCY_HQ_GUID) ? "LOW_LATENCY_HQ" : - (encodeConfig.presetGUID == NV_ENC_PRESET_LOW_LATENCY_HP_GUID) ? "LOW_LATENCY_HP" : - (encodeConfig.presetGUID == NV_ENC_PRESET_HQ_GUID) ? "HQ_PRESET" : - (encodeConfig.presetGUID == NV_ENC_PRESET_HP_GUID) ? "HP_PRESET" : - (encodeConfig.presetGUID == NV_ENC_PRESET_LOSSLESS_HP_GUID) ? "LOSSLESS_HP" : "LOW_LATENCY_DEFAULT"); - printf(" Picture Structure : %s\n", (encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FRAME) ? "Frame Mode" : - (encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM) ? "Top Field first" : - (encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP) ? "Bottom Field first" : "INVALID"); - printf(" devicetype : %s\n", encodeConfig.deviceType == NV_ENC_DX9 ? "DX9" : - encodeConfig.deviceType == NV_ENC_DX10 ? "DX10" : - encodeConfig.deviceType == NV_ENC_DX11 ? "DX11" : - encodeConfig.deviceType == NV_ENC_CUDA ? "CUDA" : "INVALID"); - - printf("\n"); - - NVENCSTATUS nvStatus = m_pNvHWEncoder->CreateEncoder(&encodeConfig); - - m_uEncodeBufferCount = encodeConfig.numB + 1; // min buffers is numb + 1 + 3 pipelining - - m_uPicStruct = encodeConfig.pictureStruct; - - return nvStatus; - } - - NVENCSTATUS EncodeFrame(EncodeFrameConfig *pEncodeFrame, DataPacket* dataPacket, bool bFlush=false, uint32_t width=0, uint32_t height=0) { - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - uint32_t lockedPitch = 0; - EncodeBuffer *pEncodeBuffer = NULL; - - if (bFlush) - { - FlushEncoder(dataPacket); - return NV_ENC_SUCCESS; - } - - if (!pEncodeFrame) - { - return NV_ENC_ERR_INVALID_PARAM; - } - - pEncodeBuffer = m_EncodeBufferQueue.GetAvailable(); - if(!pEncodeBuffer) - { - m_pNvHWEncoder->ProcessOutput(m_EncodeBufferQueue.GetPending(), dataPacket); - pEncodeBuffer = m_EncodeBufferQueue.GetAvailable(); - } - - unsigned char *pInputSurface; - - nvStatus = m_pNvHWEncoder->NvEncLockInputBuffer(pEncodeBuffer->stInputBfr.hInputSurface, (void**)&pInputSurface, &lockedPitch); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - if (pEncodeBuffer->stInputBfr.bufferFmt == NV_ENC_BUFFER_FORMAT_NV12_PL) - { - unsigned char *pInputSurfaceCh = pInputSurface + (pEncodeBuffer->stInputBfr.dwHeight*lockedPitch); - convertYUVpitchtoNV12(pEncodeFrame->yuv[0], pEncodeFrame->yuv[1], pEncodeFrame->yuv[2], pInputSurface, pInputSurfaceCh, width, height, width, lockedPitch); - } - else - { - unsigned char *pInputSurfaceCb = pInputSurface + (pEncodeBuffer->stInputBfr.dwHeight * lockedPitch); - unsigned char *pInputSurfaceCr = pInputSurfaceCb + (pEncodeBuffer->stInputBfr.dwHeight * lockedPitch); - convertYUVpitchtoYUV444(pEncodeFrame->yuv[0], pEncodeFrame->yuv[1], pEncodeFrame->yuv[2], pInputSurface, pInputSurfaceCb, pInputSurfaceCr, width, height, width, lockedPitch); - } - nvStatus = m_pNvHWEncoder->NvEncUnlockInputBuffer(pEncodeBuffer->stInputBfr.hInputSurface); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - nvStatus = m_pNvHWEncoder->NvEncEncodeFrame(pEncodeBuffer, NULL, width, height, (NV_ENC_PIC_STRUCT)m_uPicStruct); - return nvStatus; - } - - NVENCSTATUS AllocateIOBuffers(uint32_t uInputWidth, uint32_t uInputHeight, uint32_t isYuv444) - { - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - m_EncodeBufferQueue.Initialize(m_stEncodeBuffer, m_uEncodeBufferCount); - for (uint32_t i = 0; i < m_uEncodeBufferCount; i++) - { - nvStatus = m_pNvHWEncoder->NvEncCreateInputBuffer(uInputWidth, uInputHeight, &m_stEncodeBuffer[i].stInputBfr.hInputSurface, isYuv444); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - m_stEncodeBuffer[i].stInputBfr.bufferFmt = isYuv444 ? NV_ENC_BUFFER_FORMAT_YUV444_PL : NV_ENC_BUFFER_FORMAT_NV12_PL; - m_stEncodeBuffer[i].stInputBfr.dwWidth = uInputWidth; - m_stEncodeBuffer[i].stInputBfr.dwHeight = uInputHeight; - - nvStatus = m_pNvHWEncoder->NvEncCreateBitstreamBuffer(BITSTREAM_BUFFER_SIZE, &m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - m_stEncodeBuffer[i].stOutputBfr.dwBitstreamBufferSize = BITSTREAM_BUFFER_SIZE; - - #if defined (NV_WINDOWS) - nvStatus = m_pNvHWEncoder->NvEncRegisterAsyncEvent(&m_stEncodeBuffer[i].stOutputBfr.hOutputEvent); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - m_stEncodeBuffer[i].stOutputBfr.bWaitOnEvent = true; - #else - m_stEncodeBuffer[i].stOutputBfr.hOutputEvent = NULL; - #endif - } - - m_stEOSOutputBfr.bEOSFlag = TRUE; - - #if defined (NV_WINDOWS) - nvStatus = m_pNvHWEncoder->NvEncRegisterAsyncEvent(&m_stEOSOutputBfr.hOutputEvent); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - #else - m_stEOSOutputBfr.hOutputEvent = NULL; - #endif - - return NV_ENC_SUCCESS; - } - - NVENCSTATUS ReleaseIOBuffers() - { - for (uint32_t i = 0; i < m_uEncodeBufferCount; i++) - { - m_pNvHWEncoder->NvEncDestroyInputBuffer(m_stEncodeBuffer[i].stInputBfr.hInputSurface); - m_stEncodeBuffer[i].stInputBfr.hInputSurface = NULL; - - m_pNvHWEncoder->NvEncDestroyBitstreamBuffer(m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer); - m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer = NULL; - - #if defined(NV_WINDOWS) - m_pNvHWEncoder->NvEncUnregisterAsyncEvent(m_stEncodeBuffer[i].stOutputBfr.hOutputEvent); - nvCloseFile(m_stEncodeBuffer[i].stOutputBfr.hOutputEvent); - m_stEncodeBuffer[i].stOutputBfr.hOutputEvent = NULL; - #endif - } - - if (m_stEOSOutputBfr.hOutputEvent) - { - #if defined(NV_WINDOWS) - m_pNvHWEncoder->NvEncUnregisterAsyncEvent(m_stEOSOutputBfr.hOutputEvent); - nvCloseFile(m_stEOSOutputBfr.hOutputEvent); - m_stEOSOutputBfr.hOutputEvent = NULL; - #endif - } - - return NV_ENC_SUCCESS; - } - -protected: - CNvHWEncoder *m_pNvHWEncoder; - uint32_t m_uEncodeBufferCount; - uint32_t m_uPicStruct; - void* m_pDevice; -#if defined(NV_WINDOWS) - IDirect3D9 *m_pD3D; -#endif - - CUcontext m_cuContext; - EncodeConfig m_stEncoderInput; - EncodeBuffer m_stEncodeBuffer[MAX_ENCODE_QUEUE]; - CNvQueue m_EncodeBufferQueue; - EncodeOutputBuffer m_stEOSOutputBfr; - - void convertYUVpitchtoNV12( unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr, - unsigned char *nv12_luma, unsigned char *nv12_chroma, - int width, int height , int srcStride, int dstStride) - { - int y; - int x; - if (srcStride == 0) - srcStride = width; - if (dstStride == 0) - dstStride = width; - - for ( y = 0 ; y < height ; y++) - { - memcpy( nv12_luma + (dstStride*y), yuv_luma + (srcStride*y) , width ); - } - - for ( y = 0 ; y < height/2 ; y++) - { - for ( x= 0 ; x < width; x=x+2) - { - nv12_chroma[(y*dstStride) + x] = yuv_cb[((srcStride/2)*y) + (x >>1)]; - nv12_chroma[(y*dstStride) +(x+1)] = yuv_cr[((srcStride/2)*y) + (x >>1)]; - } - } - } - - void convertYUVpitchtoYUV444(unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr, - unsigned char *surf_luma, unsigned char *surf_cb, unsigned char *surf_cr, int width, int height, int srcStride, int dstStride) - { - int h; - - for (h = 0; h < height; h++) - { - memcpy(surf_luma + dstStride * h, yuv_luma + srcStride * h, width); - memcpy(surf_cb + dstStride * h, yuv_cb + srcStride * h, width); - memcpy(surf_cr + dstStride * h, yuv_cr + srcStride * h, width); - } - } -protected: - NVENCSTATUS Deinitialize(uint32_t devicetype); - NVENCSTATUS InitD3D9(uint32_t deviceID = 0); - NVENCSTATUS InitD3D11(uint32_t deviceID = 0); - NVENCSTATUS InitD3D10(uint32_t deviceID = 0); - - - - unsigned char* LockInputBuffer(void * hInputSurface, uint32_t *pLockedPitch); - - NVENCSTATUS FlushEncoder(DataPacket* dataPacket) { - NVENCSTATUS nvStatus = m_pNvHWEncoder->NvEncFlushEncoderQueue(m_stEOSOutputBfr.hOutputEvent); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - return nvStatus; - } - - EncodeBuffer *pEncodeBufer = m_EncodeBufferQueue.GetPending(); - while (pEncodeBufer) - { - m_pNvHWEncoder->ProcessOutput(pEncodeBufer, dataPacket); - pEncodeBufer = m_EncodeBufferQueue.GetPending(); - } - -#if defined(NV_WINDOWS) - if (WaitForSingleObject(m_stEOSOutputBfr.hOutputEvent, 500) != WAIT_OBJECT_0) - { - assert(0); - nvStatus = NV_ENC_ERR_GENERIC; - } -#endif - - return nvStatus; - } -}; - -// NVEncodeAPI entry point -typedef NVENCSTATUS (NVENCAPI *MYPROC)(NV_ENCODE_API_FUNCTION_LIST*); diff --git a/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.cpp b/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.cpp deleted file mode 100644 index 9cd9886075..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.cpp +++ /dev/null @@ -1,1268 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#include "NvHWEncoder.h" - -NVENCSTATUS CNvHWEncoder::NvEncOpenEncodeSession(void* device, uint32_t deviceType) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncOpenEncodeSession(device, deviceType, &m_hEncoder); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeGUIDCount(uint32_t* encodeGUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeGUIDCount(m_hEncoder, encodeGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeProfileGUIDCount(GUID encodeGUID, uint32_t* encodeProfileGUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeProfileGUIDCount(m_hEncoder, encodeGUID, encodeProfileGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeProfileGUIDs(GUID encodeGUID, GUID* profileGUIDs, uint32_t guidArraySize, uint32_t* GUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeProfileGUIDs(m_hEncoder, encodeGUID, profileGUIDs, guidArraySize, GUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeGUIDs(GUID* GUIDs, uint32_t guidArraySize, uint32_t* GUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeGUIDs(m_hEncoder, GUIDs, guidArraySize, GUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetInputFormatCount(GUID encodeGUID, uint32_t* inputFmtCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetInputFormatCount(m_hEncoder, encodeGUID, inputFmtCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetInputFormats(GUID encodeGUID, NV_ENC_BUFFER_FORMAT* inputFmts, uint32_t inputFmtArraySize, uint32_t* inputFmtCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetInputFormats(m_hEncoder, encodeGUID, inputFmts, inputFmtArraySize, inputFmtCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeCaps(GUID encodeGUID, NV_ENC_CAPS_PARAM* capsParam, int* capsVal) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeCaps(m_hEncoder, encodeGUID, capsParam, capsVal); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodePresetCount(GUID encodeGUID, uint32_t* encodePresetGUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetCount(m_hEncoder, encodeGUID, encodePresetGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodePresetGUIDs(GUID encodeGUID, GUID* presetGUIDs, uint32_t guidArraySize, uint32_t* encodePresetGUIDCount) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetGUIDs(m_hEncoder, encodeGUID, presetGUIDs, guidArraySize, encodePresetGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodePresetConfig(GUID encodeGUID, GUID presetGUID, NV_ENC_PRESET_CONFIG* presetConfig) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetConfig(m_hEncoder, encodeGUID, presetGUID, presetConfig); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncCreateInputBuffer(uint32_t width, uint32_t height, void** inputBuffer, uint32_t isYuv444) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_CREATE_INPUT_BUFFER createInputBufferParams; - - memset(&createInputBufferParams, 0, sizeof(createInputBufferParams)); - SET_VER(createInputBufferParams, NV_ENC_CREATE_INPUT_BUFFER); - - createInputBufferParams.width = width; - createInputBufferParams.height = height; - createInputBufferParams.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED; - createInputBufferParams.bufferFmt = isYuv444 ? NV_ENC_BUFFER_FORMAT_YUV444_PL : NV_ENC_BUFFER_FORMAT_NV12_PL; - - nvStatus = m_pEncodeAPI->nvEncCreateInputBuffer(m_hEncoder, &createInputBufferParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *inputBuffer = createInputBufferParams.inputBuffer; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncDestroyInputBuffer(NV_ENC_INPUT_PTR inputBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (inputBuffer) - { - nvStatus = m_pEncodeAPI->nvEncDestroyInputBuffer(m_hEncoder, inputBuffer); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncCreateBitstreamBuffer(uint32_t size, void** bitstreamBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_CREATE_BITSTREAM_BUFFER createBitstreamBufferParams; - - memset(&createBitstreamBufferParams, 0, sizeof(createBitstreamBufferParams)); - SET_VER(createBitstreamBufferParams, NV_ENC_CREATE_BITSTREAM_BUFFER); - - createBitstreamBufferParams.size = size; - createBitstreamBufferParams.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED; - - nvStatus = m_pEncodeAPI->nvEncCreateBitstreamBuffer(m_hEncoder, &createBitstreamBufferParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *bitstreamBuffer = createBitstreamBufferParams.bitstreamBuffer; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncDestroyBitstreamBuffer(NV_ENC_OUTPUT_PTR bitstreamBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (bitstreamBuffer) - { - nvStatus = m_pEncodeAPI->nvEncDestroyBitstreamBuffer(m_hEncoder, bitstreamBuffer); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncLockBitstream(NV_ENC_LOCK_BITSTREAM* lockBitstreamBufferParams) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncLockBitstream(m_hEncoder, lockBitstreamBufferParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncUnlockBitstream(NV_ENC_OUTPUT_PTR bitstreamBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncUnlockBitstream(m_hEncoder, bitstreamBuffer); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncLockInputBuffer(void* inputBuffer, void** bufferDataPtr, uint32_t* pitch) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_LOCK_INPUT_BUFFER lockInputBufferParams; - - memset(&lockInputBufferParams, 0, sizeof(lockInputBufferParams)); - SET_VER(lockInputBufferParams, NV_ENC_LOCK_INPUT_BUFFER); - - lockInputBufferParams.inputBuffer = inputBuffer; - nvStatus = m_pEncodeAPI->nvEncLockInputBuffer(m_hEncoder, &lockInputBufferParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *bufferDataPtr = lockInputBufferParams.bufferDataPtr; - *pitch = lockInputBufferParams.pitch; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncUnlockInputBuffer(NV_ENC_INPUT_PTR inputBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncUnlockInputBuffer(m_hEncoder, inputBuffer); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetEncodeStats(NV_ENC_STAT* encodeStats) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeStats(m_hEncoder, encodeStats); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncGetSequenceParams(NV_ENC_SEQUENCE_PARAM_PAYLOAD* sequenceParamPayload) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncGetSequenceParams(m_hEncoder, sequenceParamPayload); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncRegisterAsyncEvent(void** completionEvent) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_EVENT_PARAMS eventParams; - - memset(&eventParams, 0, sizeof(eventParams)); - SET_VER(eventParams, NV_ENC_EVENT_PARAMS); - -#if defined (NV_WINDOWS) - eventParams.completionEvent = CreateEvent(NULL, FALSE, FALSE, NULL); -#else - eventParams.completionEvent = NULL; -#endif - nvStatus = m_pEncodeAPI->nvEncRegisterAsyncEvent(m_hEncoder, &eventParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *completionEvent = eventParams.completionEvent; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncUnregisterAsyncEvent(void* completionEvent) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_EVENT_PARAMS eventParams; - - if (completionEvent) - { - memset(&eventParams, 0, sizeof(eventParams)); - SET_VER(eventParams, NV_ENC_EVENT_PARAMS); - - eventParams.completionEvent = completionEvent; - - nvStatus = m_pEncodeAPI->nvEncUnregisterAsyncEvent(m_hEncoder, &eventParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncMapInputResource(void* registeredResource, void** mappedResource) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_MAP_INPUT_RESOURCE mapInputResParams; - - memset(&mapInputResParams, 0, sizeof(mapInputResParams)); - SET_VER(mapInputResParams, NV_ENC_MAP_INPUT_RESOURCE); - - mapInputResParams.registeredResource = registeredResource; - - nvStatus = m_pEncodeAPI->nvEncMapInputResource(m_hEncoder, &mapInputResParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *mappedResource = mapInputResParams.mappedResource; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncUnmapInputResource(NV_ENC_INPUT_PTR mappedInputBuffer) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (mappedInputBuffer) - { - nvStatus = m_pEncodeAPI->nvEncUnmapInputResource(m_hEncoder, mappedInputBuffer); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncDestroyEncoder() -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (m_bEncoderInitialized) - { - nvStatus = m_pEncodeAPI->nvEncDestroyEncoder(m_hEncoder); - - m_bEncoderInitialized = false; - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncInvalidateRefFrames(const NvEncPictureCommand *pEncPicCommand) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - for (uint32_t i = 0; i < pEncPicCommand->numRefFramesToInvalidate; i++) - { - nvStatus = m_pEncodeAPI->nvEncInvalidateRefFrames(m_hEncoder, pEncPicCommand->refFrameNumbers[i]); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncOpenEncodeSessionEx(void* device, NV_ENC_DEVICE_TYPE deviceType) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS openSessionExParams; - - memset(&openSessionExParams, 0, sizeof(openSessionExParams)); - SET_VER(openSessionExParams, NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS); - - openSessionExParams.device = device; - openSessionExParams.deviceType = deviceType; - openSessionExParams.reserved = NULL; - openSessionExParams.apiVersion = NVENCAPI_VERSION; - - nvStatus = m_pEncodeAPI->nvEncOpenEncodeSessionEx(&openSessionExParams, &m_hEncoder); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncRegisterResource(NV_ENC_INPUT_RESOURCE_TYPE resourceType, void* resourceToRegister, uint32_t width, uint32_t height, uint32_t pitch, void** registeredResource) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_REGISTER_RESOURCE registerResParams; - - memset(®isterResParams, 0, sizeof(registerResParams)); - SET_VER(registerResParams, NV_ENC_REGISTER_RESOURCE); - - registerResParams.resourceType = resourceType; - registerResParams.resourceToRegister = resourceToRegister; - registerResParams.width = width; - registerResParams.height = height; - registerResParams.pitch = pitch; - - nvStatus = m_pEncodeAPI->nvEncRegisterResource(m_hEncoder, ®isterResParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - *registeredResource = registerResParams.registeredResource; - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncUnregisterResource(NV_ENC_REGISTERED_PTR registeredRes) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - nvStatus = m_pEncodeAPI->nvEncUnregisterResource(m_hEncoder, registeredRes); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::NvEncReconfigureEncoder(const NvEncPictureCommand *pEncPicCommand) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (pEncPicCommand->bBitrateChangePending || pEncPicCommand->bResolutionChangePending) - { - if (pEncPicCommand->bResolutionChangePending) - { - m_uCurWidth = pEncPicCommand->newWidth; - m_uCurHeight = pEncPicCommand->newHeight; - if ((m_uCurWidth > m_uMaxWidth) || (m_uCurHeight > m_uMaxHeight)) - { - return NV_ENC_ERR_INVALID_PARAM; - } - m_stCreateEncodeParams.encodeWidth = m_uCurWidth; - m_stCreateEncodeParams.encodeHeight = m_uCurHeight; - m_stCreateEncodeParams.darWidth = m_uCurWidth; - m_stCreateEncodeParams.darHeight = m_uCurHeight; - } - - if (pEncPicCommand->bBitrateChangePending) - { - m_stEncodeConfig.rcParams.averageBitRate = pEncPicCommand->newBitrate; - m_stEncodeConfig.rcParams.maxBitRate = pEncPicCommand->newBitrate; - m_stEncodeConfig.rcParams.vbvBufferSize = pEncPicCommand->newVBVSize != 0 ? pEncPicCommand->newVBVSize : (pEncPicCommand->newBitrate * m_stCreateEncodeParams.frameRateDen) / m_stCreateEncodeParams.frameRateNum; - m_stEncodeConfig.rcParams.vbvInitialDelay = m_stEncodeConfig.rcParams.vbvBufferSize; - } - - NV_ENC_RECONFIGURE_PARAMS stReconfigParams; - memset(&stReconfigParams, 0, sizeof(stReconfigParams)); - memcpy(&stReconfigParams.reInitEncodeParams, &m_stCreateEncodeParams, sizeof(m_stCreateEncodeParams)); - stReconfigParams.version = NV_ENC_RECONFIGURE_PARAMS_VER; - stReconfigParams.forceIDR = pEncPicCommand->bResolutionChangePending ? 1 : 0; - - nvStatus = m_pEncodeAPI->nvEncReconfigureEncoder(m_hEncoder, &stReconfigParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - } - - return nvStatus; -} - -CNvHWEncoder::CNvHWEncoder() -{ - m_hEncoder = NULL; - m_bEncoderInitialized = false; - m_pEncodeAPI = NULL; - m_hinstLib = NULL; - m_EncodeIdx = 0; - m_uCurWidth = 0; - m_uCurHeight = 0; - m_uMaxWidth = 0; - m_uMaxHeight = 0; - - memset(&m_stCreateEncodeParams, 0, sizeof(m_stCreateEncodeParams)); - SET_VER(m_stCreateEncodeParams, NV_ENC_INITIALIZE_PARAMS); - - memset(&m_stEncodeConfig, 0, sizeof(m_stEncodeConfig)); - SET_VER(m_stEncodeConfig, NV_ENC_CONFIG); -} - -CNvHWEncoder::~CNvHWEncoder() -{ - // clean up encode API resources here - if (m_pEncodeAPI) - { - delete m_pEncodeAPI; - m_pEncodeAPI = NULL; - } - - if (m_hinstLib) - { -#if defined (NV_WINDOWS) - FreeLibrary(m_hinstLib); -#else - dlclose(m_hinstLib); -#endif - - m_hinstLib = NULL; - } -} - -NVENCSTATUS CNvHWEncoder::ValidateEncodeGUID (GUID inputCodecGuid) -{ - unsigned int i, codecFound, encodeGUIDCount, encodeGUIDArraySize; - NVENCSTATUS nvStatus; - GUID *encodeGUIDArray; - - nvStatus = m_pEncodeAPI->nvEncGetEncodeGUIDCount(m_hEncoder, &encodeGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - return nvStatus; - } - - encodeGUIDArray = new GUID[encodeGUIDCount]; - memset(encodeGUIDArray, 0, sizeof(GUID)* encodeGUIDCount); - - encodeGUIDArraySize = 0; - nvStatus = m_pEncodeAPI->nvEncGetEncodeGUIDs(m_hEncoder, encodeGUIDArray, encodeGUIDCount, &encodeGUIDArraySize); - if (nvStatus != NV_ENC_SUCCESS) - { - delete[] encodeGUIDArray; - assert(0); - return nvStatus; - } - - assert(encodeGUIDArraySize <= encodeGUIDCount); - - codecFound = 0; - for (i = 0; i < encodeGUIDArraySize; i++) - { - if (inputCodecGuid == encodeGUIDArray[i]) - { - codecFound = 1; - break; - } - } - - delete[] encodeGUIDArray; - - if (codecFound) - return NV_ENC_SUCCESS; - else - return NV_ENC_ERR_INVALID_PARAM; -} - -NVENCSTATUS CNvHWEncoder::ValidatePresetGUID(GUID inputPresetGuid, GUID inputCodecGuid) -{ - uint32_t i, presetFound, presetGUIDCount, presetGUIDArraySize; - NVENCSTATUS nvStatus; - GUID *presetGUIDArray; - - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetCount(m_hEncoder, inputCodecGuid, &presetGUIDCount); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - return nvStatus; - } - - presetGUIDArray = new GUID[presetGUIDCount]; - memset(presetGUIDArray, 0, sizeof(GUID)* presetGUIDCount); - - presetGUIDArraySize = 0; - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetGUIDs(m_hEncoder, inputCodecGuid, presetGUIDArray, presetGUIDCount, &presetGUIDArraySize); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - delete[] presetGUIDArray; - return nvStatus; - } - - assert(presetGUIDArraySize <= presetGUIDCount); - - presetFound = 0; - for (i = 0; i < presetGUIDArraySize; i++) - { - if (inputPresetGuid == presetGUIDArray[i]) - { - presetFound = 1; - break; - } - } - - delete[] presetGUIDArray; - - if (presetFound) - return NV_ENC_SUCCESS; - else - return NV_ENC_ERR_INVALID_PARAM; -} - -NVENCSTATUS CNvHWEncoder::CreateEncoder(const EncodeConfig *pEncCfg) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (pEncCfg == NULL) - { - return NV_ENC_ERR_INVALID_PARAM; - } - - m_uCurWidth = pEncCfg->width; - m_uCurHeight = pEncCfg->height; - - m_uMaxWidth = (pEncCfg->maxWidth > 0 ? pEncCfg->maxWidth : pEncCfg->width); - m_uMaxHeight = (pEncCfg->maxHeight > 0 ? pEncCfg->maxHeight : pEncCfg->height); - - if ((m_uCurWidth > m_uMaxWidth) || (m_uCurHeight > m_uMaxHeight)) { - return NV_ENC_ERR_INVALID_PARAM; - } - - if (!pEncCfg->width || !pEncCfg->height) - { - return NV_ENC_ERR_INVALID_PARAM; - } - - GUID inputCodecGUID = pEncCfg->codec == NV_ENC_H264 ? NV_ENC_CODEC_H264_GUID : NV_ENC_CODEC_HEVC_GUID; - nvStatus = ValidateEncodeGUID(inputCodecGUID); - if (nvStatus != NV_ENC_SUCCESS) - { - PRINTERR("codec not supported \n"); - return nvStatus; - } - - codecGUID = inputCodecGUID; - - m_stCreateEncodeParams.encodeGUID = inputCodecGUID; - m_stCreateEncodeParams.presetGUID = pEncCfg->presetGUID; - m_stCreateEncodeParams.encodeWidth = pEncCfg->width; - m_stCreateEncodeParams.encodeHeight = pEncCfg->height; - - m_stCreateEncodeParams.darWidth = pEncCfg->width; - m_stCreateEncodeParams.darHeight = pEncCfg->height; - m_stCreateEncodeParams.frameRateNum = pEncCfg->fps; - m_stCreateEncodeParams.frameRateDen = 1; -#if defined(NV_WINDOWS) - m_stCreateEncodeParams.enableEncodeAsync = 1; -#else - m_stCreateEncodeParams.enableEncodeAsync = 0; -#endif - m_stCreateEncodeParams.enablePTD = 1; - m_stCreateEncodeParams.reportSliceOffsets = 0; - m_stCreateEncodeParams.enableSubFrameWrite = 0; - m_stCreateEncodeParams.encodeConfig = &m_stEncodeConfig; - m_stCreateEncodeParams.maxEncodeWidth = m_uMaxWidth; - m_stCreateEncodeParams.maxEncodeHeight = m_uMaxHeight; - - // apply preset - NV_ENC_PRESET_CONFIG stPresetCfg; - memset(&stPresetCfg, 0, sizeof(NV_ENC_PRESET_CONFIG)); - SET_VER(stPresetCfg, NV_ENC_PRESET_CONFIG); - SET_VER(stPresetCfg.presetCfg, NV_ENC_CONFIG); - - nvStatus = m_pEncodeAPI->nvEncGetEncodePresetConfig(m_hEncoder, m_stCreateEncodeParams.encodeGUID, m_stCreateEncodeParams.presetGUID, &stPresetCfg); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - return nvStatus; - } - memcpy(&m_stEncodeConfig, &stPresetCfg.presetCfg, sizeof(NV_ENC_CONFIG)); - - m_stEncodeConfig.gopLength = pEncCfg->gopLength; - m_stEncodeConfig.frameIntervalP = pEncCfg->numB + 1; - if (pEncCfg->pictureStruct == NV_ENC_PIC_STRUCT_FRAME) - { - m_stEncodeConfig.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME; - } - else - { - m_stEncodeConfig.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD; - } - - m_stEncodeConfig.mvPrecision = NV_ENC_MV_PRECISION_QUARTER_PEL; - - if (pEncCfg->bitrate || pEncCfg->vbvMaxBitrate) - { - m_stEncodeConfig.rcParams.rateControlMode = (NV_ENC_PARAMS_RC_MODE)pEncCfg->rcMode; - m_stEncodeConfig.rcParams.averageBitRate = pEncCfg->bitrate; - m_stEncodeConfig.rcParams.maxBitRate = pEncCfg->vbvMaxBitrate; - m_stEncodeConfig.rcParams.vbvBufferSize = pEncCfg->vbvSize; - m_stEncodeConfig.rcParams.vbvInitialDelay = pEncCfg->vbvSize * 9 / 10; - } - else - { - m_stEncodeConfig.rcParams.rateControlMode = NV_ENC_PARAMS_RC_CONSTQP; - } - - if (pEncCfg->rcMode == 0) - { - m_stEncodeConfig.rcParams.constQP.qpInterP = pEncCfg->presetGUID == NV_ENC_PRESET_LOSSLESS_HP_GUID? 0 : pEncCfg->qp; - m_stEncodeConfig.rcParams.constQP.qpInterB = pEncCfg->presetGUID == NV_ENC_PRESET_LOSSLESS_HP_GUID? 0 : pEncCfg->qp; - m_stEncodeConfig.rcParams.constQP.qpIntra = pEncCfg->presetGUID == NV_ENC_PRESET_LOSSLESS_HP_GUID? 0 : pEncCfg->qp; - } - - if (pEncCfg->isYuv444) - { - m_stEncodeConfig.encodeCodecConfig.h264Config.chromaFormatIDC = 3; - } - else - { - m_stEncodeConfig.encodeCodecConfig.h264Config.chromaFormatIDC = 1; - } - - if (pEncCfg->intraRefreshEnableFlag) - { - if (pEncCfg->codec == NV_ENC_HEVC) - { - m_stEncodeConfig.encodeCodecConfig.hevcConfig.enableIntraRefresh = 1; - m_stEncodeConfig.encodeCodecConfig.hevcConfig.intraRefreshPeriod = pEncCfg->intraRefreshPeriod; - m_stEncodeConfig.encodeCodecConfig.hevcConfig.intraRefreshCnt = pEncCfg->intraRefreshDuration; - } - else - { - m_stEncodeConfig.encodeCodecConfig.h264Config.enableIntraRefresh = 1; - m_stEncodeConfig.encodeCodecConfig.h264Config.intraRefreshPeriod = pEncCfg->intraRefreshPeriod; - m_stEncodeConfig.encodeCodecConfig.h264Config.intraRefreshCnt = pEncCfg->intraRefreshDuration; - } - } - - if (pEncCfg->invalidateRefFramesEnableFlag) - { - if (pEncCfg->codec == NV_ENC_HEVC) - { - m_stEncodeConfig.encodeCodecConfig.hevcConfig.maxNumRefFramesInDPB = 16; - } - else - { - m_stEncodeConfig.encodeCodecConfig.h264Config.maxNumRefFrames = 16; - } - } - - if (pEncCfg->qpDeltaMapFile) - { - m_stEncodeConfig.rcParams.enableExtQPDeltaMap = 1; - } - if (pEncCfg->codec == NV_ENC_H264) - { - m_stEncodeConfig.encodeCodecConfig.h264Config.idrPeriod = pEncCfg->gopLength; - } - else if (pEncCfg->codec == NV_ENC_HEVC) - { - m_stEncodeConfig.encodeCodecConfig.hevcConfig.idrPeriod = pEncCfg->gopLength; - } - - nvStatus = m_pEncodeAPI->nvEncInitializeEncoder(m_hEncoder, &m_stCreateEncodeParams); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - m_bEncoderInitialized = true; - - return nvStatus; -} - -GUID CNvHWEncoder::GetPresetGUID(char* encoderPreset, int codec) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - GUID presetGUID = NV_ENC_PRESET_DEFAULT_GUID; - - if (encoderPreset && (stricmp(encoderPreset, "hq") == 0)) - { - presetGUID = NV_ENC_PRESET_HQ_GUID; - } - else if (encoderPreset && (stricmp(encoderPreset, "lowLatencyHP") == 0)) - { - presetGUID = NV_ENC_PRESET_LOW_LATENCY_HP_GUID; - } - else if (encoderPreset && (stricmp(encoderPreset, "hp") == 0)) - { - presetGUID = NV_ENC_PRESET_HP_GUID; - } - else if (encoderPreset && (stricmp(encoderPreset, "lowLatencyHQ") == 0)) - { - presetGUID = NV_ENC_PRESET_LOW_LATENCY_HQ_GUID; - } - else if (encoderPreset && (stricmp(encoderPreset, "lossless") == 0)) - { - presetGUID = NV_ENC_PRESET_LOSSLESS_HP_GUID; - } - else - { - presetGUID = NV_ENC_PRESET_DEFAULT_GUID; - } - - GUID inputCodecGUID = codec == NV_ENC_H264 ? NV_ENC_CODEC_H264_GUID : NV_ENC_CODEC_HEVC_GUID; - nvStatus = ValidatePresetGUID(presetGUID, inputCodecGUID); - if (nvStatus != NV_ENC_SUCCESS) - { - presetGUID = NV_ENC_PRESET_DEFAULT_GUID; - PRINTERR("Unsupported preset guid %s\n", encoderPreset); - } - - return presetGUID; -} - -NVENCSTATUS CNvHWEncoder::ProcessOutput(const EncodeBuffer *pEncodeBuffer, DataPacket* dataPacket) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - - if (pEncodeBuffer->stOutputBfr.hBitstreamBuffer == NULL && pEncodeBuffer->stOutputBfr.bEOSFlag == FALSE) - { - return NV_ENC_ERR_INVALID_PARAM; - } - - if (pEncodeBuffer->stOutputBfr.bWaitOnEvent == TRUE) - { - if (!pEncodeBuffer->stOutputBfr.hOutputEvent) - { - return NV_ENC_ERR_INVALID_PARAM; - } -#if defined(NV_WINDOWS) - WaitForSingleObject(pEncodeBuffer->stOutputBfr.hOutputEvent, INFINITE); -#endif - } - - if (pEncodeBuffer->stOutputBfr.bEOSFlag) - return NV_ENC_SUCCESS; - - nvStatus = NV_ENC_SUCCESS; - NV_ENC_LOCK_BITSTREAM lockBitstreamData; - memset(&lockBitstreamData, 0, sizeof(lockBitstreamData)); - SET_VER(lockBitstreamData, NV_ENC_LOCK_BITSTREAM); - lockBitstreamData.outputBitstream = pEncodeBuffer->stOutputBfr.hBitstreamBuffer; - lockBitstreamData.doNotWait = false; - - nvStatus = m_pEncodeAPI->nvEncLockBitstream(m_hEncoder, &lockBitstreamData); - if (nvStatus == NV_ENC_SUCCESS) - { - dataPacket->size = lockBitstreamData.bitstreamSizeInBytes; - memcpy(dataPacket->data, lockBitstreamData.bitstreamBufferPtr, dataPacket->size); - nvStatus = m_pEncodeAPI->nvEncUnlockBitstream(m_hEncoder, pEncodeBuffer->stOutputBfr.hBitstreamBuffer); - } - else - { - PRINTERR("lock bitstream function failed \n"); - } - - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::Initialize(void* device, NV_ENC_DEVICE_TYPE deviceType) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - MYPROC nvEncodeAPICreateInstance; // function pointer to create instance in nvEncodeAPI - -#if defined(NV_WINDOWS) -#if defined (_WIN64) - m_hinstLib = LoadLibrary(TEXT("nvEncodeAPI64.dll")); -#else - m_hinstLib = LoadLibrary(TEXT("nvEncodeAPI.dll")); -#endif -#else - m_hinstLib = dlopen("libnvidia-encode.so.1", RTLD_LAZY); -#endif - if (m_hinstLib == NULL) - return NV_ENC_ERR_OUT_OF_MEMORY; - -#if defined(NV_WINDOWS) - nvEncodeAPICreateInstance = (MYPROC)GetProcAddress(m_hinstLib, "NvEncodeAPICreateInstance"); -#else - nvEncodeAPICreateInstance = (MYPROC)dlsym(m_hinstLib, "NvEncodeAPICreateInstance"); -#endif - - if (nvEncodeAPICreateInstance == NULL) - return NV_ENC_ERR_OUT_OF_MEMORY; - - m_pEncodeAPI = new NV_ENCODE_API_FUNCTION_LIST; - if (m_pEncodeAPI == NULL) - return NV_ENC_ERR_OUT_OF_MEMORY; - - memset(m_pEncodeAPI, 0, sizeof(NV_ENCODE_API_FUNCTION_LIST)); - m_pEncodeAPI->version = NV_ENCODE_API_FUNCTION_LIST_VER; - nvStatus = nvEncodeAPICreateInstance(m_pEncodeAPI); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - nvStatus = NvEncOpenEncodeSessionEx(device, deviceType); - if (nvStatus != NV_ENC_SUCCESS) - return nvStatus; - - return NV_ENC_SUCCESS; -} - -NVENCSTATUS CNvHWEncoder::NvEncEncodeFrame(EncodeBuffer *pEncodeBuffer, NvEncPictureCommand *encPicCommand, - uint32_t width, uint32_t height, NV_ENC_PIC_STRUCT ePicStruct, - int8_t *qpDeltaMapArray, uint32_t qpDeltaMapArraySize) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_PIC_PARAMS encPicParams; - - memset(&encPicParams, 0, sizeof(encPicParams)); - SET_VER(encPicParams, NV_ENC_PIC_PARAMS); - - - encPicParams.inputBuffer = pEncodeBuffer->stInputBfr.hInputSurface; - encPicParams.bufferFmt = pEncodeBuffer->stInputBfr.bufferFmt; - encPicParams.inputWidth = width; - encPicParams.inputHeight = height; - encPicParams.outputBitstream = pEncodeBuffer->stOutputBfr.hBitstreamBuffer; - encPicParams.completionEvent = pEncodeBuffer->stOutputBfr.hOutputEvent; - encPicParams.inputTimeStamp = m_EncodeIdx; - encPicParams.pictureStruct = ePicStruct; - encPicParams.qpDeltaMap = qpDeltaMapArray; - encPicParams.qpDeltaMapSize = qpDeltaMapArraySize; - - - if (encPicCommand) - { - if (encPicCommand->bForceIDR) - { - encPicParams.encodePicFlags |= NV_ENC_PIC_FLAG_FORCEIDR; - } - - if (encPicCommand->bForceIntraRefresh) - { - if (codecGUID == NV_ENC_CODEC_HEVC_GUID) - { - encPicParams.codecPicParams.hevcPicParams.forceIntraRefreshWithFrameCnt = encPicCommand->intraRefreshDuration; - } - else - { - encPicParams.codecPicParams.h264PicParams.forceIntraRefreshWithFrameCnt = encPicCommand->intraRefreshDuration; - } - } - } - - nvStatus = m_pEncodeAPI->nvEncEncodePicture(m_hEncoder, &encPicParams); - if (nvStatus != NV_ENC_SUCCESS && nvStatus != NV_ENC_ERR_NEED_MORE_INPUT) - { - assert(0); - return nvStatus; - } - - m_EncodeIdx++; - - return NV_ENC_SUCCESS; -} - -NVENCSTATUS CNvHWEncoder::NvEncFlushEncoderQueue(void *hEOSEvent) -{ - NVENCSTATUS nvStatus = NV_ENC_SUCCESS; - NV_ENC_PIC_PARAMS encPicParams; - memset(&encPicParams, 0, sizeof(encPicParams)); - SET_VER(encPicParams, NV_ENC_PIC_PARAMS); - encPicParams.encodePicFlags = NV_ENC_PIC_FLAG_EOS; - encPicParams.completionEvent = hEOSEvent; - nvStatus = m_pEncodeAPI->nvEncEncodePicture(m_hEncoder, &encPicParams); - if (nvStatus != NV_ENC_SUCCESS) - { - assert(0); - } - return nvStatus; -} - -NVENCSTATUS CNvHWEncoder::ParseArguments(EncodeConfig *encodeConfig, int argc, char *argv[]) -{ - for (int i = 1; i < argc; i++) - { - if (stricmp(argv[i], "-bmpfilePath") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->inputFilePath = argv[i]; - } - else if (stricmp(argv[i], "-i") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->inputFileName = argv[i]; - } - else if (stricmp(argv[i], "-o") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->outputFileName = argv[i]; - } - else if (stricmp(argv[i], "-size") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->width) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->height) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 2]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-maxSize") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->maxWidth) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->maxHeight) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 2]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-bitrate") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->bitrate) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-vbvMaxBitrate") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->vbvMaxBitrate) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-vbvSize") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->vbvSize) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-fps") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->fps) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-startf") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->startFrameIdx) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-endf") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->endFrameIdx) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-rcmode") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->rcMode) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-goplength") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->gopLength) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-numB") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->numB) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-qp") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->qp) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-preset") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->encoderPreset = argv[i]; - } - else if (stricmp(argv[i], "-devicetype") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->deviceType) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-codec") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->codec) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-encCmdFile") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->encCmdFileName = argv[i]; - } - else if (stricmp(argv[i], "-intraRefresh") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->intraRefreshEnableFlag) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-intraRefreshPeriod") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->intraRefreshPeriod) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-intraRefreshDuration") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->intraRefreshDuration) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-picStruct") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->pictureStruct) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-deviceID") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->deviceID) != 1) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-yuv444") == 0) - { - if (++i >= argc || sscanf(argv[i], "%d", &encodeConfig->isYuv444) != 1) - { - fprintf(stderr, "invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - else if (stricmp(argv[i], "-qpDeltaMapFile") == 0) - { - if (++i >= argc) - { - PRINTERR("invalid parameter for %s\n", argv[i - 1]); - return NV_ENC_ERR_INVALID_PARAM; - } - encodeConfig->qpDeltaMapFile = argv[i]; - } - else if (stricmp(argv[i], "-help") == 0) - { - return NV_ENC_ERR_INVALID_PARAM; - } - else - { - PRINTERR("invalid parameter %s\n", argv[i++]); - return NV_ENC_ERR_INVALID_PARAM; - } - } - - return NV_ENC_SUCCESS; -} diff --git a/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.h b/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.h deleted file mode 100644 index a334260df0..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/NvHWEncoder.h +++ /dev/null @@ -1,202 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#include -#include -#include - -#include - -#include "nvEncodeAPI.h" -#include "nvUtils.h" - -#define SET_VER(configStruct, type) {configStruct.version = type##_VER;} - -#if defined (NV_WINDOWS) - #include "d3d9.h" - #define NVENCAPI __stdcall - #pragma warning(disable : 4996) -#elif defined (NV_UNIX) - #include - #include - #define NVENCAPI -#endif - -typedef struct _EncodeConfig -{ - int width; - int height; - int maxWidth; - int maxHeight; - int fps; - int bitrate; - int vbvMaxBitrate; - int vbvSize; - int rcMode; - int qp; - GUID presetGUID; - int codec; - int invalidateRefFramesEnableFlag; - int intraRefreshEnableFlag; - int intraRefreshPeriod; - int intraRefreshDuration; - int deviceType; - int startFrameIdx; - int endFrameIdx; - int gopLength; - int numB; - int pictureStruct; - int deviceID; - int isYuv444; - char *qpDeltaMapFile; - - char* inputFileName; - char* outputFileName; - char* encoderPreset; - char* inputFilePath; - char *encCmdFileName; -}EncodeConfig; - -typedef struct _DataPacket -{ - uint8_t *data; - int size; -}DataPacket; - -typedef struct _EncodeInputBuffer -{ - unsigned int dwWidth; - unsigned int dwHeight; -#if defined (NV_WINDOWS) - IDirect3DSurface9 *pNV12Surface; -#endif - CUdeviceptr pNV12devPtr; - uint32_t uNV12Stride; - CUdeviceptr pNV12TempdevPtr; - uint32_t uNV12TempStride; - void* nvRegisteredResource; - NV_ENC_INPUT_PTR hInputSurface; - NV_ENC_BUFFER_FORMAT bufferFmt; -}EncodeInputBuffer; - -typedef struct _EncodeOutputBuffer -{ - unsigned int dwBitstreamBufferSize; - NV_ENC_OUTPUT_PTR hBitstreamBuffer; - HANDLE hOutputEvent; - bool bWaitOnEvent; - bool bEOSFlag; -}EncodeOutputBuffer; - -typedef struct _EncodeBuffer -{ - EncodeOutputBuffer stOutputBfr; - EncodeInputBuffer stInputBfr; -}EncodeBuffer; - -typedef struct _NvEncPictureCommand -{ - bool bResolutionChangePending; - bool bBitrateChangePending; - bool bForceIDR; - bool bForceIntraRefresh; - bool bInvalidateRefFrames; - - uint32_t newWidth; - uint32_t newHeight; - - uint32_t newBitrate; - uint32_t newVBVSize; - - uint32_t intraRefreshDuration; - - uint32_t numRefFramesToInvalidate; - uint32_t refFrameNumbers[16]; -}NvEncPictureCommand; - -enum -{ - NV_ENC_H264 = 0, - NV_ENC_HEVC = 1, -}; - -class CNvHWEncoder -{ -public: - uint32_t m_EncodeIdx; - uint32_t m_uMaxWidth; - uint32_t m_uMaxHeight; - uint32_t m_uCurWidth; - uint32_t m_uCurHeight; - -protected: - bool m_bEncoderInitialized; - GUID codecGUID; - - NV_ENCODE_API_FUNCTION_LIST* m_pEncodeAPI; - HINSTANCE m_hinstLib; - void *m_hEncoder; - NV_ENC_INITIALIZE_PARAMS m_stCreateEncodeParams; - NV_ENC_CONFIG m_stEncodeConfig; - -public: - NVENCSTATUS NvEncOpenEncodeSession(void* device, uint32_t deviceType); - NVENCSTATUS NvEncGetEncodeGUIDCount(uint32_t* encodeGUIDCount); - NVENCSTATUS NvEncGetEncodeProfileGUIDCount(GUID encodeGUID, uint32_t* encodeProfileGUIDCount); - NVENCSTATUS NvEncGetEncodeProfileGUIDs(GUID encodeGUID, GUID* profileGUIDs, uint32_t guidArraySize, uint32_t* GUIDCount); - NVENCSTATUS NvEncGetEncodeGUIDs(GUID* GUIDs, uint32_t guidArraySize, uint32_t* GUIDCount); - NVENCSTATUS NvEncGetInputFormatCount(GUID encodeGUID, uint32_t* inputFmtCount); - NVENCSTATUS NvEncGetInputFormats(GUID encodeGUID, NV_ENC_BUFFER_FORMAT* inputFmts, uint32_t inputFmtArraySize, uint32_t* inputFmtCount); - NVENCSTATUS NvEncGetEncodeCaps(GUID encodeGUID, NV_ENC_CAPS_PARAM* capsParam, int* capsVal); - NVENCSTATUS NvEncGetEncodePresetCount(GUID encodeGUID, uint32_t* encodePresetGUIDCount); - NVENCSTATUS NvEncGetEncodePresetGUIDs(GUID encodeGUID, GUID* presetGUIDs, uint32_t guidArraySize, uint32_t* encodePresetGUIDCount); - NVENCSTATUS NvEncGetEncodePresetConfig(GUID encodeGUID, GUID presetGUID, NV_ENC_PRESET_CONFIG* presetConfig); - NVENCSTATUS NvEncCreateInputBuffer(uint32_t width, uint32_t height, void** inputBuffer, uint32_t isYuv444); - NVENCSTATUS NvEncDestroyInputBuffer(NV_ENC_INPUT_PTR inputBuffer); - NVENCSTATUS NvEncCreateBitstreamBuffer(uint32_t size, void** bitstreamBuffer); - NVENCSTATUS NvEncDestroyBitstreamBuffer(NV_ENC_OUTPUT_PTR bitstreamBuffer); - NVENCSTATUS NvEncLockBitstream(NV_ENC_LOCK_BITSTREAM* lockBitstreamBufferParams); - NVENCSTATUS NvEncUnlockBitstream(NV_ENC_OUTPUT_PTR bitstreamBuffer); - NVENCSTATUS NvEncLockInputBuffer(void* inputBuffer, void** bufferDataPtr, uint32_t* pitch); - NVENCSTATUS NvEncUnlockInputBuffer(NV_ENC_INPUT_PTR inputBuffer); - NVENCSTATUS NvEncGetEncodeStats(NV_ENC_STAT* encodeStats); - NVENCSTATUS NvEncGetSequenceParams(NV_ENC_SEQUENCE_PARAM_PAYLOAD* sequenceParamPayload); - NVENCSTATUS NvEncRegisterAsyncEvent(void** completionEvent); - NVENCSTATUS NvEncUnregisterAsyncEvent(void* completionEvent); - NVENCSTATUS NvEncMapInputResource(void* registeredResource, void** mappedResource); - NVENCSTATUS NvEncUnmapInputResource(NV_ENC_INPUT_PTR mappedInputBuffer); - NVENCSTATUS NvEncDestroyEncoder(); - NVENCSTATUS NvEncInvalidateRefFrames(const NvEncPictureCommand *pEncPicCommand); - NVENCSTATUS NvEncOpenEncodeSessionEx(void* device, NV_ENC_DEVICE_TYPE deviceType); - NVENCSTATUS NvEncRegisterResource(NV_ENC_INPUT_RESOURCE_TYPE resourceType, void* resourceToRegister, uint32_t width, uint32_t height, uint32_t pitch, void** registeredResource); - NVENCSTATUS NvEncUnregisterResource(NV_ENC_REGISTERED_PTR registeredRes); - NVENCSTATUS NvEncReconfigureEncoder(const NvEncPictureCommand *pEncPicCommand); - NVENCSTATUS NvEncFlushEncoderQueue(void *hEOSEvent); - - CNvHWEncoder(); - virtual ~CNvHWEncoder(); - NVENCSTATUS Initialize(void* device, NV_ENC_DEVICE_TYPE deviceType); - NVENCSTATUS Deinitialize(); - NVENCSTATUS NvEncEncodeFrame(EncodeBuffer *pEncodeBuffer, NvEncPictureCommand *encPicCommand, - uint32_t width, uint32_t height, - NV_ENC_PIC_STRUCT ePicStruct = NV_ENC_PIC_STRUCT_FRAME, - int8_t *qpDeltaMapArray = NULL, uint32_t qpDeltaMapArraySize = 0); - NVENCSTATUS CreateEncoder(const EncodeConfig *pEncCfg); - GUID GetPresetGUID(char* encoderPreset, int codec); - NVENCSTATUS ProcessOutput(const EncodeBuffer *pEncodeBuffer, DataPacket* dataPacket); - NVENCSTATUS FlushEncoder(); - NVENCSTATUS ValidateEncodeGUID(GUID inputCodecGuid); - NVENCSTATUS ValidatePresetGUID(GUID presetCodecGuid, GUID inputCodecGuid); - static NVENCSTATUS ParseArguments(EncodeConfig *encodeConfig, int argc, char *argv[]); -}; - -typedef NVENCSTATUS (NVENCAPI *MYPROC)(NV_ENCODE_API_FUNCTION_LIST*); diff --git a/rdp-acceleraed/Server/NvEncoder/nvCPUOPSys.h b/rdp-acceleraed/Server/NvEncoder/nvCPUOPSys.h deleted file mode 100644 index 23e666dd65..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/nvCPUOPSys.h +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#ifndef NVCPUOPSYS_H -#define NVCPUOPSYS_H - - -#if defined(_WIN32) || defined(_WIN16) -# define NV_WINDOWS -#endif - -#if (defined(__unix__) || defined(__unix) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(__DJGPP__) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */ -# define NV_UNIX -#endif /* defined(__unix__) */ - -#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE) -# define NV_LINUX -#endif /* defined(__linux__) */ - -#endif diff --git a/rdp-acceleraed/Server/NvEncoder/nvEncodeAPI.h b/rdp-acceleraed/Server/NvEncoder/nvEncodeAPI.h deleted file mode 100644 index 11df6d5f5c..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/nvEncodeAPI.h +++ /dev/null @@ -1,2965 +0,0 @@ -/* - * Copyright 1993-2014 NVIDIA Corporation. All rights reserved. - * - * NOTICE TO LICENSEE: - * - * This source code and/or documentation ("Licensed Deliverables") are - * subject to NVIDIA intellectual property rights under U.S. and - * international Copyright laws. - * - * These Licensed Deliverables contained herein is PROPRIETARY and - * CONFIDENTIAL to NVIDIA and is being provided under the terms and - * conditions of a form of NVIDIA software license agreement by and - * between NVIDIA and Licensee ("License Agreement") or electronically - * accepted by Licensee. Notwithstanding any terms or conditions to - * the contrary in the License Agreement, reproduction or disclosure - * of the Licensed Deliverables to any third party without the express - * written consent of NVIDIA is prohibited. - * - * ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, - * DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, - * “MATERIALS”) ARE BEING PROVIDED “AS IS.” WITHOUT EXPRESS OR IMPLIED - * WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH REGARD - * TO THESE LICENSED DELIVERABLES, INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. - * NOTWITHSTANDING ANY TERMS OR CONDITIONS TO THE CONTRARY IN THE LICENSE - * AGREEMENT, IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING - * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, - * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION - * WITH THE USE OR PERFORMANCE OF THESE LICENSED DELIVERABLES. - * - * Information furnished is believed to be accurate and reliable. However, - * NVIDIA assumes no responsibility for the consequences of use of such - * information nor for any infringement of patents or other rights of - * third parties, which may result from its use. No License is granted - * by implication or otherwise under any patent or patent rights of NVIDIA - * Corporation. Specifications mentioned in the software are subject to - * change without notice. This publication supersedes and replaces all - * other information previously supplied. - * - * NVIDIA Corporation products are not authorized for use as critical - * components in life support devices or systems without express written - * approval of NVIDIA Corporation. - * - * U.S. Government End Users. These Licensed Deliverables are a - * "commercial item" as that term is defined at 48 C.F.R. 2.101 (OCT - * 1995), consisting of "commercial computer software" and "commercial - * computer software documentation" as such terms are used in 48 - * C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Government - * only as a commercial end item. Consistent with 48 C.F.R.12.212 and - * 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), all - * U.S. Government End Users acquire the Licensed Deliverables with - * only those rights set forth herein. - * - * Any use of the Licensed Deliverables in individual and commercial - * software must include, in the user documentation and internal - * comments to the code, the above Disclaimer and U.S. Government End - * Users Notice. - */ - -/** - * \file nvEncodeAPI.h - * NvEncodeAPI provides a NVENC Video Encoding interface to NVIDIA GPU devices based on the Kepler architecture. - * \date 2011-2013 - * This file contains the interface constants, structure definitions and function prototypes. - */ - -#ifndef _NV_ENCODEAPI_H_ -#define _NV_ENCODEAPI_H_ - -#include - -#ifdef _WIN32 -#include -#endif - -#ifdef _MSC_VER -#ifndef _STDINT -typedef __int32 int32_t; -typedef unsigned __int32 uint32_t; -typedef __int64 int64_t; -typedef unsigned __int64 uint64_t; -typedef signed char int8_t; -typedef unsigned char uint8_t; -typedef short int16_t; -typedef unsigned short uint16_t; -#endif -#else -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup ENCODER_STRUCTURE NvEncodeAPI Data structures - * @{ - */ - -#ifdef _WIN32 -#define NVENCAPI __stdcall -typedef RECT NVENC_RECT; -#else -#define NVENCAPI -// ========================================================================================= -#ifndef GUID -/*! - * \struct GUID - * Abstracts the GUID structure for non-windows platforms. - */ -// ========================================================================================= -typedef struct -{ - uint32_t Data1; /**< [in]: Specifies the first 8 hexadecimal digits of the GUID. */ - uint16_t Data2; /**< [in]: Specifies the first group of 4 hexadecimal digits. */ - uint16_t Data3; /**< [in]: Specifies the second group of 4 hexadecimal digits. */ - uint8_t Data4[8]; /**< [in]: Array of 8 bytes. The first 2 bytes contain the third group of 4 hexadecimal digits. - The remaining 6 bytes contain the final 12 hexadecimal digits. */ -} GUID; -#endif // GUID - -/** - * \struct _NVENC_RECT - * Defines a Rectangle. Used in ::NV_ENC_PREPROCESS_FRAME. - */ -typedef struct _NVENC_RECT -{ - uint32_t left; /**< [in]: X coordinate of the upper left corner of rectangular area to be specified. */ - uint32_t top; /**< [in]: Y coordinate of the upper left corner of the rectangular area to be specified. */ - uint32_t right; /**< [in]: X coordinate of the bottom right corner of the rectangular area to be specified. */ - uint32_t bottom; /**< [in]: Y coordinate of the bottom right corner of the rectangular area to be specified. */ -} NVENC_RECT; - -#endif // _WIN32 - -/** @} */ /* End of GUID and NVENC_RECT structure grouping*/ - -typedef void* NV_ENC_INPUT_PTR; /**< NVENCODE API input buffer */ -typedef void* NV_ENC_OUTPUT_PTR; /**< NVENCODE API output buffer*/ -typedef void* NV_ENC_REGISTERED_PTR; /**< A Resource that has beenr egistered with NVENCODE API*/ - -#define NVENCAPI_MAJOR_VERSION 5 -#define NVENCAPI_MINOR_VERSION 0 - -#define NVENCAPI_VERSION ((NVENCAPI_MAJOR_VERSION << 4) | (NVENCAPI_MINOR_VERSION)) - -/** - * Macro to generate per-structure version for use with API. - */ -#define NVENCAPI_STRUCT_VERSION(typeName, ver) (uint32_t)(sizeof(typeName) | ((ver)<<16) | (NVENCAPI_VERSION << 24)) - - -#define NVENC_INFINITE_GOPLENGTH 0xffffffff - -#define NV_MAX_SEQ_HDR_LEN (512) - -// ========================================================================================= -// Encode Codec GUIDS supported by the NvEncodeAPI interface. -// ========================================================================================= - -// {6BC82762-4E63-4ca4-AA85-1E50F321F6BF} -static const GUID NV_ENC_CODEC_H264_GUID = -{ 0x6bc82762, 0x4e63, 0x4ca4, { 0xaa, 0x85, 0x1e, 0x50, 0xf3, 0x21, 0xf6, 0xbf } }; - -// {790CDC88-4522-4d7b-9425-BDA9975F7603} -static const GUID NV_ENC_CODEC_HEVC_GUID = -{ 0x790cdc88, 0x4522, 0x4d7b, { 0x94, 0x25, 0xbd, 0xa9, 0x97, 0x5f, 0x76, 0x3 } }; - - - -// ========================================================================================= -// * Encode Profile GUIDS supported by the NvEncodeAPI interface. -// ========================================================================================= - -// {BFD6F8E7-233C-4341-8B3E-4818523803F4} -static const GUID NV_ENC_CODEC_PROFILE_AUTOSELECT_GUID = -{ 0xbfd6f8e7, 0x233c, 0x4341, { 0x8b, 0x3e, 0x48, 0x18, 0x52, 0x38, 0x3, 0xf4 } }; - -// {0727BCAA-78C4-4c83-8C2F-EF3DFF267C6A} -static const GUID NV_ENC_H264_PROFILE_BASELINE_GUID = -{ 0x727bcaa, 0x78c4, 0x4c83, { 0x8c, 0x2f, 0xef, 0x3d, 0xff, 0x26, 0x7c, 0x6a } }; - -// {60B5C1D4-67FE-4790-94D5-C4726D7B6E6D} -static const GUID NV_ENC_H264_PROFILE_MAIN_GUID = -{ 0x60b5c1d4, 0x67fe, 0x4790, { 0x94, 0xd5, 0xc4, 0x72, 0x6d, 0x7b, 0x6e, 0x6d } }; - -// {E7CBC309-4F7A-4b89-AF2A-D537C92BE310} -static const GUID NV_ENC_H264_PROFILE_HIGH_GUID = -{ 0xe7cbc309, 0x4f7a, 0x4b89, { 0xaf, 0x2a, 0xd5, 0x37, 0xc9, 0x2b, 0xe3, 0x10 } }; - -// {7AC663CB-A598-4960-B844-339B261A7D52} -static const GUID NV_ENC_H264_PROFILE_HIGH_444_GUID = -{ 0x7ac663cb, 0xa598, 0x4960, { 0xb8, 0x44, 0x33, 0x9b, 0x26, 0x1a, 0x7d, 0x52 } }; - -// {40847BF5-33F7-4601-9084-E8FE3C1DB8B7} -static const GUID NV_ENC_H264_PROFILE_STEREO_GUID = -{ 0x40847bf5, 0x33f7, 0x4601, { 0x90, 0x84, 0xe8, 0xfe, 0x3c, 0x1d, 0xb8, 0xb7 } }; - -// {CE788D20-AAA9-4318-92BB-AC7E858C8D36} -static const GUID NV_ENC_H264_PROFILE_SVC_TEMPORAL_SCALABILTY = -{ 0xce788d20, 0xaaa9, 0x4318, { 0x92, 0xbb, 0xac, 0x7e, 0x85, 0x8c, 0x8d, 0x36 } }; - -// {AEC1BD87-E85B-48f2-84C3-98BCA6285072} -static const GUID NV_ENC_H264_PROFILE_CONSTRAINED_HIGH_GUID = -{ 0xaec1bd87, 0xe85b, 0x48f2, { 0x84, 0xc3, 0x98, 0xbc, 0xa6, 0x28, 0x50, 0x72 } }; - -// {B514C39A-B55B-40fa-878F-F1253B4DFDEC} -static const GUID NV_ENC_HEVC_PROFILE_MAIN_GUID = -{ 0xb514c39a, 0xb55b, 0x40fa, { 0x87, 0x8f, 0xf1, 0x25, 0x3b, 0x4d, 0xfd, 0xec } }; - - - -// ========================================================================================= -// * Preset GUIDS supported by the NvEncodeAPI interface. -// ========================================================================================= -// {B2DFB705-4EBD-4C49-9B5F-24A777D3E587} -static const GUID NV_ENC_PRESET_DEFAULT_GUID = -{ 0xb2dfb705, 0x4ebd, 0x4c49, { 0x9b, 0x5f, 0x24, 0xa7, 0x77, 0xd3, 0xe5, 0x87 } }; - -// {60E4C59F-E846-4484-A56D-CD45BE9FDDF6} -static const GUID NV_ENC_PRESET_HP_GUID = -{ 0x60e4c59f, 0xe846, 0x4484, { 0xa5, 0x6d, 0xcd, 0x45, 0xbe, 0x9f, 0xdd, 0xf6 } }; - -// {34DBA71D-A77B-4B8F-9C3E-B6D5DA24C012} -static const GUID NV_ENC_PRESET_HQ_GUID = -{ 0x34dba71d, 0xa77b, 0x4b8f, { 0x9c, 0x3e, 0xb6, 0xd5, 0xda, 0x24, 0xc0, 0x12 } }; - -// {82E3E450-BDBB-4e40-989C-82A90DF9EF32} -static const GUID NV_ENC_PRESET_BD_GUID = -{ 0x82e3e450, 0xbdbb, 0x4e40, { 0x98, 0x9c, 0x82, 0xa9, 0xd, 0xf9, 0xef, 0x32 } }; - -// {49DF21C5-6DFA-4feb-9787-6ACC9EFFB726} -static const GUID NV_ENC_PRESET_LOW_LATENCY_DEFAULT_GUID = -{ 0x49df21c5, 0x6dfa, 0x4feb, { 0x97, 0x87, 0x6a, 0xcc, 0x9e, 0xff, 0xb7, 0x26 } }; - -// {C5F733B9-EA97-4cf9-BEC2-BF78A74FD105} -static const GUID NV_ENC_PRESET_LOW_LATENCY_HQ_GUID = -{ 0xc5f733b9, 0xea97, 0x4cf9, { 0xbe, 0xc2, 0xbf, 0x78, 0xa7, 0x4f, 0xd1, 0x5 } }; - -// {67082A44-4BAD-48FA-98EA-93056D150A58} -static const GUID NV_ENC_PRESET_LOW_LATENCY_HP_GUID = -{ 0x67082a44, 0x4bad, 0x48fa, { 0x98, 0xea, 0x93, 0x5, 0x6d, 0x15, 0xa, 0x58 } }; - -// {D5BFB716-C604-44e7-9BB8-DEA5510FC3AC} -static const GUID NV_ENC_PRESET_LOSSLESS_DEFAULT_GUID = -{ 0xd5bfb716, 0xc604, 0x44e7, { 0x9b, 0xb8, 0xde, 0xa5, 0x51, 0xf, 0xc3, 0xac } }; - -// {149998E7-2364-411d-82EF-179888093409} -static const GUID NV_ENC_PRESET_LOSSLESS_HP_GUID = -{ 0x149998e7, 0x2364, 0x411d, { 0x82, 0xef, 0x17, 0x98, 0x88, 0x9, 0x34, 0x9 } }; - -/** - * \addtogroup ENCODER_STRUCTURE NvEncodeAPI Data structures - * @{ - */ - -/** - * Input frame encode modes - */ -typedef enum _NV_ENC_PARAMS_FRAME_FIELD_MODE -{ - NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME = 0x01, /**< Frame mode */ - NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD = 0x02, /**< Field mode */ - NV_ENC_PARAMS_FRAME_FIELD_MODE_MBAFF = 0x03 /**< MB adaptive frame/field */ -} NV_ENC_PARAMS_FRAME_FIELD_MODE; - -/** - * Rate Control Modes - */ -typedef enum _NV_ENC_PARAMS_RC_MODE -{ - NV_ENC_PARAMS_RC_CONSTQP = 0x0, /**< Constant QP mode */ - NV_ENC_PARAMS_RC_VBR = 0x1, /**< Variable bitrate mode */ - NV_ENC_PARAMS_RC_CBR = 0x2, /**< Constant bitrate mode */ - NV_ENC_PARAMS_RC_VBR_MINQP = 0x4, /**< Variable bitrate mode with MinQP */ - NV_ENC_PARAMS_RC_2_PASS_QUALITY = 0x8, /**< Multi pass encoding optimized for image quality and works only with low latency mode */ - NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP = 0x10, /**< Multi pass encoding optimized for maintaining frame size and works only with low latency mode */ - NV_ENC_PARAMS_RC_2_PASS_VBR = 0x20 /**< Multi pass VBR */ -} NV_ENC_PARAMS_RC_MODE; - -#define NV_ENC_PARAMS_RC_CBR2 NV_ENC_PARAMS_RC_CBR /**< Deprecated */ - -/** - * Input picture structure - */ -typedef enum _NV_ENC_PIC_STRUCT -{ - NV_ENC_PIC_STRUCT_FRAME = 0x01, /**< Progressive frame */ - NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM = 0x02, /**< Field encoding top field first */ - NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP = 0x03 /**< Field encoding bottom field first */ -} NV_ENC_PIC_STRUCT; - -/** - * Input picture type - */ -typedef enum _NV_ENC_PIC_TYPE -{ - NV_ENC_PIC_TYPE_P = 0x0, /**< Forward predicted */ - NV_ENC_PIC_TYPE_B = 0x01, /**< Bi-directionally predicted picture */ - NV_ENC_PIC_TYPE_I = 0x02, /**< Intra predicted picture */ - NV_ENC_PIC_TYPE_IDR = 0x03, /**< IDR picture */ - NV_ENC_PIC_TYPE_BI = 0x04, /**< Bi-directionally predicted with only Intra MBs */ - NV_ENC_PIC_TYPE_SKIPPED = 0x05, /**< Picture is skipped */ - NV_ENC_PIC_TYPE_INTRA_REFRESH = 0x06, /**< First picture in intra refresh cycle */ - NV_ENC_PIC_TYPE_UNKNOWN = 0xFF /**< Picture type unknown */ -} NV_ENC_PIC_TYPE; - -/** - * Motion vector precisions - */ -typedef enum _NV_ENC_MV_PRECISION -{ - NV_ENC_MV_PRECISION_DEFAULT = 0x0, /** NvI1 - I2 --> NvI2 - I3 --> NvI3 - - d) After returning from ::NvEncEncodePicture() call , the client must queue the output - bitstream processing work to the secondary thread. The output bitstream processing - for asynchronous mode consist of first waiting on completion event(E1, E2..) - and then locking the output bitstream buffer(O1, O2..) for reading the encoded - data. The work queued to the secondary thread by the client is in the following order - (I1, O1, E1) - (I2, O2, E2) - (I3, O3, E3) - Note they are in the same order in which client calls ::NvEncEncodePicture() API - in \p step a). - - e) NvEncodeAPI interface will do the re-ordering such that Encoder HW will receive - the following encode commands: - (NvI1, O1, E1) ---P1 Frame - (NvI3, O2, E2) ---P3 Frame - (NvI2, O3, E3) ---B2 frame - - f) After the encoding operations are completed, the events will be signalled - by NvEncodeAPI interface in the following order : - (O1, E1) ---P1 Frame ,output bitstream copied to O1 and event E1 signalled. - (O2, E2) ---P3 Frame ,output bitstream copied to O2 and event E2 signalled. - (O3, E3) ---B2 Frame ,output bitstream copied to O3 and event E3 signalled. - - g) The client must lock the bitstream data using ::NvEncLockBitstream() API in - the order O1,O2,O3 to read the encoded data, after waiting for the events - to be signalled in the same order i.e E1, E2 and E3.The output processing is - done in the secondary thread in the following order: - Waits on E1, copies encoded bitstream from O1 - Waits on E2, copies encoded bitstream from O2 - Waits on E3, copies encoded bitstream from O3 - - -Note the client will receive the events signalling and output buffer in the - same order in which they have submitted for encoding. - -Note the LockBitstream will have picture type field which will notify the - output picture type to the clients. - -Note the input, output buffer and the output completion eventare free to be - reused once NvEncodeAPI interfaced has signalled the event and the client has - copied the data from the output buffer. - - * \endcode - * - *\par Synchronous Encoding - * The client can enable synchronous mode of encoding by setting - * NV_ENC_INITIALIZE_PARAMS::enableEncodeAsync to 0 in ::NvEncInitializeEncoder() API. - * The NvEncodeAPI interface may return ::NV_ENC_ERR_NEED_MORE_INPUT error code for - * some ::NvEncEncodePicture() API calls when NV_ENC_INITIALIZE_PARAMS::enablePTD - * is set to 1, but the client must not treat it as a fatal error. The NvEncodeAPI - * interface might not be able to submit an input picture buffer for encoding - * immediately due to re-ordering for B frames. The NvEncodeAPI interface cannot - * submit the input picture which is decided to be encoded as B frame as it waits - * for backward reference from temporally subsequent frames. This input picture - * is buffered internally and waits for more input picture to arrive. The client - * must not call ::NvEncLockBitstream() API on the output buffers whose - * ::NvEncEncodePicture() API returns ::NV_ENC_ERR_NEED_MORE_INPUT. The client must - * wait for the NvEncodeAPI interface to return ::NV_ENC_SUCCESS before locking the - * output bitstreams to read the encoded bitstream data. The following example - * explains the scenario with synchronous encoding with 2 B frames. - *\code - The below example shows how synchronous encoding works in case of 1 B frames - ----------------------------------------------------------------------------- - Suppose the client allocated 4 input buffers(I1,I2..), 4 output buffers(O1,O2..) - and 4 completion events(E1, E2, ...). The NvEncodeAPI interface will need to - keep a copy of the input buffers for re-ordering and it allocates following - internal buffers (NvI1, NvI2...). These internal buffers are managed by NvEncodeAPI - and the client is not responsible for the allocating or freeing the memory of - the internal buffers. - - The client calls ::NvEncEncodePicture() API with input buffer I1 and output buffer O1. - The NvEncodeAPI decides to encode I1 as P frame and submits it to encoder - HW and returns ::NV_ENC_SUCCESS. - The client can now read the encoded data by locking the output O1 by calling - NvEncLockBitstream API. - - The client calls ::NvEncEncodePicture() API with input buffer I2 and output buffer O2. - The NvEncodeAPI decides to encode I2 as B frame and buffers I2 by copying it - to internal buffer and returns ::NV_ENC_ERR_NEED_MORE_INPUT. - The error is not fatal and it notifies client that it cannot read the encoded - data by locking the output O2 by calling ::NvEncLockBitstream() API without submitting - more work to the NvEncodeAPI interface. - - The client calls ::NvEncEncodePicture() with input buffer I3 and output buffer O3. - The NvEncodeAPI decides to encode I3 as P frame and it first submits I3 for - encoding which will be used as backward reference frame for I2. - The NvEncodeAPI then submits I2 for encoding and returns ::NV_ENC_SUCESS. Both - the submission are part of the same ::NvEncEncodePicture() function call. - The client can now read the encoded data for both the frames by locking the output - O2 followed by O3 ,by calling ::NvEncLockBitstream() API. - - The client must always lock the output in the same order in which it has submitted - to receive the encoded bitstream in correct encoding order. - - * \endcode - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] encodePicParams - * Pointer to the ::_NV_ENC_PIC_PARAMS structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_ENCODER_BUSY \n - * ::NV_ENC_ERR_NEED_MORE_INPUT \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncEncodePicture (void* encoder, NV_ENC_PIC_PARAMS* encodePicParams); - - -// NvEncLockBitstream -/** - * \brief Lock output bitstream buffer - * - * This function is used to lock the bitstream buffer to read the encoded data. - * The client can only access the encoded data by calling this function. - * The pointer to client accessible encoded data is returned in the - * NV_ENC_LOCK_BITSTREAM::bitstreamBufferPtr field. The size of the encoded data - * in the output buffer is returned in the NV_ENC_LOCK_BITSTREAM::bitstreamSizeInBytes - * The NvEncodeAPI interface also returns the output picture type and picture structure - * of the encoded frame in NV_ENC_LOCK_BITSTREAM::pictureType and - * NV_ENC_LOCK_BITSTREAM::pictureStruct fields respectively. If the client has - * set NV_ENC_LOCK_BITSTREAM::doNotWait to 1, the function might return - * ::NV_ENC_ERR_LOCK_BUSY if client is operating in synchronous mode. This is not - * a fatal failure if NV_ENC_LOCK_BITSTREAM::doNotWait is set to 1. In the above case the client can - * retry the function after few milliseconds. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] lockBitstreamBufferParams - * Pointer to the ::_NV_ENC_LOCK_BITSTREAM structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_LOCK_BUSY \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncLockBitstream (void* encoder, NV_ENC_LOCK_BITSTREAM* lockBitstreamBufferParams); - - -// NvEncUnlockBitstream -/** - * \brief Unlock the output bitstream buffer - * - * This function is used to unlock the output bitstream buffer after the client - * has read the encoded data from output buffer. The client must call this function - * to unlock the output buffer which it has previously locked using ::NvEncLockBitstream() - * function. Using a locked bitstream buffer in ::NvEncEncodePicture() API will cause - * the function to fail. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] bitstreamBuffer - * bitstream buffer pointer being unlocked - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncUnlockBitstream (void* encoder, NV_ENC_OUTPUT_PTR bitstreamBuffer); - - -// NvLockInputBuffer -/** - * \brief Locks an input buffer - * - * This function is used to lock the input buffer to load the uncompressed YUV - * pixel data into input buffer memory. The client must pass the NV_ENC_INPUT_PTR - * it had previously allocated using ::NvEncCreateInputBuffer()in the - * NV_ENC_LOCK_INPUT_BUFFER::inputBuffer field. - * The NvEncodeAPI interface returns pointer to client accessible input buffer - * memory in NV_ENC_LOCK_INPUT_BUFFER::bufferDataPtr field. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] lockInputBufferParams - * Pointer to the ::_NV_ENC_LOCK_INPUT_BUFFER structure - * - * \return - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_LOCK_BUSY \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncLockInputBuffer (void* encoder, NV_ENC_LOCK_INPUT_BUFFER* lockInputBufferParams); - - -// NvUnlockInputBuffer -/** - * \brief Unlocks the input buffer - * - * This function is used to unlock the input buffer memory previously locked for - * uploading YUV pixel data. The input buffer must be unlocked before being used - * again for encoding, otherwise NvEncodeAPI will fail the ::NvEncEncodePicture() - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in] inputBuffer - * Pointer to the input buffer that is being unlocked. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - * - */ -NVENCSTATUS NVENCAPI NvEncUnlockInputBuffer (void* encoder, NV_ENC_INPUT_PTR inputBuffer); - - -// NvEncGetEncodeStats -/** - * \brief Get encoding statistics. - * - * This function is used to retrieve the encoding statistics. - * This API is not supported when encode device type is CUDA. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] encodeStats - * Pointer to the ::_NV_ENC_STAT structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncGetEncodeStats (void* encoder, NV_ENC_STAT* encodeStats); - - -// NvEncGetSequenceParams -/** - * \brief Get encoded sequence and picture header. - * - * This function can be used to retrieve the sequence and picture header out of - * band. The client must call this function only after the encoder has been - * initialized using ::NvEncInitializeEncoder() function. The client must - * allocate the memory where the NvEncodeAPI interface can copy the bitstream - * header and pass the pointer to the memory in NV_ENC_SEQUENCE_PARAM_PAYLOAD::spsppsBuffer. - * The size of buffer is passed in the field NV_ENC_SEQUENCE_PARAM_PAYLOAD::inBufferSize. - * The NvEncodeAPI interface will copy the bitstream header payload and returns - * the actual size of the bitstream header in the field - * NV_ENC_SEQUENCE_PARAM_PAYLOAD::outSPSPPSPayloadSize. - * The client must call ::NvEncGetSequenceParams() function from the same thread which is - * being used to call ::NvEncEncodePicture() function. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] sequenceParamPayload - * Pointer to the ::_NV_ENC_SEQUENCE_PARAM_PAYLOAD structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncGetSequenceParams (void* encoder, NV_ENC_SEQUENCE_PARAM_PAYLOAD* sequenceParamPayload); - - -// NvEncRegisterAsyncEvent -/** - * \brief Register event for notification to encoding completion. - * - * This function is used to register the completion event with NvEncodeAPI - * interface. The event is required when the client has configured the encoder to - * work in asynchronous mode. In this mode the client needs to send a completion - * event with every output buffer. The NvEncodeAPI interface will signal the - * completion of the encoding process using this event. Only after the event is - * signalled the client can get the encoded data using ::NvEncLockBitstream() function. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in] eventParams - * Pointer to the ::_NV_ENC_EVENT_PARAMS structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncRegisterAsyncEvent (void* encoder, NV_ENC_EVENT_PARAMS* eventParams); - - -// NvEncUnregisterAsyncEvent -/** - * \brief Unregister completion event. - * - * This function is used to unregister completion event which has been previously - * registered using ::NvEncRegisterAsyncEvent() function. The client must unregister - * all events before destroying the encoder using ::NvEncDestroyEncoder() function. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in] eventParams - * Pointer to the ::_NV_ENC_EVENT_PARAMS structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncUnregisterAsyncEvent (void* encoder, NV_ENC_EVENT_PARAMS* eventParams); - - -// NvEncMapInputResource -/** - * \brief Map an externally created input resource pointer for encoding. - * - * Maps an externally allocated input resource [using and returns a NV_ENC_INPUT_PTR - * which can be used for encoding in the ::NvEncEncodePicture() function. The - * mapped resource is returned in the field NV_ENC_MAP_INPUT_RESOURCE::outputResourcePtr. - * The NvEncodeAPI interface also returns the buffer format of the mapped resource - * in the field NV_ENC_MAP_INPUT_RESOURCE::outbufferFmt. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in,out] mapInputResParams - * Pointer to the ::_NV_ENC_MAP_INPUT_RESOURCE structure. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_RESOURCE_NOT_REGISTERED \n - * ::NV_ENC_ERR_MAP_FAILED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncMapInputResource (void* encoder, NV_ENC_MAP_INPUT_RESOURCE* mapInputResParams); - - -// NvEncUnmapInputResource -/** - * \brief UnMaps a NV_ENC_INPUT_PTR which was mapped for encoding - * - * - * UnMaps an input buffer which was previously mapped using ::NvEncMapInputResource() - * API. The mapping created using ::NvEncMapInputResource() should be invalidated - * using this API before the external resource is destroyed by the client. - * - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in] mappedInputBuffer - * Pointer to the NV_ENC_INPUT_PTR - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_RESOURCE_NOT_REGISTERED \n - * ::NV_ENC_ERR_RESOURCE_NOT_MAPPED \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncUnmapInputResource (void* encoder, NV_ENC_INPUT_PTR mappedInputBuffer); - -// NvEncDestroyEncoder -/** - * \brief Destroy Encoding Session - * - * Destroys the encoder session previously created using ::NvEncOpenEncodeSession() - * function. The client must flush the encoder before freeing any resources. In order - * to flush the encoder the client must pass a NULL encode picture packet and either - * wait for the ::NvEncEncodePicture() function to return in synchronous mode or wait - * for the flush event to be signaled by the encoder in asynchronous mode. - * The client must free all the input and output resources created using the - * NvEncodeAPI interface before destroying the encoder. If the client is operating - * in asynchronous mode, it must also unregister the completion events previously - * registered. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncDestroyEncoder (void* encoder); - -// NvEncInvalidateRefFrames -/** - * \brief Invalidate reference frames - * - * Invalidates reference frame based on the time stamp provided by the client. - * The encoder marks any reference frames or any frames which havev been reconstructed - * using the corrupt frame as invalid for motion estimation and uses older reference - * frames for motion estimation. The encoded forces the current frame to be encoded - * as an intra frame if no reference frames are left after invalidation process. - * This is usefull for low latency application for error resiliency. The client - * is recommended to set NV_ENC_CONFIG_H264::maxNumRefFrames to a large value so - * that encoder can keep a backup of older reference frames in the DPB and can use them - * for motion estimation when the newer reference frames have been invalidated. - * This API can be called multiple times. - * - * \param [in] encoder - * Pointer to the NvEncodeAPI interface. - * \param [in] invalidRefFrameTimeStamp - * Timestamp of the invalid reference frames which needs to be invalidated. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncInvalidateRefFrames(void* encoder, uint64_t invalidRefFrameTimeStamp); - -// NvEncOpenEncodeSessionEx -/** - * \brief Opens an encoding session. - * - * Opens an encoding session and returns a pointer to the encoder interface in - * the \p **encoder parameter. The client should start encoding process by calling - * this API first. - * The client must pass a pointer to IDirect3DDevice9 interface \p *device parameter. - * If the Encoder session fails, the client must call ::NvEncDestroyEncoder API - * before exiting. - * - * \param [in] openSessionExParams - * Pointer to a ::NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS structure. - * \param [out] encoder - * Encode Session pointer to the NvEncodeAPI interface. - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_NO_ENCODE_DEVICE \n - * ::NV_ENC_ERR_UNSUPPORTED_DEVICE \n - * ::NV_ENC_ERR_INVALID_DEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncOpenEncodeSessionEx (NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS *openSessionExParams, void** encoder); - -// NvEncRegisterResource -/** - * \brief Registers a resource with the Nvidia Video Encoder Interface. - * - * Registers a resource with the Nvidia Video Encoder Interface for book keeping. - * The client is expected to pass the registered resource handle as well, while calling ::NvEncMapInputResource API. - * This API is not implemented for the DirectX Interface. - * DirectX based clients need not change their implementation. - * - * \param [in] encoder - * Pointer to the NVEncodeAPI interface. - * - * \param [in] registerResParams - * Pointer to a ::_NV_ENC_REGISTER_RESOURCE structure - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_RESOURCE_REGISTER_FAILED \n - * ::NV_ENC_ERR_GENERIC \n - * ::NV_ENC_ERR_UNIMPLEMENTED \n - * - */ -NVENCSTATUS NVENCAPI NvEncRegisterResource (void* encoder, NV_ENC_REGISTER_RESOURCE* registerResParams); - -// NvEncUnregisterResource -/** - * \brief Unregisters a resource previously registered with the Nvidia Video Encoder Interface. - * - * Unregisters a resource previously registered with the Nvidia Video Encoder Interface. - * The client is expected to unregister any resource that it has registered with the - * Nvidia Video Encoder Interface before destroying the resource. - * This API is not implemented for the DirectX Interface. - * DirectX based clients need not change their implementation. - * - * \param [in] encoder - * Pointer to the NVEncodeAPI interface. - * - * \param [in] registeredResource - * The registered resource pointer that was returned in ::NvEncRegisterResource. - * - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_INVALID_ENCODERDEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_OUT_OF_MEMORY \n - * ::NV_ENC_ERR_INVALID_VERSION \n - * ::NV_ENC_ERR_INVALID_PARAM \n - * ::NV_ENC_ERR_ENCODER_NOT_INITIALIZED \n - * ::NV_ENC_ERR_RESOURCE_NOT_REGISTERED \n - * ::NV_ENC_ERR_GENERIC \n - * ::NV_ENC_ERR_UNIMPLEMENTED \n - * - */ -NVENCSTATUS NVENCAPI NvEncUnregisterResource (void* encoder, NV_ENC_REGISTERED_PTR registeredResource); - -// NvEncReconfigureEncoder -/** - * \brief Reconfigure an existing encoding session. - * - * Reconfigure an existing encoding session. - * The client should call this API to change/reconfigure the parameter passed during - * NvEncInitializeEncoder API call. - * Currently Reconfiguration of following are not supported. - * Change in GOP structure. - * Change in sync-Async mode. - * Change in MaxWidth & MaxHeight. - * Change in PTDmode. - * - * Resolution change is possible only if maxEncodeWidth & maxEncodeHeight of NV_ENC_INITIALIZE_PARAMS - * is set while creating encoder session. - * - * \param [in] encoder - * Pointer to the NVEncodeAPI interface. - * - * \param [in] reInitEncodeParams - * Pointer to a ::NV_ENC_RECONFIGURE_PARAMS structure. - * \return - * ::NV_ENC_SUCCESS \n - * ::NV_ENC_ERR_INVALID_PTR \n - * ::NV_ENC_ERR_NO_ENCODE_DEVICE \n - * ::NV_ENC_ERR_UNSUPPORTED_DEVICE \n - * ::NV_ENC_ERR_INVALID_DEVICE \n - * ::NV_ENC_ERR_DEVICE_NOT_EXIST \n - * ::NV_ENC_ERR_UNSUPPORTED_PARAM \n - * ::NV_ENC_ERR_GENERIC \n - * - */ -NVENCSTATUS NVENCAPI NvEncReconfigureEncoder (void *encoder, NV_ENC_RECONFIGURE_PARAMS* reInitEncodeParams); - - -/// \cond API PFN -/* - * Defines API function pointers - */ -typedef NVENCSTATUS (NVENCAPI* PNVENCOPENENCODESESSION) (void* device, uint32_t deviceType, void** encoder); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEGUIDCOUNT) (void* encoder, uint32_t* encodeGUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEGUIDS) (void* encoder, GUID* GUIDs, uint32_t guidArraySize, uint32_t* GUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEPROFILEGUIDCOUNT) (void* encoder, GUID encodeGUID, uint32_t* encodeProfileGUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEPROFILEGUIDS) (void* encoder, GUID encodeGUID, GUID* profileGUIDs, uint32_t guidArraySize, uint32_t* GUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETINPUTFORMATCOUNT) (void* encoder, GUID encodeGUID, uint32_t* inputFmtCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETINPUTFORMATS) (void* encoder, GUID encodeGUID, NV_ENC_BUFFER_FORMAT* inputFmts, uint32_t inputFmtArraySize, uint32_t* inputFmtCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODECAPS) (void* encoder, GUID encodeGUID, NV_ENC_CAPS_PARAM* capsParam, int* capsVal); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEPRESETCOUNT) (void* encoder, GUID encodeGUID, uint32_t* encodePresetGUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEPRESETGUIDS) (void* encoder, GUID encodeGUID, GUID* presetGUIDs, uint32_t guidArraySize, uint32_t* encodePresetGUIDCount); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODEPRESETCONFIG) (void* encoder, GUID encodeGUID, GUID presetGUID, NV_ENC_PRESET_CONFIG* presetConfig); -typedef NVENCSTATUS (NVENCAPI* PNVENCINITIALIZEENCODER) (void* encoder, NV_ENC_INITIALIZE_PARAMS* createEncodeParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCCREATEINPUTBUFFER) (void* encoder, NV_ENC_CREATE_INPUT_BUFFER* createInputBufferParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCDESTROYINPUTBUFFER) (void* encoder, NV_ENC_INPUT_PTR inputBuffer); -typedef NVENCSTATUS (NVENCAPI* PNVENCCREATEBITSTREAMBUFFER) (void* encoder, NV_ENC_CREATE_BITSTREAM_BUFFER* createBitstreamBufferParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCDESTROYBITSTREAMBUFFER) (void* encoder, NV_ENC_OUTPUT_PTR bitstreamBuffer); -typedef NVENCSTATUS (NVENCAPI* PNVENCENCODEPICTURE) (void* encoder, NV_ENC_PIC_PARAMS* encodePicParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCLOCKBITSTREAM) (void* encoder, NV_ENC_LOCK_BITSTREAM* lockBitstreamBufferParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCUNLOCKBITSTREAM) (void* encoder, NV_ENC_OUTPUT_PTR bitstreamBuffer); -typedef NVENCSTATUS (NVENCAPI* PNVENCLOCKINPUTBUFFER) (void* encoder, NV_ENC_LOCK_INPUT_BUFFER* lockInputBufferParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCUNLOCKINPUTBUFFER) (void* encoder, NV_ENC_INPUT_PTR inputBuffer); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETENCODESTATS) (void* encoder, NV_ENC_STAT* encodeStats); -typedef NVENCSTATUS (NVENCAPI* PNVENCGETSEQUENCEPARAMS) (void* encoder, NV_ENC_SEQUENCE_PARAM_PAYLOAD* sequenceParamPayload); -typedef NVENCSTATUS (NVENCAPI* PNVENCREGISTERASYNCEVENT) (void* encoder, NV_ENC_EVENT_PARAMS* eventParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCUNREGISTERASYNCEVENT) (void* encoder, NV_ENC_EVENT_PARAMS* eventParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCMAPINPUTRESOURCE) (void* encoder, NV_ENC_MAP_INPUT_RESOURCE* mapInputResParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCUNMAPINPUTRESOURCE) (void* encoder, NV_ENC_INPUT_PTR mappedInputBuffer); -typedef NVENCSTATUS (NVENCAPI* PNVENCDESTROYENCODER) (void* encoder); -typedef NVENCSTATUS (NVENCAPI* PNVENCINVALIDATEREFFRAMES) (void* encoder, uint64_t invalidRefFrameTimeStamp); -typedef NVENCSTATUS (NVENCAPI* PNVENCOPENENCODESESSIONEX) (NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS *openSessionExParams, void** encoder); -typedef NVENCSTATUS (NVENCAPI* PNVENCREGISTERRESOURCE) (void* encoder, NV_ENC_REGISTER_RESOURCE* registerResParams); -typedef NVENCSTATUS (NVENCAPI* PNVENCUNREGISTERRESOURCE) (void* encoder, NV_ENC_REGISTERED_PTR registeredRes); -typedef NVENCSTATUS (NVENCAPI* PNVENCRECONFIGUREENCODER) (void* encoder, NV_ENC_RECONFIGURE_PARAMS* reInitEncodeParams); - -/// \endcond - - -/** @} */ /* END ENCODE_FUNC */ - -/** - * \ingroup ENCODER_STRUCTURE - * NV_ENCODE_API_FUNCTION_LIST - */ -typedef struct _NV_ENCODE_API_FUNCTION_LIST -{ - uint32_t version; /**< [in]: Client should pass NV_ENCODE_API_FUNCTION_LIST_VER. */ - uint32_t reserved; /**< [in]: Reserved and should be set to 0. */ - PNVENCOPENENCODESESSION nvEncOpenEncodeSession; /**< [out]: Client should access ::NvEncOpenEncodeSession() API through this pointer. */ - PNVENCGETENCODEGUIDCOUNT nvEncGetEncodeGUIDCount; /**< [out]: Client should access ::NvEncGetEncodeGUIDCount() API through this pointer. */ - PNVENCGETENCODEPRESETCOUNT nvEncGetEncodeProfileGUIDCount; /**< [out]: Client should access ::NvEncGetEncodeProfileGUIDCount() API through this pointer.*/ - PNVENCGETENCODEPRESETGUIDS nvEncGetEncodeProfileGUIDs; /**< [out]: Client should access ::NvEncGetEncodeProfileGUIDs() API through this pointer. */ - PNVENCGETENCODEGUIDS nvEncGetEncodeGUIDs; /**< [out]: Client should access ::NvEncGetEncodeGUIDs() API through this pointer. */ - PNVENCGETINPUTFORMATCOUNT nvEncGetInputFormatCount; /**< [out]: Client should access ::NvEncGetInputFormatCount() API through this pointer. */ - PNVENCGETINPUTFORMATS nvEncGetInputFormats; /**< [out]: Client should access ::NvEncGetInputFormats() API through this pointer. */ - PNVENCGETENCODECAPS nvEncGetEncodeCaps; /**< [out]: Client should access ::NvEncGetEncodeCaps() API through this pointer. */ - PNVENCGETENCODEPRESETCOUNT nvEncGetEncodePresetCount; /**< [out]: Client should access ::NvEncGetEncodePresetCount() API through this pointer. */ - PNVENCGETENCODEPRESETGUIDS nvEncGetEncodePresetGUIDs; /**< [out]: Client should access ::NvEncGetEncodePresetGUIDs() API through this pointer. */ - PNVENCGETENCODEPRESETCONFIG nvEncGetEncodePresetConfig; /**< [out]: Client should access ::NvEncGetEncodePresetConfig() API through this pointer. */ - PNVENCINITIALIZEENCODER nvEncInitializeEncoder; /**< [out]: Client should access ::NvEncInitializeEncoder() API through this pointer. */ - PNVENCCREATEINPUTBUFFER nvEncCreateInputBuffer; /**< [out]: Client should access ::NvEncCreateInputBuffer() API through this pointer. */ - PNVENCDESTROYINPUTBUFFER nvEncDestroyInputBuffer; /**< [out]: Client should access ::NvEncDestroyInputBuffer() API through this pointer. */ - PNVENCCREATEBITSTREAMBUFFER nvEncCreateBitstreamBuffer; /**< [out]: Client should access ::NvEncCreateBitstreamBuffer() API through this pointer. */ - PNVENCDESTROYBITSTREAMBUFFER nvEncDestroyBitstreamBuffer; /**< [out]: Client should access ::NvEncDestroyBitstreamBuffer() API through this pointer. */ - PNVENCENCODEPICTURE nvEncEncodePicture; /**< [out]: Client should access ::NvEncEncodePicture() API through this pointer. */ - PNVENCLOCKBITSTREAM nvEncLockBitstream; /**< [out]: Client should access ::NvEncLockBitstream() API through this pointer. */ - PNVENCUNLOCKBITSTREAM nvEncUnlockBitstream; /**< [out]: Client should access ::NvEncUnlockBitstream() API through this pointer. */ - PNVENCLOCKINPUTBUFFER nvEncLockInputBuffer; /**< [out]: Client should access ::NvEncLockInputBuffer() API through this pointer. */ - PNVENCUNLOCKINPUTBUFFER nvEncUnlockInputBuffer; /**< [out]: Client should access ::NvEncUnlockInputBuffer() API through this pointer. */ - PNVENCGETENCODESTATS nvEncGetEncodeStats; /**< [out]: Client should access ::NvEncGetEncodeStats() API through this pointer. */ - PNVENCGETSEQUENCEPARAMS nvEncGetSequenceParams; /**< [out]: Client should access ::NvEncGetSequenceParams() API through this pointer. */ - PNVENCREGISTERASYNCEVENT nvEncRegisterAsyncEvent; /**< [out]: Client should access ::NvEncRegisterAsyncEvent() API through this pointer. */ - PNVENCUNREGISTERASYNCEVENT nvEncUnregisterAsyncEvent; /**< [out]: Client should access ::NvEncUnregisterAsyncEvent() API through this pointer. */ - PNVENCMAPINPUTRESOURCE nvEncMapInputResource; /**< [out]: Client should access ::NvEncMapInputResource() API through this pointer. */ - PNVENCUNMAPINPUTRESOURCE nvEncUnmapInputResource; /**< [out]: Client should access ::NvEncUnmapInputResource() API through this pointer. */ - PNVENCDESTROYENCODER nvEncDestroyEncoder; /**< [out]: Client should access ::NvEncDestroyEncoder() API through this pointer. */ - PNVENCINVALIDATEREFFRAMES nvEncInvalidateRefFrames; /**< [out]: Client should access ::NvEncInvalidateRefFrames() API through this pointer. */ - PNVENCOPENENCODESESSIONEX nvEncOpenEncodeSessionEx; /**< [out]: Client should access ::NvEncOpenEncodeSession() API through this pointer. */ - PNVENCREGISTERRESOURCE nvEncRegisterResource; /**< [out]: Client should access ::NvEncRegisterResource() API through this pointer. */ - PNVENCUNREGISTERRESOURCE nvEncUnregisterResource; /**< [out]: Client should access ::NvEncUnregisterResource() API through this pointer. */ - PNVENCRECONFIGUREENCODER nvEncReconfigureEncoder; /**< [out]: Client should access ::NvEncReconfigureEncoder() API through this pointer. */ - void* reserved2[285]; /**< [in]: Reserved and must be set to NULL */ -} NV_ENCODE_API_FUNCTION_LIST; - -/** Macro for constructing the version field of ::_NV_ENCODEAPI_FUNCTION_LIST. */ -#define NV_ENCODE_API_FUNCTION_LIST_VER NVENCAPI_STRUCT_VERSION(NV_ENCODE_API_FUNCTION_LIST, 2) - -// NvEncodeAPICreateInstance -/** - * \ingroup ENCODE_FUNC - * Entry Point to the NvEncodeAPI interface. - * - * Creates an instance of the NvEncodeAPI interface, and populates the - * pFunctionList with function pointers to the API routines implemented by the - * NvEncodeAPI interface. - * - * \param [out] functionList - * - * \return - * ::NV_ENC_SUCCESS - * ::NV_ENC_ERR_INVALID_PTR - */ -NVENCSTATUS NVENCAPI NvEncodeAPICreateInstance(NV_ENCODE_API_FUNCTION_LIST *functionList); - -#ifdef __cplusplus -} -#endif - - -#endif - diff --git a/rdp-acceleraed/Server/NvEncoder/nvFileIO.h b/rdp-acceleraed/Server/NvEncoder/nvFileIO.h deleted file mode 100644 index fc6e059c72..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/nvFileIO.h +++ /dev/null @@ -1,177 +0,0 @@ -/// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#ifndef NVFILE_IO_H -#define NVFILE_IO_H - -#if defined __linux__ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef void * HANDLE; -typedef void *HINSTANCE; -typedef unsigned long DWORD, *LPDWORD; -typedef DWORD FILE_SIZE; - -#define FALSE 0 -#define TRUE 1 -#define INFINITE UINT_MAX - -#define FILE_BEGIN SEEK_SET -#define INVALID_SET_FILE_POINTER (-1) -#define INVALID_HANDLE_VALUE ((void *)(-1)) - -#else -#include -#include -#endif - -#include "nvCPUOPSys.h" - -typedef unsigned long long U64; -typedef unsigned int U32; - -inline U32 nvSetFilePointer(HANDLE hInputFile, U32 fileOffset, U32 *moveFilePointer, U32 flag) -{ -#if defined (NV_WINDOWS) - return SetFilePointer(hInputFile, fileOffset, NULL, flag); -#elif defined __linux || defined __APPLE_ || defined __MACOSX - return fseek((FILE *)hInputFile, fileOffset, flag); -#endif -} - -inline U32 nvSetFilePointer64(HANDLE hInputFile, U64 fileOffset, U64 *moveFilePointer, U32 flag) -{ -#if defined (NV_WINDOWS) - return SetFilePointer(hInputFile, ((U32 *)&fileOffset)[0], (PLONG)&((U32 *)&fileOffset)[1], flag); -#elif defined __linux || defined __APPLE__ || defined __MACOSX - return fseek((FILE *)hInputFile, (long int)fileOffset, flag); -#endif -} - -inline bool nvReadFile(HANDLE hInputFile, void *buf, U32 bytes_to_read, U32 *bytes_read, void *operlapped) -{ -#if defined (NV_WINDOWS) - ReadFile(hInputFile, buf, bytes_to_read, (LPDWORD)bytes_read, NULL); - return true; -#elif defined __linux || defined __APPLE__ || defined __MACOSX - U32 num_bytes_read; - num_bytes_read = fread(buf, bytes_to_read, 1, (FILE *)hInputFile); - - if (bytes_read) - { - *bytes_read = num_bytes_read; - } - return true; -#endif -} - -inline void nvGetFileSize(HANDLE hInputFile, DWORD *pFilesize) -{ -#if defined (NV_WINDOWS) - LARGE_INTEGER file_size; - - if (hInputFile != INVALID_HANDLE_VALUE) - { - file_size.LowPart = GetFileSize(hInputFile, (LPDWORD)&file_size.HighPart); - printf("[ Input Filesize] : %lld bytes\n", ((LONGLONG) file_size.HighPart << 32) + (LONGLONG)file_size.LowPart); - - if (pFilesize != NULL) *pFilesize = file_size.LowPart; - } - -#elif defined __linux || defined __APPLE__ || defined __MACOSX - FILE_SIZE file_size; - - if (hInputFile != NULL) - { - nvSetFilePointer64(hInputFile, 0, NULL, SEEK_END); - file_size = ftell((FILE *)hInputFile); - nvSetFilePointer64(hInputFile, 0, NULL, SEEK_SET); - printf("Input Filesize: %ld bytes\n", file_size); - - if (pFilesize != NULL) *pFilesize = file_size; - } - -#endif -} - -inline HANDLE nvOpenFile(const char *input_file) -{ - HANDLE hInput = NULL; - -#if defined (NV_WINDOWS) - hInput = CreateFileA(input_file, GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_EXISTING , FILE_ATTRIBUTE_NORMAL, NULL); - - if (hInput == INVALID_HANDLE_VALUE) - { - fprintf(stderr, "nvOpenFile Failed to open \"%s\"\n", input_file); - exit(EXIT_FAILURE); - } - -#elif defined __linux || defined __APPLE_ || defined __MACOSX - hInput = fopen(input_file, "rb"); - - if (hInput == NULL) - { - fprintf(stderr, "nvOpenFile Failed to open \"%s\"\n", input_file); - exit(EXIT_FAILURE); - } - -#endif - return hInput; -} - -inline HANDLE nvOpenFileWrite(const char *output_file) -{ - HANDLE hOutput = NULL; - -#if defined (NV_WINDOWS) - hOutput = CreateFileA(output_file, GENERIC_WRITE, FILE_SHARE_WRITE, NULL, OPEN_EXISTING , FILE_ATTRIBUTE_NORMAL, NULL); - - if (hOutput == INVALID_HANDLE_VALUE) - { - fprintf(stderr, "nvOpenFileWrite Failed to open \"%s\"\n", output_file); - exit(EXIT_FAILURE); - } - -#elif defined __linux || defined __APPLE_ || defined __MACOSX - hOutput = fopen(output_file, "wb+"); - - if (hOutput == NULL) - { - fprintf(stderr, "nvOpenFileWrite Failed to open \"%s\"\n", output_file); - exit(EXIT_FAILURE); - } - -#endif - return hOutput; -} - -inline void nvCloseFile(HANDLE hFileHandle) -{ - if (hFileHandle) - { -#if defined (NV_WINDOWS) - CloseHandle(hFileHandle); -#else - fclose((FILE *)hFileHandle); -#endif - } -} - -#endif diff --git a/rdp-acceleraed/Server/NvEncoder/nvUtils.h b/rdp-acceleraed/Server/NvEncoder/nvUtils.h deleted file mode 100644 index 1520444600..0000000000 --- a/rdp-acceleraed/Server/NvEncoder/nvUtils.h +++ /dev/null @@ -1,127 +0,0 @@ -// -// Copyright 1993-2014 NVIDIA Corporation. All rights reserved. -// -// Please refer to the NVIDIA end user license agreement (EULA) associated -// with this source code for terms and conditions that govern your use of -// this software. Any use, reproduction, disclosure, or distribution of -// this software and related documentation outside the terms of the EULA -// is strictly prohibited. -// -//////////////////////////////////////////////////////////////////////////// - -#ifndef NVUTILS_H -#define NVUTILS_H - -#include "nvCPUOPSys.h" -#include "nvFileIO.h" - -#if defined (NV_WINDOWS) -#include -#elif defined NV_UNIX -#include -#include - -#define FALSE 0 -#define TRUE 1 -#define INFINITE UINT_MAX -#define stricmp strcasecmp -#define FILE_BEGIN SEEK_SET -#define INVALID_SET_FILE_POINTER (-1) -#define INVALID_HANDLE_VALUE ((void *)(-1)) -#define max(a, b) ((a) > (b) ? (a) : (b)) -#define min(a, b) ((a) < (b) ? (a) : (b)) - -typedef void* HANDLE; -typedef void* HINSTANCE; -typedef unsigned long DWORD, *LPWORD; -typedef DWORD FILE_SIZE; -#endif - -inline bool NvSleep(unsigned int mSec) -{ -#if defined (NV_WINDOWS) - Sleep(mSec); -#elif defined NV_UNIX - usleep(mSec * 1000); -#else -#error NvSleep function unknown for this platform. -#endif - return true; -} - -inline bool NvQueryPerformanceFrequency(unsigned long long *freq) -{ - *freq = 0; -#if defined (NV_WINDOWS) - LARGE_INTEGER lfreq; - if (!QueryPerformanceFrequency(&lfreq)) { - return false; - } - *freq = lfreq.QuadPart; -#elif defined NV_UNIX - // We use system's gettimeofday() to return timer ticks in uSec - *freq = 1000000000; -#else -#error NvQueryPerformanceFrequency function not defined for this platform. -#endif - - return true; -} - -#define SEC_TO_NANO_ULL(sec) ((unsigned long long)sec * 1000000000) -#define MICRO_TO_NANO_ULL(sec) ((unsigned long long)sec * 1000) - -inline bool NvQueryPerformanceCounter(unsigned long long *counter) -{ - *counter = 0; -#if defined (NV_WINDOWS) - LARGE_INTEGER lcounter; - if (!QueryPerformanceCounter(&lcounter)) { - return false; - } - *counter = lcounter.QuadPart; -#elif defined NV_UNIX - struct timeval tv; - int ret; - - ret = gettimeofday(&tv, NULL); - if (ret != 0) { - return false; - } - - *counter = SEC_TO_NANO_ULL(tv.tv_sec) + MICRO_TO_NANO_ULL(tv.tv_usec); -#else -#error NvQueryPerformanceCounter function not defined for this platform. -#endif - return true; -} - -#if defined NV_UNIX -__inline bool operator==(const GUID &guid1, const GUID &guid2) -{ - if (guid1.Data1 == guid2.Data1 && - guid1.Data2 == guid2.Data2 && - guid1.Data3 == guid2.Data3 && - guid1.Data4[0] == guid2.Data4[0] && - guid1.Data4[1] == guid2.Data4[1] && - guid1.Data4[2] == guid2.Data4[2] && - guid1.Data4[3] == guid2.Data4[3] && - guid1.Data4[4] == guid2.Data4[4] && - guid1.Data4[5] == guid2.Data4[5] && - guid1.Data4[6] == guid2.Data4[6] && - guid1.Data4[7] == guid2.Data4[7]) - { - return true; - } - - return false; -} -__inline bool operator!=(const GUID &guid1, const GUID &guid2) -{ - return !(guid1 == guid2); -} -#endif -#endif - -#define PRINTERR(message, ...) \ - fprintf(stderr, "%s line %d: " message, __FILE__, __LINE__, ##__VA_ARGS__) diff --git a/rdp-acceleraed/Server/WDDMCapture.h b/rdp-acceleraed/Server/WDDMCapture.h deleted file mode 100644 index 06eb65742e..0000000000 --- a/rdp-acceleraed/Server/WDDMCapture.h +++ /dev/null @@ -1,40 +0,0 @@ -#pragma once - -#include "wddm.h" - -#include "Capture.h" - -class WDDMCapture : public Capture { -public: - void init(UINT monitorID, RECT screen) - { - this->screen = screen; - - wddm.wf_dxgi_init(monitorID, screen); - - } - int getNextFrame(RGBQUAD** pPixels) - { - int rc; - rc = wddm.wf_dxgi_nextFrame(3000); - if (rc != 0) { - return rc; - } - - int pitch; - rc = wddm.wf_dxgi_getPixelData((byte**)pPixels, &pitch, &screen); - if (rc != 0) { - return rc; - } - - return 0; - } - void doneNextFrame() - { - int rc = wddm.wf_dxgi_releasePixelData(); - } - -private: - RECT screen; - WDDM wddm; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/bounded_buffer.h b/rdp-acceleraed/Server/bounded_buffer.h deleted file mode 100644 index c92e8f2c9e..0000000000 --- a/rdp-acceleraed/Server/bounded_buffer.h +++ /dev/null @@ -1,53 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include // for auto_cpu_timer - -template -class bounded_buffer -{ -public: - - typedef boost::circular_buffer container_type; - typedef typename container_type::size_type size_type; - typedef typename container_type::value_type value_type; - typedef typename boost::call_traits::param_type param_type; - - explicit bounded_buffer(size_type capacity) : m_unread(0), m_container(capacity) {} - - void push_front(typename boost::call_traits::param_type item) - { // `param_type` represents the "best" way to pass a parameter of type `value_type` to a method. - - boost::mutex::scoped_lock lock(m_mutex); - m_not_full.wait(lock, boost::bind(&bounded_buffer::is_not_full, this)); - m_container.push_front(item); - ++m_unread; - lock.unlock(); - m_not_empty.notify_one(); - } - - void pop_back(value_type* pItem) { - boost::mutex::scoped_lock lock(m_mutex); - m_not_empty.wait(lock, boost::bind(&bounded_buffer::is_not_empty, this)); - *pItem = m_container[--m_unread]; - lock.unlock(); - m_not_full.notify_one(); - } - -private: - bounded_buffer(const bounded_buffer&); // Disabled copy constructor. - bounded_buffer& operator = (const bounded_buffer&); // Disabled assign operator. - - bool is_not_empty() const { return m_unread > 0; } - bool is_not_full() const { return m_unread < m_container.capacity(); } - - size_type m_unread; - container_type m_container; - boost::mutex m_mutex; - boost::condition m_not_empty; - boost::condition m_not_full; -}; // \ No newline at end of file diff --git a/rdp-acceleraed/Server/color_conversion.cu b/rdp-acceleraed/Server/color_conversion.cu deleted file mode 100644 index 4df9c39c55..0000000000 --- a/rdp-acceleraed/Server/color_conversion.cu +++ /dev/null @@ -1,100 +0,0 @@ -#include "cuda.h" -#include "cuda_runtime.h" -#include "device_launch_parameters.h" - -#include "color_conversion.h" - -#include "stdio.h" - -__host__ __device__ __forceinline__ int divUp(int total, int grain) -{ - return (total + grain - 1) / grain; -} - -__global__ void RGB_to_jp(uchar4 *input, unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr, int width, int height) -{ - const int x = blockIdx.x * blockDim.x + threadIdx.x; - const int y = blockIdx.y * blockDim.y + threadIdx.y; - - if (x >= width || y>=height) return; - - uchar4 px = input[y * width + x]; - int Y = ( ( 66 * px.x + 129 * px.y + 25 * px.z + 128) >> 8) + 16; - int U = ( ( -38 * px.x - 74 * px.y + 112 * px.z + 128) >> 8) + 128; - int V = ( ( 112 * px.x - 94 * px.y - 18 * px.z + 128) >> 8) + 128; - - yuv_luma[y * width + x] = Y; - - int pos = (y >> 1) * (width >> 1) + (x >> 1); - yuv_cr[pos] = U; - yuv_cb[pos] = V; -} - -bool RGB_to_YV12(int width, int height, void *pPixels, void* yuv_luma, void* yuv_cb, void* yuv_cr) -{ - cudaError_t cudaStatus; - - const dim3 block(32, 8); - const dim3 grid(divUp(width, block.x), divUp(height, block.y)); - - unsigned char *yuv_luma_device; - cudaMalloc(&yuv_luma_device, width *height * sizeof(unsigned char)); - - unsigned char *yuv_cb_device; - cudaMalloc(&yuv_cb_device, width *height * sizeof(unsigned char) / 4); - - unsigned char *yuv_cr_device; - cudaMalloc(&yuv_cr_device, width *height * sizeof(unsigned char) / 4); - - - // Copy input vectors from host memory to GPU buffers. - uchar4 *dev_pPixels; - cudaStatus = cudaMalloc((void**)&dev_pPixels, width *height * sizeof(uchar4)); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaMalloc failed!"); - return false; - } - - cudaStatus = cudaMemcpy(dev_pPixels, pPixels, width *height * sizeof(uchar4), cudaMemcpyHostToDevice); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaMemcpy 1 failed!"); - return false; - } - - RGB_to_jp<<< grid, block >>>(dev_pPixels, yuv_luma_device, yuv_cb_device, yuv_cr_device, width, height); - - cudaStatus = cudaGetLastError(); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "RGB_to_jp failed!"); - return false; - } - - cudaStatus = cudaDeviceSynchronize(); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaDeviceSynchronize failed!"); - return false; - } - - cudaStatus = cudaMemcpy(yuv_luma, yuv_luma_device, width *height * sizeof(unsigned char), cudaMemcpyDeviceToHost); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaMemcpy 2 failed!"); - return false; - } - cudaStatus = cudaMemcpy(yuv_cb, yuv_cb_device, width *height * sizeof(unsigned char) / 4, cudaMemcpyDeviceToHost); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaMemcpy 2 failed!"); - return false; - } - cudaStatus = cudaMemcpy(yuv_cr, yuv_cr_device, width *height * sizeof(unsigned char) / 4, cudaMemcpyDeviceToHost); - if (cudaStatus != cudaSuccess) { - fprintf(stderr, "cudaMemcpy 2 failed!"); - return false; - } - - cudaFree(yuv_luma_device); - cudaFree(yuv_cb_device); - cudaFree(yuv_cr_device); - cudaFree(dev_pPixels); - - return true; -} \ No newline at end of file diff --git a/rdp-acceleraed/Server/color_conversion.h b/rdp-acceleraed/Server/color_conversion.h deleted file mode 100644 index b6d6ff1ee1..0000000000 --- a/rdp-acceleraed/Server/color_conversion.h +++ /dev/null @@ -1 +0,0 @@ -bool RGB_to_YV12(int width, int height, void *pPixels, void* yuv_luma, void* yuv_cb, void* yuv_cr); \ No newline at end of file diff --git a/rdp-acceleraed/Server/config.h.in b/rdp-acceleraed/Server/config.h.in deleted file mode 100644 index 17c9f9579d..0000000000 --- a/rdp-acceleraed/Server/config.h.in +++ /dev/null @@ -1,4 +0,0 @@ -#cmakedefine HAS_CUDA -#cmakedefine HAS_WDDM -#cmakedefine HAS_NVENC -#cmakedefine HAS_FFMPEG \ No newline at end of file diff --git a/rdp-acceleraed/Server/fps.h b/rdp-acceleraed/Server/fps.h deleted file mode 100644 index 471b3a6320..0000000000 --- a/rdp-acceleraed/Server/fps.h +++ /dev/null @@ -1,43 +0,0 @@ -#pragma once -#include - -class FPS { -public: - FPS() { - fps = 0; - numFrame = 0; - lastSec = 0; - lastShouldRefresh = 0; - } - void newFrame() { - numFrame++; - double newTime = (double)clock() / CLOCKS_PER_SEC; - - if (newTime >= lastSec + 1) { - fps = numFrame; - numFrame = 0; - lastSec = newTime; - printf("FPS: %d\n", getFps()); - } - } - int getFps() { - return fps; - } - - /* Returns true only 30 times per second */ - bool shouldRefresh() { - double newTime = (double)clock() / CLOCKS_PER_SEC; - if (newTime >= lastShouldRefresh + 1.0/30) { - lastShouldRefresh = newTime; - return true; - } else { - return false; - } - } -private: - int fps; - int numFrame; - double lastSec; - - double lastShouldRefresh; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/monitor.h b/rdp-acceleraed/Server/monitor.h deleted file mode 100644 index f5ee0ff5bc..0000000000 --- a/rdp-acceleraed/Server/monitor.h +++ /dev/null @@ -1,19 +0,0 @@ -#pragma once - -BOOL CALLBACK MonitorEnumProc(HMONITOR hMonitor, HDC hdcMonitor, LPRECT lprcMonitor, LPARAM dwData); - -class Monitor { -public: - Monitor() { - if(!EnumDisplayMonitors(NULL, NULL, MonitorEnumProc, reinterpret_cast(this))) { - throw std::runtime_error ("EnumDisplayMonitors failed"); - } - } - std::vector monitors; -}; -BOOL CALLBACK MonitorEnumProc(HMONITOR hMonitor, HDC hdcMonitor, LPRECT lprcMonitor, LPARAM dwData) -{ - Monitor* mon = (Monitor*)dwData; - mon->monitors.push_back(*lprcMonitor); - return true; -} \ No newline at end of file diff --git a/rdp-acceleraed/Server/params.h b/rdp-acceleraed/Server/params.h deleted file mode 100644 index 81c5469e7e..0000000000 --- a/rdp-acceleraed/Server/params.h +++ /dev/null @@ -1,38 +0,0 @@ -#pragma once - -#include -#include -#include - -using namespace std; - -class Params { -public: - - Params(int argc, const char* argv[]) { - // defaults - monitor = -1; - port = -1; - - map params; - for (int i = 1; i < argc; i++) { - string key = argv[i]; - params[key] = argv[i + 1]; - i++; - } - - typedef map::iterator it_type; - for (it_type iterator = params.begin(); iterator != params.end(); iterator++) { - cout << iterator->first << " : " << iterator->second << endl; - - if (iterator->first.compare("monitor") == 0) { - monitor = atoi(iterator->second.c_str()); - } else if (iterator->first.compare("port") == 0) { - port = atoi(iterator->second.c_str()); - } - } - } - - int monitor; - int port; -}; \ No newline at end of file diff --git a/rdp-acceleraed/Server/server.cpp b/rdp-acceleraed/Server/server.cpp deleted file mode 100644 index bca30de28b..0000000000 --- a/rdp-acceleraed/Server/server.cpp +++ /dev/null @@ -1,278 +0,0 @@ -// -// Copyright (c) 2003-2013 Christopher M. Kohlhoff (chris at kohlhoff dot com) -// -// Distributed under the Boost Software License, Version 1.0. (See accompanying -// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) -// - -#include -#include -#include -#include -#include - -#include "fps.h" -#include "monitor.h" -#include "params.h" -#include "config.h" - -#ifdef HAS_WDDM - #include "WDDMCapture.h" -#else - #include "GDICapture.h" -#endif - -#ifdef HAS_FFMPEG - #include "FFMPEG_encoding.hpp" -#endif - -#ifdef HAS_NVENC - #include "NV_encoding.hpp" -#endif - -using namespace std; -using namespace boost::asio; -using ip::tcp; - -const int max_length = 1024; - -typedef boost::shared_ptr socket_ptr; - -bounded_buffer screenToSendQueue(2); - -void threadScreenCapture(UINT monitorID, RECT screen){ - int height = screen.bottom - screen.top; - int width = screen.right - screen.left; - -#ifdef HAS_WDDM - WDDMCapture capture; -#else - GDICapture capture; -#endif - - capture.init(monitorID, screen); - - RGBQUAD* pPixels; - FPS fps; - while(true){ - int rc = capture.getNextFrame(&pPixels); - if (rc == 0) { - RGBQUAD* pixCopy = new RGBQUAD[width * height]; - memcpy(pixCopy, pPixels, width * height * sizeof(RGBQUAD)); - screenToSendQueue.push_front(pixCopy); - - capture.doneNextFrame(); - fps.newFrame(); - } - } -} - -void sessionVideo(socket_ptr sock, UINT monitorID, RECT screen) -{ - - // get the height and width of the screen - int height = screen.bottom - screen.top; - int width = screen.right - screen.left; - -#ifdef HAS_NVENC - NV_encoding nv_encoding; - nv_encoding.load(width, height, sock, monitorID); -#elif defined(HAS_FFMPEG) - FFMPEG_encoding ffmpeg; - ffmpeg.load(width, height, sock); -#endif - - boost::thread t(boost::bind(threadScreenCapture, monitorID, screen)); - - FPS fps; - RGBQUAD* pPixels; - while(true){ - screenToSendQueue.pop_back(&pPixels); - -#ifdef HAS_NVENC - nv_encoding.write(width, height, pPixels); -#elif defined(HAS_FFMPEG) - ffmpeg.write(width, height, pPixels); -#endif - //fps.newFrame(); - - free(pPixels); - } -#ifdef HAS_NVENC - nv_encoding.close(); -#elif defined(HAS_FFMPEG) - ffmpeg.close(); -#endif -} - -struct SendStruct { - int type; - int x; - int y; - int button; - int keycode; -}; -void sessionKeystroke(socket_ptr sock, RECT screen) -{ - char data[sizeof(SendStruct)]; - boost::system::error_code error; - - SendStruct* s; - INPUT input = {0}; - while(true) { - size_t length = sock->read_some(buffer(data), error); - if (error == error::eof) - return; // Connection closed cleanly by peer. - else if (error) - throw boost::system::system_error(error); // Some other error. - - s = (SendStruct*)data; - - ::ZeroMemory(&input,sizeof(INPUT)); - switch(s->type){ - case 0: // MotionNotify - SetCursorPos(s->x + screen.left, s->y + screen.top); - break; - - case 1: - switch (s->button) { - case 1: // left button - input.mi.dwFlags = MOUSEEVENTF_LEFTDOWN; - break; - case 2: // middle button - input.mi.dwFlags = MOUSEEVENTF_MIDDLEDOWN; - break; - case 3: // third button - input.mi.dwFlags = MOUSEEVENTF_RIGHTDOWN; - break; - case 4: // scroll up - input.mi.dwFlags = MOUSEEVENTF_WHEEL; - input.mi.mouseData = 100; - break; - case 5: // scroll down - input.mi.dwFlags = MOUSEEVENTF_WHEEL; - input.mi.mouseData = -100; - break; - } - input.type = INPUT_MOUSE; - ::SendInput(1,&input,sizeof(INPUT)); - break; - case 2: - switch (s->button) { - case 1: // left button - input.mi.dwFlags = MOUSEEVENTF_LEFTUP; - break; - case 2: // middle button - input.mi.dwFlags = MOUSEEVENTF_MIDDLEUP; - break; - case 3: // third button - input.mi.dwFlags = MOUSEEVENTF_RIGHTUP; - break; - } - if (input.mi.dwFlags) { - input.type = INPUT_MOUSE; - ::SendInput(1,&input,sizeof(INPUT)); - } - break; - - case 3: - input.type = INPUT_KEYBOARD; - input.ki.wScan = s->keycode; - input.ki.wVk=0; - input.ki.dwFlags = KEYEVENTF_UNICODE; - ::SendInput(1,&input,sizeof(INPUT)); - break; - case 4: - input.type = INPUT_KEYBOARD; - input.ki.wScan = s->keycode; - input.ki.wVk=0; - input.ki.dwFlags = KEYEVENTF_UNICODE | KEYEVENTF_KEYUP; - ::SendInput(1,&input,sizeof(INPUT)); - break; - } - } -} -void session(socket_ptr sock, UINT monitorID, RECT screenCoordinates) -{ - try - { - sock->set_option(tcp::no_delay(true)); - char data[max_length]; - - boost::system::error_code error; - size_t length = sock->read_some(buffer(data), error); - if (error == error::eof) - return; // Connection closed cleanly by peer. - else if (error) - throw boost::system::system_error(error); // Some other error. - - if (data[0] == 'a'){ - sessionVideo(sock, monitorID, screenCoordinates); - } else if (data[0] == 'b'){ - sessionKeystroke(sock, screenCoordinates); - } else { - cout << "Received a connection with a wrong identification buffer " << string(data, length) << endl; - } - } - catch (exception& e) - { - cerr << "Exception in thread: " << e.what() << "\n"; - } -} - -void server(io_service& io_service, short port, UINT monitorID, RECT screenCoordinates) -{ - tcp::acceptor a(io_service, tcp::endpoint(tcp::v4(), port)); - for (;;) - { - socket_ptr sock(new tcp::socket(io_service)); - a.accept(*sock); - boost::thread t(boost::bind(session, sock, monitorID, screenCoordinates)); - } -} - -int main(int argc, const char* argv[]) -{ - cout << "Version 0.9" << endl; - Params params(argc, argv); - if (params.port == -1) - { - cerr << "Usage: ./server [options] port <#>" << endl; - cerr << "monitor \n"; - cerr << "Sample: ./server monitor 1 port 8080" << endl; - return 1; - } - - Monitor monitor; - RECT screenCoordinates; - int monitorCount = GetSystemMetrics(SM_CMONITORS); - if (monitorCount > 1 && params.monitor == -1) { - cerr << "There are more than one monitor available, select which monitor to use with\n./server -monitor " << endl; - return 1; - } else { - if (params.monitor < 0 || params.monitor >= monitor.monitors.size()) { - cerr << "The chosen monitor " << params.monitor << " is invalid, select from the following:\n"; - for (int i=0;i -#include - -//#define CINTERFACE - -#include -#include -#pragma comment (lib, "d3d11.lib") -#include - -#include - -/* Driver types supported */ -D3D_DRIVER_TYPE DriverTypes[] = -{ - D3D_DRIVER_TYPE_HARDWARE, - D3D_DRIVER_TYPE_WARP, - D3D_DRIVER_TYPE_REFERENCE, -}; -UINT NumDriverTypes = ARRAYSIZE(DriverTypes); - -D3D_FEATURE_LEVEL FeatureLevels[] = -{ - D3D_FEATURE_LEVEL_11_0, - D3D_FEATURE_LEVEL_10_1, - D3D_FEATURE_LEVEL_10_0, - D3D_FEATURE_LEVEL_9_1 -}; - -UINT NumFeatureLevels = ARRAYSIZE(FeatureLevels); - -D3D_FEATURE_LEVEL FeatureLevel; - -ID3D11Device* gDevice = NULL; -ID3D11DeviceContext* gContext = NULL; -IDXGIOutputDuplication* gOutputDuplication = NULL; - -IDXGISurface* surf = NULL; -ID3D11Texture2D* sStage = NULL; - -DXGI_OUTDUPL_FRAME_INFO FrameInfo; - -class WDDM { -public: - int wf_dxgi_init(UINT screenID, RECT screen) - { - //not sure if needed - gAcquiredDesktopImage = NULL; - - this->screen = screen; - - if (wf_dxgi_createDevice() != 0) - { - return 1; - } - - if (wf_dxgi_getDuplication(screenID) != 0) - { - return 1; - } - - return 0; - - } - int wf_dxgi_createDevice() - { - HRESULT status; - UINT DriverTypeIndex; - - for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex) - { - /*status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, D3D11_CREATE_DEVICE_DEBUG, FeatureLevels, NumFeatureLevels, - D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext); - */ - status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, NULL, FeatureLevels, NumFeatureLevels, - D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext); - if (SUCCEEDED(status)) - break; - - _tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]); - } - - if (FAILED(status)) - { - _tprintf(_T("Failed to create device in InitializeDx\n")); - return 1; - - //debug - /* - for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex) - { - status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, NULL, FeatureLevels, NumFeatureLevels, - D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext); - if (SUCCEEDED(status)) - break; - - _tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]); - } - - if (FAILED(status)) - { - _tprintf(_T("Failed to create device in InitializeDx\n")); - return 1; - } - */ - } - - return 0; - } - - int wf_dxgi_getDuplication(UINT screenID) - { - HRESULT status; - UINT dTop, i = 0; - DXGI_OUTPUT_DESC desc; - IDXGIOutput * pOutput; - IDXGIDevice* DxgiDevice = NULL; - IDXGIAdapter* DxgiAdapter = NULL; - IDXGIOutput* DxgiOutput = NULL; - IDXGIOutput1* DxgiOutput1 = NULL; - - status = gDevice->QueryInterface(__uuidof(IDXGIDevice), (void**)&DxgiDevice); - - if (FAILED(status)) - { - _tprintf(_T("Failed to get QI for DXGI Device\n")); - return 1; - } - - status = DxgiDevice->GetParent(__uuidof(IDXGIAdapter), (void**)&DxgiAdapter); - DxgiDevice->Release(); - DxgiDevice = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get parent DXGI Adapter\n")); - return 1; - } - - ZeroMemory(&desc, sizeof(desc)); - pOutput = NULL; - - while (DxgiAdapter->EnumOutputs(i, &pOutput) != DXGI_ERROR_NOT_FOUND) - { - DXGI_OUTPUT_DESC* pDesc = &desc; - - status = pOutput->GetDesc(pDesc); - - if (FAILED(status)) - { - _tprintf(_T("Failed to get description\n")); - return 1; - } - - wprintf(L"Output %d: [%s] [%s] (%d, %d, %d, %d)\n", i, pDesc->DeviceName, pDesc->AttachedToDesktop ? L"attached" : L"not attached", - pDesc->DesktopCoordinates.left, pDesc->DesktopCoordinates.top, pDesc->DesktopCoordinates.right, pDesc->DesktopCoordinates.bottom); - - if (pDesc->AttachedToDesktop) - dTop = i; - - pOutput->Release(); - ++i; - } - - dTop = screenID; - - status = DxgiAdapter->EnumOutputs(dTop, &DxgiOutput); - DxgiAdapter->Release(); - DxgiAdapter = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get output\n")); - return 1; - } - - status = DxgiOutput->QueryInterface(__uuidof(DxgiOutput1), (void**)&DxgiOutput1); - DxgiOutput->Release(); - DxgiOutput = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get IDXGIOutput1\n")); - return 1; - } - - status = DxgiOutput1->DuplicateOutput(gDevice, &gOutputDuplication); - DxgiOutput1->Release(); - DxgiOutput1 = NULL; - - if (FAILED(status)) - { - if (status == DXGI_ERROR_NOT_CURRENTLY_AVAILABLE) - { - _tprintf(_T("There is already the maximum number of applications using the Desktop Duplication API running, please close one of those applications and then try again.\n")); - return 1; - } - - _tprintf(_T("Failed to get duplicate output\n")); - return 1; - } - - return 0; - } - int wf_dxgi_cleanup() - { - if (framesWaiting > 0) - { - wf_dxgi_releasePixelData(); - } - - if (gAcquiredDesktopImage) - { - gAcquiredDesktopImage->Release(); - gAcquiredDesktopImage = NULL; - } - - if (gOutputDuplication) - { - gOutputDuplication->Release(); - gOutputDuplication = NULL; - } - - if (gContext) - { - gContext->Release(); - gContext = NULL; - } - - if (gDevice) - { - gDevice->Release(); - gDevice = NULL; - } - - return 0; - } - - int wf_dxgi_nextFrame(UINT timeout) - { - HRESULT status = 0; - UINT i = 0; - UINT DataBufferSize = 0; - BYTE* DataBuffer = NULL; - IDXGIResource* DesktopResource = NULL; - - if (framesWaiting > 0) - { - wf_dxgi_releasePixelData(); - } - - if (gAcquiredDesktopImage) - { - gAcquiredDesktopImage->Release(); - gAcquiredDesktopImage = NULL; - } - - status = gOutputDuplication->AcquireNextFrame(timeout, &FrameInfo, &DesktopResource); - - if (status == DXGI_ERROR_WAIT_TIMEOUT) - { - return 1; - } - - if (FAILED(status)) - { - if (status == DXGI_ERROR_ACCESS_LOST) - { - _tprintf(_T("Failed to acquire next frame with status=%#X\n"), status); - _tprintf(_T("Trying to reinitialize due to ACCESS LOST...")); - wf_dxgi_getDuplication(0); - } - else - { - _tprintf(_T("Failed to acquire next frame with status=%#X\n"), status); - _tprintf(_T("\tAccumulated Frames: %d\n\tRects: %d\n\tBuffSize: %d\n"), - FrameInfo.AccumulatedFrames, - FrameInfo.RectsCoalesced, - FrameInfo.TotalMetadataBufferSize); - - status = gOutputDuplication->ReleaseFrame(); - - if (FAILED(status)) - { - _tprintf(_T("Failed to release frame with status=%d\n"), status); - } - - return 1; - } - } - - status = DesktopResource->QueryInterface(__uuidof(ID3D11Texture2D), (void**)&gAcquiredDesktopImage); - DesktopResource->Release(); - DesktopResource = NULL; - - if (FAILED(status)) - { - return 1; - } - - framesWaiting = FrameInfo.AccumulatedFrames; - - return 0; - } - - int wf_dxgi_getPixelData(BYTE** data, int* pitch, RECT* invalid) - { - HRESULT status; - D3D11_BOX Box; - DXGI_MAPPED_RECT mappedRect; - D3D11_TEXTURE2D_DESC tDesc; - - tDesc.Width = (invalid->right - invalid->left); - tDesc.Height = (invalid->bottom - invalid->top); - tDesc.MipLevels = 1; - tDesc.ArraySize = 1; - tDesc.Format = DXGI_FORMAT_B8G8R8A8_UNORM; - tDesc.SampleDesc.Count = 1; - tDesc.SampleDesc.Quality = 0; - tDesc.Usage = D3D11_USAGE_STAGING; - tDesc.BindFlags = 0; - tDesc.CPUAccessFlags = D3D11_CPU_ACCESS_READ; - tDesc.MiscFlags = 0; - - INT OffsetX = screen.left; - INT OffsetY = screen.top; - - Box.top = invalid->top - OffsetY; - Box.left = invalid->left - OffsetX; - Box.right = invalid->right - OffsetX; - Box.bottom = invalid->bottom - OffsetY; - Box.front = 0; - Box.back = 1; - - status = gDevice->CreateTexture2D(&tDesc, NULL, &sStage); - - if (FAILED(status)) - { - _tprintf(_T("Failed to create staging surface\n")); - exit(1); - return 1; - } - - gContext->CopySubresourceRegion(sStage, 0, 0, 0, 0, gAcquiredDesktopImage, 0, &Box); - - status = sStage->QueryInterface(__uuidof(IDXGISurface), (void**)&surf); - - if (FAILED(status)) - { - _tprintf(_T("Failed to QI staging surface\n")); - exit(1); - return 1; - } - - surf->Map(&mappedRect, DXGI_MAP_READ); - - if (FAILED(status)) - { - _tprintf(_T("Failed to map staging surface\n")); - exit(1); - return 1; - } - - *data = mappedRect.pBits; - *pitch = mappedRect.Pitch; - - return 0; - } - - int wf_dxgi_releasePixelData() - { - HRESULT status; - - if (surf) { - surf->Unmap(); - surf->Release(); - surf = NULL; - } - if (sStage) { - sStage->Release(); - sStage = NULL; - } - - status = gOutputDuplication->ReleaseFrame(); - - if (FAILED(status)) - { - _tprintf(_T("Failed to release frame\n")); - return 1; - } - - framesWaiting = 0; - - return 0; - } -private: - ID3D11Texture2D* gAcquiredDesktopImage; - int framesWaiting; - RECT screen; -}; \ No newline at end of file diff --git a/rdp-acceleraed/WindowsCompileGuide.md b/rdp-acceleraed/WindowsCompileGuide.md deleted file mode 100644 index 21970b8e75..0000000000 --- a/rdp-acceleraed/WindowsCompileGuide.md +++ /dev/null @@ -1,49 +0,0 @@ -###To compile the server in windows WITH NVIDIA card### -- Install BOOST - - http://www.boost.org/users/download/ - - I downloaded boost_1_69_0-msvc-14.1-64.exe from https://sourceforge.net/projects/boost/files/boost-binaries/1.69.0/ for Visual Studio 2017 -- Install CMAKE, I took cmake-3.13.3-win64-x64.msi - - http://www.cmake.org/install/ -- Install Nvidia CUDA 10.0 from https://developer.nvidia.com/cuda-downloads -- Open CMAKE - - In the field: where is the source code, have the path to the subfolder Server from RPI-GPU-rdpClient git. - - In the field: Where to build the binaries, make a subfolder build under Server - - Press configure, I selected "Visual Studio 15 2017 Win64" - - Click on Add Entry and enter BOOST_ROOT to the root of the Boost folder "C:\local\boost_1_69_0" - - Do the same for BOOST_LIBRARYDIR and set it to "C:\local\boost_1_69_0\lib64-msvc-14.1" - - I had to set CUDA_TOOLKIT_ROOT_DIR to "C:/Program Files/NVIDIA GPU Computing Toolkit/CUDA/v10.0" - - Configure and Generate - - It should look like the following: - - ![ScreenShot](https://i.imgur.com/Htlr9NP.png) -- Open Server\build\server.sln in Visual Studio - - Select Release and Build the Solution -- Open a command prompt and cd to Server\build\Release - - Run "server monitor 0 port 8080" - -###To compile the server in windows WITHOUT NVIDIA card### -Note, the FPS will be significantly lower without a NVIDIA card, around 10FPS depending on the CPU. -- Install BOOST - - http://www.boost.org/users/download/ - - I downloaded boost_1_60_0-msvc-10.0-32.exe from https://sourceforge.net/projects/boost/files/boost-binaries/1.60.0/ for Visual Studio 2010 -- Install CMAKE, I took cmake-3.5.0-rc3-win32-x86.msi - - http://www.cmake.org/install/ -- Open CMAKE - - In the field: where is the source code, have the path to the subfolder Server from RPI-GPU-rdpClient git. - - In the field: Where to build the binaries, make a subfolder build under Server - - Press configure, I selected "Visual Studio 10 2010" - - Click on Add Entry and enter BOOST_ROOT to the root of the Boost folder "C:/local/boost_1_60_0" - - Do the same for BOOST_LIBRARYDIR and set it to "C:/local/boost_1_60_0/lib32-msvc-10.0" - - Download FFMPEG from http://ffmpeg.zeranoe.com/builds/, need the dev and shared - - Set FFMPEG_ROOT to the root of FFMPEG dev folder with the README.txt - - In my case "RPI-GPU-rdpClient\ffmpeg\ffmpeg-20160307-git-6f5048f-win32-dev" - - Add the bin folder of the shared zip to your path, or copy the DLLs - - Uncheck USE_CUDA and USE_NVENC - - Only keep USE_WDDM if you have Windows 8.0 or up - - Compile and Generate - - It should look like the following: - - ![ScreenShot](http://i.imgur.com/485jCoE.png) -- Open Server\build\server.sln in Visual Studio - - Select Release and Build the Solution -- Open a command prompt and cd to Server\build\Release - - Run "server monitor 0 port 8080" -- If missing [inttypes.h], check http://stackoverflow.com/questions/13266868/ffmpeg-inttypes-h-not-found-error diff --git a/rdp-acceleraed/win8-wddm/win8-wddm.sln b/rdp-acceleraed/win8-wddm/win8-wddm.sln deleted file mode 100644 index bdbb0c98af..0000000000 --- a/rdp-acceleraed/win8-wddm/win8-wddm.sln +++ /dev/null @@ -1,20 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 11.00 -# Visual Studio 2010 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "win8-wddm", "win8-wddm\win8-wddm.vcxproj", "{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Release|Win32 = Release|Win32 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Debug|Win32.ActiveCfg = Debug|Win32 - {293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Debug|Win32.Build.0 = Debug|Win32 - {293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Release|Win32.ActiveCfg = Release|Win32 - {293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Release|Win32.Build.0 = Release|Win32 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection -EndGlobal diff --git a/rdp-acceleraed/win8-wddm/win8-wddm/main.cpp b/rdp-acceleraed/win8-wddm/win8-wddm/main.cpp deleted file mode 100644 index e06209ef1b..0000000000 --- a/rdp-acceleraed/win8-wddm/win8-wddm/main.cpp +++ /dev/null @@ -1,30 +0,0 @@ - -#pragma comment (lib, "d3d11.lib") -#pragma comment (lib, "Dxgi.lib") - - -#include -#include "wddm.h" - -using namespace std; - -int main(int argc, const char* argv[]) { - WDDM wddm; - - wddm.wf_dxgi_init(); - - byte* data; - int pitch; - RECT rect; - rect.left=0; - rect.top=0; - rect.bottom=600; - rect.right=600; - while(true) { - wddm.wf_dxgi_getPixelData(&data, &pitch, &rect); - } - - system("pause"); - - wddm.wf_dxgi_cleanup(); -} \ No newline at end of file diff --git a/rdp-acceleraed/win8-wddm/win8-wddm/wddm.h b/rdp-acceleraed/win8-wddm/win8-wddm/wddm.h deleted file mode 100644 index dd68b26cdf..0000000000 --- a/rdp-acceleraed/win8-wddm/win8-wddm/wddm.h +++ /dev/null @@ -1,383 +0,0 @@ -#pragma once - -//#pragma comment (lib, "d3dx11.lib") -//#pragma comment (lib, "d3dx10.lib") - -#include -#include - -//#define CINTERFACE - -#include -#include -#include - -#include - -/* Driver types supported */ -D3D_DRIVER_TYPE DriverTypes[] = -{ - D3D_DRIVER_TYPE_HARDWARE, - D3D_DRIVER_TYPE_WARP, - D3D_DRIVER_TYPE_REFERENCE, -}; -UINT NumDriverTypes = ARRAYSIZE(DriverTypes); - -D3D_FEATURE_LEVEL FeatureLevels[] = -{ - D3D_FEATURE_LEVEL_11_0, - D3D_FEATURE_LEVEL_10_1, - D3D_FEATURE_LEVEL_10_0, - D3D_FEATURE_LEVEL_9_1 -}; - -UINT NumFeatureLevels = ARRAYSIZE(FeatureLevels); - -D3D_FEATURE_LEVEL FeatureLevel; - -ID3D11Device* gDevice = NULL; -ID3D11DeviceContext* gContext = NULL; -IDXGIOutputDuplication* gOutputDuplication = NULL; - -IDXGISurface* surf; -ID3D11Texture2D* sStage; - -DXGI_OUTDUPL_FRAME_INFO FrameInfo; - -class WDDM { -public: - int wf_dxgi_init() - { - //not sure if needed - gAcquiredDesktopImage = NULL; - - if (wf_dxgi_createDevice() != 0) - { - return 1; - } - - if (wf_dxgi_getDuplication(0) != 0) - { - return 1; - } - - return 0; - - } - int wf_dxgi_createDevice() - { - HRESULT status; - UINT DriverTypeIndex; - - for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex) - { - status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, 0, FeatureLevels, NumFeatureLevels, - D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext); - if (SUCCEEDED(status)) - break; - - _tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]); - } - - if (FAILED(status)) - { - _tprintf(_T("Failed to create device in InitializeDx\n")); - return 1; - } - - return 0; - } - - int wf_dxgi_getDuplication(UINT screenID) - { - HRESULT status; - UINT i = 0; - DXGI_OUTPUT_DESC desc; - IDXGIOutput * pOutput; - IDXGIDevice* DxgiDevice = NULL; - IDXGIAdapter* DxgiAdapter = NULL; - IDXGIOutput* DxgiOutput = NULL; - IDXGIOutput1* DxgiOutput1 = NULL; - - status = gDevice->QueryInterface(__uuidof(IDXGIDevice), (void**) &DxgiDevice); - - if (FAILED(status)) - { - _tprintf(_T("Failed to get QI for DXGI Device\n")); - return 1; - } - - status = DxgiDevice->GetParent(__uuidof(IDXGIAdapter), (void**) &DxgiAdapter); - DxgiDevice->Release(); - DxgiDevice = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get parent DXGI Adapter\n")); - return 1; - } - - ZeroMemory(&desc, sizeof(desc)); - pOutput = NULL; - - while (DxgiAdapter->EnumOutputs(i, &pOutput) != DXGI_ERROR_NOT_FOUND) - { - DXGI_OUTPUT_DESC* pDesc = &desc; - - status = pOutput->GetDesc(pDesc); - - if (FAILED(status)) - { - _tprintf(_T("Failed to get description\n")); - return 1; - } - - _tprintf(_T("Output %d: [%s] [%d]\n"), i, pDesc->DeviceName, pDesc->AttachedToDesktop); - - /*if (pDesc->AttachedToDesktop) - dTop = i;*/ - - pOutput->Release(); - ++i; - } - - status = DxgiAdapter->EnumOutputs(screenID, &DxgiOutput); - DxgiAdapter->Release(); - DxgiAdapter = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get output\n")); - return 1; - } - - status = DxgiOutput->QueryInterface(__uuidof(IDXGIOutput1), (void**) &DxgiOutput1); - DxgiOutput->Release(); - DxgiOutput = NULL; - - if (FAILED(status)) - { - _tprintf(_T("Failed to get IDXGIOutput1\n")); - return 1; - } - - status = DxgiOutput1->DuplicateOutput((IUnknown*)gDevice, &gOutputDuplication); - DxgiOutput1->Release(); - DxgiOutput1 = NULL; - - if (FAILED(status)) - { - if (status == DXGI_ERROR_NOT_CURRENTLY_AVAILABLE) - { - _tprintf(_T("There is already the maximum number of applications using the Desktop Duplication API running, please close one of those applications and then try again.\n")); - return 1; - } - - _tprintf(_T("Failed to get duplicate output. Status = %#X\n"), status); - return 1; - } - - return 0; - } - int wf_dxgi_cleanup() - { - /*if (framesWaiting > 0) - { - wf_dxgi_releasePixelData(wfi); - }*/ - - if (gAcquiredDesktopImage) - { - gAcquiredDesktopImage->Release(); - gAcquiredDesktopImage = NULL; - } - - if (gOutputDuplication) - { - gOutputDuplication->Release(); - gOutputDuplication = NULL; - } - - if(gContext) - { - gContext->Release(); - gContext = NULL; - } - - if(gDevice) - { - gDevice->Release(); - gDevice = NULL; - } - - return 0; - } - - int wf_dxgi_nextFrame(UINT timeout) - { - HRESULT status = 0; - UINT i = 0; - UINT DataBufferSize = 0; - BYTE* DataBuffer = NULL; - IDXGIResource* DesktopResource = NULL; - - if (gAcquiredDesktopImage) - { - gAcquiredDesktopImage->Release(); - gAcquiredDesktopImage = NULL; - } - - status = gOutputDuplication->AcquireNextFrame(timeout, &FrameInfo, &DesktopResource); - - if (status == DXGI_ERROR_WAIT_TIMEOUT) - { - return 1; - } - - if (FAILED(status)) - { - if (status == DXGI_ERROR_ACCESS_LOST) - { - _tprintf(_T("Failed to acquire next frame with status=%#X\n"), status); - _tprintf(_T("Trying to reinitialize due to ACCESS LOST...")); - if (gAcquiredDesktopImage) - { - gAcquiredDesktopImage->Release(); - gAcquiredDesktopImage = NULL; - } - - if (gOutputDuplication) - { - gOutputDuplication->Release(); - gOutputDuplication = NULL; - } - - wf_dxgi_getDuplication(0); // TODO - - return 1; - } - else - { - _tprintf(_T("Failed to acquire next frame with status=%#X\n"), status); - - status = gOutputDuplication->ReleaseFrame(); - - if (FAILED(status)) - { - _tprintf(_T("Failed to release frame with status=%d\n"), status); - } - - return 1; - } - } - - status = DesktopResource->QueryInterface(__uuidof(ID3D11Texture2D), (void**) &gAcquiredDesktopImage); - DesktopResource->Release(); - DesktopResource = NULL; - - if (FAILED(status)) - { - return 1; - } - - //wfi->framesWaiting = FrameInfo.AccumulatedFrames; - - if (FrameInfo.AccumulatedFrames == 0) - { - status = gOutputDuplication->ReleaseFrame(); - - if (FAILED(status)) - { - _tprintf(_T("Failed to release frame with status=%d\n"), status); - } - } - - return 0; - } - - int wf_dxgi_getPixelData(BYTE** data, int* pitch, RECT* invalid) - { - HRESULT status; - D3D11_BOX Box; - DXGI_MAPPED_RECT mappedRect; - D3D11_TEXTURE2D_DESC tDesc; - - tDesc.Width = (invalid->right - invalid->left); - tDesc.Height = (invalid->bottom - invalid->top); - tDesc.MipLevels = 1; - tDesc.ArraySize = 1; - tDesc.Format = DXGI_FORMAT_B8G8R8A8_UNORM; - tDesc.SampleDesc.Count = 1; - tDesc.SampleDesc.Quality = 0; - tDesc.Usage = D3D11_USAGE_STAGING; - tDesc.BindFlags = 0; - tDesc.CPUAccessFlags = D3D11_CPU_ACCESS_READ; - tDesc.MiscFlags = 0; - - Box.top = invalid->top; - Box.left = invalid->left; - Box.right = invalid->right; - Box.bottom = invalid->bottom; - Box.front = 0; - Box.back = 1; - - status = gDevice->CreateTexture2D(&tDesc, NULL, &sStage); - - if (FAILED(status)) - { - _tprintf(_T("Failed to create staging surface\n")); - exit(1); - return 1; - } - - gContext->CopySubresourceRegion((ID3D11Resource*) sStage, 0,0,0,0, (ID3D11Resource*) gAcquiredDesktopImage, 0, &Box); - - status = sStage->QueryInterface(_uuidof(IDXGISurface), (void**) &surf); - - if (FAILED(status)) - { - _tprintf(_T("Failed to QI staging surface\n")); - exit(1); - return 1; - } - - surf->Map(&mappedRect, DXGI_MAP_READ); - - if (FAILED(status)) - { - _tprintf(_T("Failed to map staging surface\n")); - exit(1); - return 1; - } - - *data = mappedRect.pBits; - *pitch = mappedRect.Pitch; - - return 0; - } - - int wf_dxgi_releasePixelData() - { - HRESULT status; - - surf->Unmap(); - surf->Release(); - surf = NULL; - sStage->Release(); - sStage = NULL; - - status = gOutputDuplication->ReleaseFrame(); - - if (FAILED(status)) - { - _tprintf(_T("Failed to release frame\n")); - return 1; - } - - //wfi->framesWaiting = 0; - - return 0; - } -private: - ID3D11Texture2D* gAcquiredDesktopImage; -}; \ No newline at end of file diff --git a/rdp-acceleraed/win8-wddm/win8-wddm/win8-wddm.vcxproj.filters b/rdp-acceleraed/win8-wddm/win8-wddm/win8-wddm.vcxproj.filters deleted file mode 100644 index 9e3511bf59..0000000000 --- a/rdp-acceleraed/win8-wddm/win8-wddm/win8-wddm.vcxproj.filters +++ /dev/null @@ -1,27 +0,0 @@ - - - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - - - Source Files - - - - - Header Files - - - \ No newline at end of file diff --git a/temp-telegraf/README.md b/temp-telegraf/README.md deleted file mode 100644 index f7080b14d2..0000000000 --- a/temp-telegraf/README.md +++ /dev/null @@ -1,37 +0,0 @@ -# raspberrypi-temperature-telegraf -Collect RaspberryPi CPU and GPU temperature with telegraf - -### How to use (No script required :fire:) -1. Add this to you telegraf.conf -``` -[[inputs.file]] - files = ["/sys/class/thermal/thermal_zone0/temp"] - name_override = "cpu_temperature" - data_format = "value" - data_type = "integer" - -[[inputs.exec]] - commands = [ "/opt/vc/bin/vcgencmd measure_temp" ] - name_override = "gpu_temperature" - data_format = "grok" - grok_patterns = ["%{NUMBER:value:float}"] - -``` -2. Add telegraf user to video group ```sudo usermod -a -G video telegraf``` -3. ```sudo service telegraf stop;sudo service telegraf start``` -4. Run test ```telegraf -config /etc/telegraf/telegraf.conf -test``` - -### How to use (Old way) -1. Copy ```telegraf_pi_temp.sh``` to ```/usr/local/bin/telegraf_pi_temp.sh``` -2. Modify file permissions ```chmod +x /usr/local/bin/telegraf_pi_temp.sh``` -3. Add ```telegraf``` user to video group ```sudo usermod -a -G video telegraf``` -4. ```sudo service telegraf restart``` or ```sudo reboot``` -5. Add to your telegraf.conf snippet from ```telegraf.conf``` -6. Run test ```telegraf -config /etc/telegraf/telegraf.conf -test``` - -### Data format -To get a human readable *cpu* temperature divide it by 1000 (in grafana use the math(/ 1000) function -```json -{"cpu":54768, "gpu":54.8} -``` - diff --git a/temp-telegraf/telegraf.conf b/temp-telegraf/telegraf.conf deleted file mode 100644 index b267f5da0c..0000000000 --- a/temp-telegraf/telegraf.conf +++ /dev/null @@ -1,5 +0,0 @@ -[[inputs.exec]] - commands = ["/usr/local/bin/telegraf_pi_temp.sh"] - timeout = "5s" - data_format = "json" - name_suffix = "_pi_temp" \ No newline at end of file diff --git a/temp-telegraf/telegraf_pi_temp.sh b/temp-telegraf/telegraf_pi_temp.sh deleted file mode 100644 index 89d1023596..0000000000 --- a/temp-telegraf/telegraf_pi_temp.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash -prefix="temp=" -suffix="'C" -gpu=$(/opt/vc/bin/vcgencmd measure_temp) -gpu_temp=${gpu#$prefix} -gpu_temp=${gpu_temp%$suffix} -echo -e "{\"cpu\":"$(