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20 lines
449 B
20 lines
449 B
3 years ago
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MIO pin configuration defines for Xilinx ZynqMP
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*
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* Copyright (C) 2020 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
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#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
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/* Bit value for different voltage levels */
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#define IO_STANDARD_LVCMOS33 0
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#define IO_STANDARD_LVCMOS18 1
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/* Bit values for Slew Rates */
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#define SLEW_RATE_FAST 0
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#define SLEW_RATE_SLOW 1
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#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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